xref: /OK3568_Linux_fs/kernel/drivers/char/hw_random/stm32-rng.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2015, Daniel Thompson
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/hw_random.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/iopoll.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/of_platform.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/reset.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define RNG_CR 0x00
20*4882a593Smuzhiyun #define RNG_CR_RNGEN BIT(2)
21*4882a593Smuzhiyun #define RNG_CR_CED BIT(5)
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define RNG_SR 0x04
24*4882a593Smuzhiyun #define RNG_SR_SEIS BIT(6)
25*4882a593Smuzhiyun #define RNG_SR_CEIS BIT(5)
26*4882a593Smuzhiyun #define RNG_SR_DRDY BIT(0)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define RNG_DR 0x08
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct stm32_rng_private {
31*4882a593Smuzhiyun 	struct hwrng rng;
32*4882a593Smuzhiyun 	void __iomem *base;
33*4882a593Smuzhiyun 	struct clk *clk;
34*4882a593Smuzhiyun 	struct reset_control *rst;
35*4882a593Smuzhiyun 	bool ced;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
stm32_rng_read(struct hwrng * rng,void * data,size_t max,bool wait)38*4882a593Smuzhiyun static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	struct stm32_rng_private *priv =
41*4882a593Smuzhiyun 	    container_of(rng, struct stm32_rng_private, rng);
42*4882a593Smuzhiyun 	u32 sr;
43*4882a593Smuzhiyun 	int retval = 0;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	pm_runtime_get_sync((struct device *) priv->rng.priv);
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	while (max > sizeof(u32)) {
48*4882a593Smuzhiyun 		sr = readl_relaxed(priv->base + RNG_SR);
49*4882a593Smuzhiyun 		/* Manage timeout which is based on timer and take */
50*4882a593Smuzhiyun 		/* care of initial delay time when enabling rng	*/
51*4882a593Smuzhiyun 		if (!sr && wait) {
52*4882a593Smuzhiyun 			retval = readl_relaxed_poll_timeout_atomic(priv->base
53*4882a593Smuzhiyun 								   + RNG_SR,
54*4882a593Smuzhiyun 								   sr, sr,
55*4882a593Smuzhiyun 								   10, 50000);
56*4882a593Smuzhiyun 			if (retval)
57*4882a593Smuzhiyun 				dev_err((struct device *)priv->rng.priv,
58*4882a593Smuzhiyun 					"%s: timeout %x!\n", __func__, sr);
59*4882a593Smuzhiyun 		}
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 		/* If error detected or data not ready... */
62*4882a593Smuzhiyun 		if (sr != RNG_SR_DRDY) {
63*4882a593Smuzhiyun 			if (WARN_ONCE(sr & (RNG_SR_SEIS | RNG_SR_CEIS),
64*4882a593Smuzhiyun 					"bad RNG status - %x\n", sr))
65*4882a593Smuzhiyun 				writel_relaxed(0, priv->base + RNG_SR);
66*4882a593Smuzhiyun 			break;
67*4882a593Smuzhiyun 		}
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 		*(u32 *)data = readl_relaxed(priv->base + RNG_DR);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 		retval += sizeof(u32);
72*4882a593Smuzhiyun 		data += sizeof(u32);
73*4882a593Smuzhiyun 		max -= sizeof(u32);
74*4882a593Smuzhiyun 	}
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	pm_runtime_mark_last_busy((struct device *) priv->rng.priv);
77*4882a593Smuzhiyun 	pm_runtime_put_sync_autosuspend((struct device *) priv->rng.priv);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	return retval || !wait ? retval : -EIO;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
stm32_rng_init(struct hwrng * rng)82*4882a593Smuzhiyun static int stm32_rng_init(struct hwrng *rng)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct stm32_rng_private *priv =
85*4882a593Smuzhiyun 	    container_of(rng, struct stm32_rng_private, rng);
86*4882a593Smuzhiyun 	int err;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	err = clk_prepare_enable(priv->clk);
89*4882a593Smuzhiyun 	if (err)
90*4882a593Smuzhiyun 		return err;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	if (priv->ced)
93*4882a593Smuzhiyun 		writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
94*4882a593Smuzhiyun 	else
95*4882a593Smuzhiyun 		writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
96*4882a593Smuzhiyun 			       priv->base + RNG_CR);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	/* clear error indicators */
99*4882a593Smuzhiyun 	writel_relaxed(0, priv->base + RNG_SR);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
stm32_rng_cleanup(struct hwrng * rng)104*4882a593Smuzhiyun static void stm32_rng_cleanup(struct hwrng *rng)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct stm32_rng_private *priv =
107*4882a593Smuzhiyun 	    container_of(rng, struct stm32_rng_private, rng);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	writel_relaxed(0, priv->base + RNG_CR);
110*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
stm32_rng_probe(struct platform_device * ofdev)113*4882a593Smuzhiyun static int stm32_rng_probe(struct platform_device *ofdev)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	struct device *dev = &ofdev->dev;
116*4882a593Smuzhiyun 	struct device_node *np = ofdev->dev.of_node;
117*4882a593Smuzhiyun 	struct stm32_rng_private *priv;
118*4882a593Smuzhiyun 	struct resource res;
119*4882a593Smuzhiyun 	int err;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);
122*4882a593Smuzhiyun 	if (!priv)
123*4882a593Smuzhiyun 		return -ENOMEM;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	err = of_address_to_resource(np, 0, &res);
126*4882a593Smuzhiyun 	if (err)
127*4882a593Smuzhiyun 		return err;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	priv->base = devm_ioremap_resource(dev, &res);
130*4882a593Smuzhiyun 	if (IS_ERR(priv->base))
131*4882a593Smuzhiyun 		return PTR_ERR(priv->base);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	priv->clk = devm_clk_get(&ofdev->dev, NULL);
134*4882a593Smuzhiyun 	if (IS_ERR(priv->clk))
135*4882a593Smuzhiyun 		return PTR_ERR(priv->clk);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	priv->rst = devm_reset_control_get(&ofdev->dev, NULL);
138*4882a593Smuzhiyun 	if (!IS_ERR(priv->rst)) {
139*4882a593Smuzhiyun 		reset_control_assert(priv->rst);
140*4882a593Smuzhiyun 		udelay(2);
141*4882a593Smuzhiyun 		reset_control_deassert(priv->rst);
142*4882a593Smuzhiyun 	}
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	priv->ced = of_property_read_bool(np, "clock-error-detect");
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	dev_set_drvdata(dev, priv);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	priv->rng.name = dev_driver_string(dev);
149*4882a593Smuzhiyun #ifndef CONFIG_PM
150*4882a593Smuzhiyun 	priv->rng.init = stm32_rng_init;
151*4882a593Smuzhiyun 	priv->rng.cleanup = stm32_rng_cleanup;
152*4882a593Smuzhiyun #endif
153*4882a593Smuzhiyun 	priv->rng.read = stm32_rng_read;
154*4882a593Smuzhiyun 	priv->rng.priv = (unsigned long) dev;
155*4882a593Smuzhiyun 	priv->rng.quality = 900;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	pm_runtime_set_autosuspend_delay(dev, 100);
158*4882a593Smuzhiyun 	pm_runtime_use_autosuspend(dev);
159*4882a593Smuzhiyun 	pm_runtime_enable(dev);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	return devm_hwrng_register(dev, &priv->rng);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
stm32_rng_remove(struct platform_device * ofdev)164*4882a593Smuzhiyun static int stm32_rng_remove(struct platform_device *ofdev)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	pm_runtime_disable(&ofdev->dev);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #ifdef CONFIG_PM
stm32_rng_runtime_suspend(struct device * dev)172*4882a593Smuzhiyun static int stm32_rng_runtime_suspend(struct device *dev)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	struct stm32_rng_private *priv = dev_get_drvdata(dev);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	stm32_rng_cleanup(&priv->rng);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return 0;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
stm32_rng_runtime_resume(struct device * dev)181*4882a593Smuzhiyun static int stm32_rng_runtime_resume(struct device *dev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct stm32_rng_private *priv = dev_get_drvdata(dev);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return stm32_rng_init(&priv->rng);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun #endif
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static const struct dev_pm_ops stm32_rng_pm_ops = {
190*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
191*4882a593Smuzhiyun 			   stm32_rng_runtime_resume, NULL)
192*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
193*4882a593Smuzhiyun 				pm_runtime_force_resume)
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun static const struct of_device_id stm32_rng_match[] = {
198*4882a593Smuzhiyun 	{
199*4882a593Smuzhiyun 		.compatible = "st,stm32-rng",
200*4882a593Smuzhiyun 	},
201*4882a593Smuzhiyun 	{},
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stm32_rng_match);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static struct platform_driver stm32_rng_driver = {
206*4882a593Smuzhiyun 	.driver = {
207*4882a593Smuzhiyun 		.name = "stm32-rng",
208*4882a593Smuzhiyun 		.pm = &stm32_rng_pm_ops,
209*4882a593Smuzhiyun 		.of_match_table = stm32_rng_match,
210*4882a593Smuzhiyun 	},
211*4882a593Smuzhiyun 	.probe = stm32_rng_probe,
212*4882a593Smuzhiyun 	.remove = stm32_rng_remove,
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun module_platform_driver(stm32_rng_driver);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun MODULE_LICENSE("GPL");
218*4882a593Smuzhiyun MODULE_AUTHOR("Daniel Thompson <daniel.thompson@linaro.org>");
219*4882a593Smuzhiyun MODULE_DESCRIPTION("STMicroelectronics STM32 RNG device driver");
220