1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2019 Nuvoton Technology corporation.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/kernel.h>
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/iopoll.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/random.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/hw_random.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/of_irq.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define NPCM_RNGCS_REG 0x00 /* Control and status register */
18*4882a593Smuzhiyun #define NPCM_RNGD_REG 0x04 /* Data register */
19*4882a593Smuzhiyun #define NPCM_RNGMODE_REG 0x08 /* Mode register */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define NPCM_RNG_CLK_SET_25MHZ GENMASK(4, 3) /* 20-25 MHz */
22*4882a593Smuzhiyun #define NPCM_RNG_DATA_VALID BIT(1)
23*4882a593Smuzhiyun #define NPCM_RNG_ENABLE BIT(0)
24*4882a593Smuzhiyun #define NPCM_RNG_M1ROSEL BIT(1)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define NPCM_RNG_TIMEOUT_USEC 20000
27*4882a593Smuzhiyun #define NPCM_RNG_POLL_USEC 1000
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define to_npcm_rng(p) container_of(p, struct npcm_rng, rng)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct npcm_rng {
32*4882a593Smuzhiyun void __iomem *base;
33*4882a593Smuzhiyun struct hwrng rng;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
npcm_rng_init(struct hwrng * rng)36*4882a593Smuzhiyun static int npcm_rng_init(struct hwrng *rng)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct npcm_rng *priv = to_npcm_rng(rng);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun writel(NPCM_RNG_CLK_SET_25MHZ | NPCM_RNG_ENABLE,
41*4882a593Smuzhiyun priv->base + NPCM_RNGCS_REG);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
npcm_rng_cleanup(struct hwrng * rng)46*4882a593Smuzhiyun static void npcm_rng_cleanup(struct hwrng *rng)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct npcm_rng *priv = to_npcm_rng(rng);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun writel(NPCM_RNG_CLK_SET_25MHZ, priv->base + NPCM_RNGCS_REG);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
npcm_rng_read(struct hwrng * rng,void * buf,size_t max,bool wait)53*4882a593Smuzhiyun static int npcm_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct npcm_rng *priv = to_npcm_rng(rng);
56*4882a593Smuzhiyun int retval = 0;
57*4882a593Smuzhiyun int ready;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun pm_runtime_get_sync((struct device *)priv->rng.priv);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun while (max) {
62*4882a593Smuzhiyun if (wait) {
63*4882a593Smuzhiyun if (readb_poll_timeout(priv->base + NPCM_RNGCS_REG,
64*4882a593Smuzhiyun ready,
65*4882a593Smuzhiyun ready & NPCM_RNG_DATA_VALID,
66*4882a593Smuzhiyun NPCM_RNG_POLL_USEC,
67*4882a593Smuzhiyun NPCM_RNG_TIMEOUT_USEC))
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun } else {
70*4882a593Smuzhiyun if ((readb(priv->base + NPCM_RNGCS_REG) &
71*4882a593Smuzhiyun NPCM_RNG_DATA_VALID) == 0)
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun *(u8 *)buf = readb(priv->base + NPCM_RNGD_REG);
76*4882a593Smuzhiyun retval++;
77*4882a593Smuzhiyun buf++;
78*4882a593Smuzhiyun max--;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun pm_runtime_mark_last_busy((struct device *)priv->rng.priv);
82*4882a593Smuzhiyun pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return retval || !wait ? retval : -EIO;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
npcm_rng_probe(struct platform_device * pdev)87*4882a593Smuzhiyun static int npcm_rng_probe(struct platform_device *pdev)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct npcm_rng *priv;
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
93*4882a593Smuzhiyun if (!priv)
94*4882a593Smuzhiyun return -ENOMEM;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun priv->base = devm_platform_ioremap_resource(pdev, 0);
97*4882a593Smuzhiyun if (IS_ERR(priv->base))
98*4882a593Smuzhiyun return PTR_ERR(priv->base);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, priv);
101*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
102*4882a593Smuzhiyun pm_runtime_use_autosuspend(&pdev->dev);
103*4882a593Smuzhiyun pm_runtime_enable(&pdev->dev);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #ifndef CONFIG_PM
106*4882a593Smuzhiyun priv->rng.init = npcm_rng_init;
107*4882a593Smuzhiyun priv->rng.cleanup = npcm_rng_cleanup;
108*4882a593Smuzhiyun #endif
109*4882a593Smuzhiyun priv->rng.name = pdev->name;
110*4882a593Smuzhiyun priv->rng.read = npcm_rng_read;
111*4882a593Smuzhiyun priv->rng.priv = (unsigned long)&pdev->dev;
112*4882a593Smuzhiyun priv->rng.quality = 1000;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun writel(NPCM_RNG_M1ROSEL, priv->base + NPCM_RNGMODE_REG);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun ret = devm_hwrng_register(&pdev->dev, &priv->rng);
117*4882a593Smuzhiyun if (ret) {
118*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register rng device: %d\n",
119*4882a593Smuzhiyun ret);
120*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
121*4882a593Smuzhiyun pm_runtime_set_suspended(&pdev->dev);
122*4882a593Smuzhiyun return ret;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
npcm_rng_remove(struct platform_device * pdev)128*4882a593Smuzhiyun static int npcm_rng_remove(struct platform_device *pdev)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun struct npcm_rng *priv = platform_get_drvdata(pdev);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun devm_hwrng_unregister(&pdev->dev, &priv->rng);
133*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
134*4882a593Smuzhiyun pm_runtime_set_suspended(&pdev->dev);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #ifdef CONFIG_PM
npcm_rng_runtime_suspend(struct device * dev)140*4882a593Smuzhiyun static int npcm_rng_runtime_suspend(struct device *dev)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct npcm_rng *priv = dev_get_drvdata(dev);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun npcm_rng_cleanup(&priv->rng);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
npcm_rng_runtime_resume(struct device * dev)149*4882a593Smuzhiyun static int npcm_rng_runtime_resume(struct device *dev)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun struct npcm_rng *priv = dev_get_drvdata(dev);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return npcm_rng_init(&priv->rng);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun #endif
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct dev_pm_ops npcm_rng_pm_ops = {
158*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(npcm_rng_runtime_suspend,
159*4882a593Smuzhiyun npcm_rng_runtime_resume, NULL)
160*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
161*4882a593Smuzhiyun pm_runtime_force_resume)
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const struct of_device_id rng_dt_id[] __maybe_unused = {
165*4882a593Smuzhiyun { .compatible = "nuvoton,npcm750-rng", },
166*4882a593Smuzhiyun {},
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rng_dt_id);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static struct platform_driver npcm_rng_driver = {
171*4882a593Smuzhiyun .driver = {
172*4882a593Smuzhiyun .name = "npcm-rng",
173*4882a593Smuzhiyun .pm = &npcm_rng_pm_ops,
174*4882a593Smuzhiyun .of_match_table = of_match_ptr(rng_dt_id),
175*4882a593Smuzhiyun },
176*4882a593Smuzhiyun .probe = npcm_rng_probe,
177*4882a593Smuzhiyun .remove = npcm_rng_remove,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun module_platform_driver(npcm_rng_driver);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun MODULE_DESCRIPTION("Nuvoton NPCM Random Number Generator Driver");
183*4882a593Smuzhiyun MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
184*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
185