1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* n2rng.h: Niagara2 RNG defines. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 David S. Miller <davem@davemloft.net> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _N2RNG_H 8*4882a593Smuzhiyun #define _N2RNG_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* ver1 devices - n2-rng, vf-rng, kt-rng */ 11*4882a593Smuzhiyun #define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */ 12*4882a593Smuzhiyun #define RNG_v1_CTL_WAIT_SHIFT 9 13*4882a593Smuzhiyun #define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */ 14*4882a593Smuzhiyun #define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */ 15*4882a593Smuzhiyun #define RNG_v1_CTL_VCO_SHIFT 6 16*4882a593Smuzhiyun #define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */ 17*4882a593Smuzhiyun #define RNG_v1_CTL_ASEL_SHIFT 4 18*4882a593Smuzhiyun #define RNG_v1_CTL_ASEL_NOOUT 2 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* these are the same in v2 as in v1 */ 21*4882a593Smuzhiyun #define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */ 22*4882a593Smuzhiyun #define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */ 23*4882a593Smuzhiyun #define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */ 24*4882a593Smuzhiyun #define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* ver2 devices - m4-rng, m7-rng */ 27*4882a593Smuzhiyun #define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */ 28*4882a593Smuzhiyun #define RNG_v2_CTL_WAIT_SHIFT 12 29*4882a593Smuzhiyun #define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */ 30*4882a593Smuzhiyun #define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */ 31*4882a593Smuzhiyun #define RNG_v2_CTL_VCO_SHIFT 9 32*4882a593Smuzhiyun #define RNG_v2_CTL_PERF 0x0000000000000180ULL /* Perf */ 33*4882a593Smuzhiyun #define RNG_v2_CTL_ASEL 0x0000000000000070ULL /* Analog MUX select */ 34*4882a593Smuzhiyun #define RNG_v2_CTL_ASEL_SHIFT 4 35*4882a593Smuzhiyun #define RNG_v2_CTL_ASEL_NOOUT 7 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define HV_FAST_RNG_GET_DIAG_CTL 0x130 39*4882a593Smuzhiyun #define HV_FAST_RNG_CTL_READ 0x131 40*4882a593Smuzhiyun #define HV_FAST_RNG_CTL_WRITE 0x132 41*4882a593Smuzhiyun #define HV_FAST_RNG_DATA_READ_DIAG 0x133 42*4882a593Smuzhiyun #define HV_FAST_RNG_DATA_READ 0x134 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define HV_RNG_STATE_UNCONFIGURED 0 45*4882a593Smuzhiyun #define HV_RNG_STATE_CONFIGURED 1 46*4882a593Smuzhiyun #define HV_RNG_STATE_HEALTHCHECK 2 47*4882a593Smuzhiyun #define HV_RNG_STATE_ERROR 3 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define HV_RNG_NUM_CONTROL 4 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 52*4882a593Smuzhiyun extern unsigned long sun4v_rng_get_diag_ctl(void); 53*4882a593Smuzhiyun extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra, 54*4882a593Smuzhiyun unsigned long *state, 55*4882a593Smuzhiyun unsigned long *tick_delta); 56*4882a593Smuzhiyun extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra, 57*4882a593Smuzhiyun unsigned long unit, 58*4882a593Smuzhiyun unsigned long *state, 59*4882a593Smuzhiyun unsigned long *tick_delta, 60*4882a593Smuzhiyun unsigned long *watchdog, 61*4882a593Smuzhiyun unsigned long *write_status); 62*4882a593Smuzhiyun extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra, 63*4882a593Smuzhiyun unsigned long state, 64*4882a593Smuzhiyun unsigned long write_timeout, 65*4882a593Smuzhiyun unsigned long *tick_delta); 66*4882a593Smuzhiyun extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra, 67*4882a593Smuzhiyun unsigned long state, 68*4882a593Smuzhiyun unsigned long write_timeout, 69*4882a593Smuzhiyun unsigned long unit); 70*4882a593Smuzhiyun extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra, 71*4882a593Smuzhiyun unsigned long len, 72*4882a593Smuzhiyun unsigned long *tick_delta); 73*4882a593Smuzhiyun extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra, 74*4882a593Smuzhiyun unsigned long len, 75*4882a593Smuzhiyun unsigned long unit, 76*4882a593Smuzhiyun unsigned long *tick_delta); 77*4882a593Smuzhiyun extern unsigned long sun4v_rng_data_read(unsigned long data_ra, 78*4882a593Smuzhiyun unsigned long *tick_delta); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun enum n2rng_compat_id { 81*4882a593Smuzhiyun N2_n2_rng, 82*4882a593Smuzhiyun N2_vf_rng, 83*4882a593Smuzhiyun N2_kt_rng, 84*4882a593Smuzhiyun N2_m4_rng, 85*4882a593Smuzhiyun N2_m7_rng, 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct n2rng_template { 89*4882a593Smuzhiyun enum n2rng_compat_id id; 90*4882a593Smuzhiyun int multi_capable; 91*4882a593Smuzhiyun int chip_version; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct n2rng_unit { 95*4882a593Smuzhiyun u64 control[HV_RNG_NUM_CONTROL]; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct n2rng { 99*4882a593Smuzhiyun struct platform_device *op; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun unsigned long flags; 102*4882a593Smuzhiyun #define N2RNG_FLAG_MULTI 0x00000001 /* Multi-unit capable RNG */ 103*4882a593Smuzhiyun #define N2RNG_FLAG_CONTROL 0x00000002 /* Operating in control domain */ 104*4882a593Smuzhiyun #define N2RNG_FLAG_READY 0x00000008 /* Ready for hw-rng layer */ 105*4882a593Smuzhiyun #define N2RNG_FLAG_SHUTDOWN 0x00000010 /* Driver unregistering */ 106*4882a593Smuzhiyun #define N2RNG_FLAG_BUFFER_VALID 0x00000020 /* u32 buffer holds valid data */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun struct n2rng_template *data; 109*4882a593Smuzhiyun int num_units; 110*4882a593Smuzhiyun struct n2rng_unit *units; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct hwrng hwrng; 113*4882a593Smuzhiyun u32 buffer; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Registered hypervisor group API major and minor version. */ 116*4882a593Smuzhiyun unsigned long hvapi_major; 117*4882a593Smuzhiyun unsigned long hvapi_minor; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun struct delayed_work work; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun unsigned long hv_state; /* HV_RNG_STATE_foo */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun unsigned long health_check_sec; 124*4882a593Smuzhiyun unsigned long accum_cycles; 125*4882a593Smuzhiyun unsigned long wd_timeo; 126*4882a593Smuzhiyun #define N2RNG_HEALTH_CHECK_SEC_DEFAULT 0 127*4882a593Smuzhiyun #define N2RNG_ACCUM_CYCLES_DEFAULT 2048 128*4882a593Smuzhiyun #define N2RNG_WD_TIMEO_DEFAULT 0 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun u64 scratch_control[HV_RNG_NUM_CONTROL]; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define RNG_v1_SELFTEST_TICKS 38859 133*4882a593Smuzhiyun #define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C) 134*4882a593Smuzhiyun #define RNG_v2_SELFTEST_TICKS 64 135*4882a593Smuzhiyun #define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff) 136*4882a593Smuzhiyun #define SELFTEST_POLY ((u64)0x231DCEE91262B8A3) 137*4882a593Smuzhiyun #define SELFTEST_MATCH_GOAL 6 138*4882a593Smuzhiyun #define SELFTEST_LOOPS_MAX 40000 139*4882a593Smuzhiyun #define SELFTEST_BUFFER_WORDS 8 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun u64 test_data; 142*4882a593Smuzhiyun u64 test_control[HV_RNG_NUM_CONTROL]; 143*4882a593Smuzhiyun u64 test_buffer[SELFTEST_BUFFER_WORDS]; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define N2RNG_BLOCK_LIMIT 60000 147*4882a593Smuzhiyun #define N2RNG_BUSY_LIMIT 100 148*4882a593Smuzhiyun #define N2RNG_HCHECK_LIMIT 100 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #endif /* !(__ASSEMBLY__) */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #endif /* _N2RNG_H */ 153