1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Broadcom Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
6*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11*4882a593Smuzhiyun * GNU General Public License for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * DESCRIPTION: The Broadcom iProc RNG200 Driver
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/hw_random.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/of_address.h>
23*4882a593Smuzhiyun #include <linux/of_platform.h>
24*4882a593Smuzhiyun #include <linux/platform_device.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Registers */
28*4882a593Smuzhiyun #define RNG_CTRL_OFFSET 0x00
29*4882a593Smuzhiyun #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
30*4882a593Smuzhiyun #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
31*4882a593Smuzhiyun #define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RNG_SOFT_RESET_OFFSET 0x04
34*4882a593Smuzhiyun #define RNG_SOFT_RESET 0x00000001
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define RBG_SOFT_RESET_OFFSET 0x08
37*4882a593Smuzhiyun #define RBG_SOFT_RESET 0x00000001
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define RNG_INT_STATUS_OFFSET 0x18
40*4882a593Smuzhiyun #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
41*4882a593Smuzhiyun #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
42*4882a593Smuzhiyun #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
43*4882a593Smuzhiyun #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define RNG_FIFO_DATA_OFFSET 0x20
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define RNG_FIFO_COUNT_OFFSET 0x24
48*4882a593Smuzhiyun #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct iproc_rng200_dev {
51*4882a593Smuzhiyun struct hwrng rng;
52*4882a593Smuzhiyun void __iomem *base;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
56*4882a593Smuzhiyun
iproc_rng200_restart(void __iomem * rng_base)57*4882a593Smuzhiyun static void iproc_rng200_restart(void __iomem *rng_base)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun uint32_t val;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Disable RBG */
62*4882a593Smuzhiyun val = ioread32(rng_base + RNG_CTRL_OFFSET);
63*4882a593Smuzhiyun val &= ~RNG_CTRL_RNG_RBGEN_MASK;
64*4882a593Smuzhiyun val |= RNG_CTRL_RNG_RBGEN_DISABLE;
65*4882a593Smuzhiyun iowrite32(val, rng_base + RNG_CTRL_OFFSET);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Clear all interrupt status */
68*4882a593Smuzhiyun iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Reset RNG and RBG */
71*4882a593Smuzhiyun val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
72*4882a593Smuzhiyun val |= RBG_SOFT_RESET;
73*4882a593Smuzhiyun iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
76*4882a593Smuzhiyun val |= RNG_SOFT_RESET;
77*4882a593Smuzhiyun iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
80*4882a593Smuzhiyun val &= ~RNG_SOFT_RESET;
81*4882a593Smuzhiyun iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
84*4882a593Smuzhiyun val &= ~RBG_SOFT_RESET;
85*4882a593Smuzhiyun iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Enable RBG */
88*4882a593Smuzhiyun val = ioread32(rng_base + RNG_CTRL_OFFSET);
89*4882a593Smuzhiyun val &= ~RNG_CTRL_RNG_RBGEN_MASK;
90*4882a593Smuzhiyun val |= RNG_CTRL_RNG_RBGEN_ENABLE;
91*4882a593Smuzhiyun iowrite32(val, rng_base + RNG_CTRL_OFFSET);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
iproc_rng200_read(struct hwrng * rng,void * buf,size_t max,bool wait)94*4882a593Smuzhiyun static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
95*4882a593Smuzhiyun bool wait)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct iproc_rng200_dev *priv = to_rng_priv(rng);
98*4882a593Smuzhiyun uint32_t num_remaining = max;
99*4882a593Smuzhiyun uint32_t status;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define MAX_RESETS_PER_READ 1
102*4882a593Smuzhiyun uint32_t num_resets = 0;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #define MAX_IDLE_TIME (1 * HZ)
105*4882a593Smuzhiyun unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Is RNG sane? If not, reset it. */
110*4882a593Smuzhiyun status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
111*4882a593Smuzhiyun if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
112*4882a593Smuzhiyun RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (num_resets >= MAX_RESETS_PER_READ)
115*4882a593Smuzhiyun return max - num_remaining;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun iproc_rng200_restart(priv->base);
118*4882a593Smuzhiyun num_resets++;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Are there any random numbers available? */
122*4882a593Smuzhiyun if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
123*4882a593Smuzhiyun RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (num_remaining >= sizeof(uint32_t)) {
126*4882a593Smuzhiyun /* Buffer has room to store entire word */
127*4882a593Smuzhiyun *(uint32_t *)buf = ioread32(priv->base +
128*4882a593Smuzhiyun RNG_FIFO_DATA_OFFSET);
129*4882a593Smuzhiyun buf += sizeof(uint32_t);
130*4882a593Smuzhiyun num_remaining -= sizeof(uint32_t);
131*4882a593Smuzhiyun } else {
132*4882a593Smuzhiyun /* Buffer can only store partial word */
133*4882a593Smuzhiyun uint32_t rnd_number = ioread32(priv->base +
134*4882a593Smuzhiyun RNG_FIFO_DATA_OFFSET);
135*4882a593Smuzhiyun memcpy(buf, &rnd_number, num_remaining);
136*4882a593Smuzhiyun buf += num_remaining;
137*4882a593Smuzhiyun num_remaining = 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Reset the IDLE timeout */
141*4882a593Smuzhiyun idle_endtime = jiffies + MAX_IDLE_TIME;
142*4882a593Smuzhiyun } else {
143*4882a593Smuzhiyun if (!wait)
144*4882a593Smuzhiyun /* Cannot wait, return immediately */
145*4882a593Smuzhiyun return max - num_remaining;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Can wait, give others chance to run */
148*4882a593Smuzhiyun usleep_range(min(num_remaining * 10, 500U), 500);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun return max - num_remaining;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
iproc_rng200_init(struct hwrng * rng)155*4882a593Smuzhiyun static int iproc_rng200_init(struct hwrng *rng)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct iproc_rng200_dev *priv = to_rng_priv(rng);
158*4882a593Smuzhiyun uint32_t val;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* Setup RNG. */
161*4882a593Smuzhiyun val = ioread32(priv->base + RNG_CTRL_OFFSET);
162*4882a593Smuzhiyun val &= ~RNG_CTRL_RNG_RBGEN_MASK;
163*4882a593Smuzhiyun val |= RNG_CTRL_RNG_RBGEN_ENABLE;
164*4882a593Smuzhiyun iowrite32(val, priv->base + RNG_CTRL_OFFSET);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
iproc_rng200_cleanup(struct hwrng * rng)169*4882a593Smuzhiyun static void iproc_rng200_cleanup(struct hwrng *rng)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun struct iproc_rng200_dev *priv = to_rng_priv(rng);
172*4882a593Smuzhiyun uint32_t val;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* Disable RNG hardware */
175*4882a593Smuzhiyun val = ioread32(priv->base + RNG_CTRL_OFFSET);
176*4882a593Smuzhiyun val &= ~RNG_CTRL_RNG_RBGEN_MASK;
177*4882a593Smuzhiyun val |= RNG_CTRL_RNG_RBGEN_DISABLE;
178*4882a593Smuzhiyun iowrite32(val, priv->base + RNG_CTRL_OFFSET);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
iproc_rng200_probe(struct platform_device * pdev)181*4882a593Smuzhiyun static int iproc_rng200_probe(struct platform_device *pdev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun struct iproc_rng200_dev *priv;
184*4882a593Smuzhiyun struct device *dev = &pdev->dev;
185*4882a593Smuzhiyun int ret;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
188*4882a593Smuzhiyun if (!priv)
189*4882a593Smuzhiyun return -ENOMEM;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* Map peripheral */
192*4882a593Smuzhiyun priv->base = devm_platform_ioremap_resource(pdev, 0);
193*4882a593Smuzhiyun if (IS_ERR(priv->base)) {
194*4882a593Smuzhiyun dev_err(dev, "failed to remap rng regs\n");
195*4882a593Smuzhiyun return PTR_ERR(priv->base);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun priv->rng.name = "iproc-rng200";
199*4882a593Smuzhiyun priv->rng.read = iproc_rng200_read;
200*4882a593Smuzhiyun priv->rng.init = iproc_rng200_init;
201*4882a593Smuzhiyun priv->rng.cleanup = iproc_rng200_cleanup;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /* Register driver */
204*4882a593Smuzhiyun ret = devm_hwrng_register(dev, &priv->rng);
205*4882a593Smuzhiyun if (ret) {
206*4882a593Smuzhiyun dev_err(dev, "hwrng registration failed\n");
207*4882a593Smuzhiyun return ret;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun dev_info(dev, "hwrng registered\n");
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun return 0;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun static const struct of_device_id iproc_rng200_of_match[] = {
216*4882a593Smuzhiyun { .compatible = "brcm,bcm2711-rng200", },
217*4882a593Smuzhiyun { .compatible = "brcm,bcm7211-rng200", },
218*4882a593Smuzhiyun { .compatible = "brcm,bcm7278-rng200", },
219*4882a593Smuzhiyun { .compatible = "brcm,iproc-rng200", },
220*4882a593Smuzhiyun {},
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun static struct platform_driver iproc_rng200_driver = {
225*4882a593Smuzhiyun .driver = {
226*4882a593Smuzhiyun .name = "iproc-rng200",
227*4882a593Smuzhiyun .of_match_table = iproc_rng200_of_match,
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun .probe = iproc_rng200_probe,
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun module_platform_driver(iproc_rng200_driver);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom");
234*4882a593Smuzhiyun MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
235*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
236