1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Ingenic True Random Number Generator driver
4*4882a593Smuzhiyun * Copyright (c) 2019 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
5*4882a593Smuzhiyun * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/hw_random.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/iopoll.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* DTRNG register offsets */
20*4882a593Smuzhiyun #define TRNG_REG_CFG_OFFSET 0x00
21*4882a593Smuzhiyun #define TRNG_REG_RANDOMNUM_OFFSET 0x04
22*4882a593Smuzhiyun #define TRNG_REG_STATUS_OFFSET 0x08
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* bits within the CFG register */
25*4882a593Smuzhiyun #define CFG_RDY_CLR BIT(12)
26*4882a593Smuzhiyun #define CFG_INT_MASK BIT(11)
27*4882a593Smuzhiyun #define CFG_GEN_EN BIT(0)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* bits within the STATUS register */
30*4882a593Smuzhiyun #define STATUS_RANDOM_RDY BIT(0)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct ingenic_trng {
33*4882a593Smuzhiyun void __iomem *base;
34*4882a593Smuzhiyun struct clk *clk;
35*4882a593Smuzhiyun struct hwrng rng;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
ingenic_trng_init(struct hwrng * rng)38*4882a593Smuzhiyun static int ingenic_trng_init(struct hwrng *rng)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
41*4882a593Smuzhiyun unsigned int ctrl;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
44*4882a593Smuzhiyun ctrl |= CFG_GEN_EN;
45*4882a593Smuzhiyun writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
ingenic_trng_cleanup(struct hwrng * rng)50*4882a593Smuzhiyun static void ingenic_trng_cleanup(struct hwrng *rng)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
53*4882a593Smuzhiyun unsigned int ctrl;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
56*4882a593Smuzhiyun ctrl &= ~CFG_GEN_EN;
57*4882a593Smuzhiyun writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
ingenic_trng_read(struct hwrng * rng,void * buf,size_t max,bool wait)60*4882a593Smuzhiyun static int ingenic_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
63*4882a593Smuzhiyun u32 *data = buf;
64*4882a593Smuzhiyun u32 status;
65*4882a593Smuzhiyun int ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = readl_poll_timeout(trng->base + TRNG_REG_STATUS_OFFSET, status,
68*4882a593Smuzhiyun status & STATUS_RANDOM_RDY, 10, 1000);
69*4882a593Smuzhiyun if (ret == -ETIMEDOUT) {
70*4882a593Smuzhiyun pr_err("%s: Wait for DTRNG data ready timeout\n", __func__);
71*4882a593Smuzhiyun return ret;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun *data = readl(trng->base + TRNG_REG_RANDOMNUM_OFFSET);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 4;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
ingenic_trng_probe(struct platform_device * pdev)79*4882a593Smuzhiyun static int ingenic_trng_probe(struct platform_device *pdev)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct ingenic_trng *trng;
82*4882a593Smuzhiyun int ret;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
85*4882a593Smuzhiyun if (!trng)
86*4882a593Smuzhiyun return -ENOMEM;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun trng->base = devm_platform_ioremap_resource(pdev, 0);
89*4882a593Smuzhiyun if (IS_ERR(trng->base)) {
90*4882a593Smuzhiyun pr_err("%s: Failed to map DTRNG registers\n", __func__);
91*4882a593Smuzhiyun ret = PTR_ERR(trng->base);
92*4882a593Smuzhiyun return PTR_ERR(trng->base);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun trng->clk = devm_clk_get(&pdev->dev, NULL);
96*4882a593Smuzhiyun if (IS_ERR(trng->clk)) {
97*4882a593Smuzhiyun ret = PTR_ERR(trng->clk);
98*4882a593Smuzhiyun pr_crit("%s: Cannot get DTRNG clock\n", __func__);
99*4882a593Smuzhiyun return PTR_ERR(trng->clk);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun ret = clk_prepare_enable(trng->clk);
103*4882a593Smuzhiyun if (ret) {
104*4882a593Smuzhiyun pr_crit("%s: Unable to enable DTRNG clock\n", __func__);
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun trng->rng.name = pdev->name;
109*4882a593Smuzhiyun trng->rng.init = ingenic_trng_init;
110*4882a593Smuzhiyun trng->rng.cleanup = ingenic_trng_cleanup;
111*4882a593Smuzhiyun trng->rng.read = ingenic_trng_read;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun ret = hwrng_register(&trng->rng);
114*4882a593Smuzhiyun if (ret) {
115*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register hwrng\n");
116*4882a593Smuzhiyun goto err_unprepare_clk;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun platform_set_drvdata(pdev, trng);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun dev_info(&pdev->dev, "Ingenic DTRNG driver registered\n");
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun err_unprepare_clk:
125*4882a593Smuzhiyun clk_disable_unprepare(trng->clk);
126*4882a593Smuzhiyun return ret;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
ingenic_trng_remove(struct platform_device * pdev)129*4882a593Smuzhiyun static int ingenic_trng_remove(struct platform_device *pdev)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun struct ingenic_trng *trng = platform_get_drvdata(pdev);
132*4882a593Smuzhiyun unsigned int ctrl;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun hwrng_unregister(&trng->rng);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
137*4882a593Smuzhiyun ctrl &= ~CFG_GEN_EN;
138*4882a593Smuzhiyun writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun clk_disable_unprepare(trng->clk);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct of_device_id ingenic_trng_of_match[] = {
146*4882a593Smuzhiyun { .compatible = "ingenic,x1830-dtrng" },
147*4882a593Smuzhiyun { /* sentinel */ }
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ingenic_trng_of_match);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static struct platform_driver ingenic_trng_driver = {
152*4882a593Smuzhiyun .probe = ingenic_trng_probe,
153*4882a593Smuzhiyun .remove = ingenic_trng_remove,
154*4882a593Smuzhiyun .driver = {
155*4882a593Smuzhiyun .name = "ingenic-trng",
156*4882a593Smuzhiyun .of_match_table = ingenic_trng_of_match,
157*4882a593Smuzhiyun },
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun module_platform_driver(ingenic_trng_driver);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun MODULE_LICENSE("GPL");
163*4882a593Smuzhiyun MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>");
164*4882a593Smuzhiyun MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
165*4882a593Smuzhiyun MODULE_DESCRIPTION("Ingenic True Random Number Generator driver");
166