1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #include <linux/bitops.h> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define POWER_DOWN_ENABLE 0x01 7*4882a593Smuzhiyun #define POWER_DOWN_DISABLE 0x00 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* hwrng quality: bits of true entropy per 1024 bits of input */ 10*4882a593Smuzhiyun #define CC_TRNG_QUALITY 1024 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* CryptoCell TRNG HW definitions */ 13*4882a593Smuzhiyun #define CC_TRNG_NUM_OF_ROSCS 4 14*4882a593Smuzhiyun /* The number of words generated in the entropy holding register (EHR) 15*4882a593Smuzhiyun * 6 words (192 bit) according to HW implementation 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define CC_TRNG_EHR_IN_WORDS 6 18*4882a593Smuzhiyun #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32)) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* RNG interrupt mask */ 23*4882a593Smuzhiyun #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \ 24*4882a593Smuzhiyun BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \ 25*4882a593Smuzhiyun BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \ 26*4882a593Smuzhiyun BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \ 27*4882a593Smuzhiyun BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun // -------------------------------------- 30*4882a593Smuzhiyun // BLOCK: RNG 31*4882a593Smuzhiyun // -------------------------------------- 32*4882a593Smuzhiyun #define CC_RNG_IMR_REG_OFFSET 0x0100UL 33*4882a593Smuzhiyun #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL 34*4882a593Smuzhiyun #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL 35*4882a593Smuzhiyun #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL 36*4882a593Smuzhiyun #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL 37*4882a593Smuzhiyun #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL 38*4882a593Smuzhiyun #define CC_RNG_ISR_REG_OFFSET 0x0104UL 39*4882a593Smuzhiyun #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL 40*4882a593Smuzhiyun #define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL 41*4882a593Smuzhiyun #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL 42*4882a593Smuzhiyun #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL 43*4882a593Smuzhiyun #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL 44*4882a593Smuzhiyun #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL 45*4882a593Smuzhiyun #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL 46*4882a593Smuzhiyun #define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL 47*4882a593Smuzhiyun #define CC_RNG_ICR_REG_OFFSET 0x0108UL 48*4882a593Smuzhiyun #define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL 49*4882a593Smuzhiyun #define CC_EHR_DATA_0_REG_OFFSET 0x0114UL 50*4882a593Smuzhiyun #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL 51*4882a593Smuzhiyun #define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL 52*4882a593Smuzhiyun #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL 53*4882a593Smuzhiyun #define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL 54*4882a593Smuzhiyun #define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL 55*4882a593Smuzhiyun #define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL 56*4882a593Smuzhiyun #define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL 57*4882a593Smuzhiyun // -------------------------------------- 58*4882a593Smuzhiyun // BLOCK: SEC_HOST_RGF 59*4882a593Smuzhiyun // -------------------------------------- 60*4882a593Smuzhiyun #define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL 61*4882a593Smuzhiyun #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL 62*4882a593Smuzhiyun #define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL 63*4882a593Smuzhiyun #define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun // -------------------------------------- 68*4882a593Smuzhiyun // BLOCK: NVM 69*4882a593Smuzhiyun // -------------------------------------- 70*4882a593Smuzhiyun #define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL 71*4882a593Smuzhiyun #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 72*4882a593Smuzhiyun #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL 73