xref: /OK3568_Linux_fs/kernel/drivers/char/hw_random/ba431-rng.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2020 Silex Insight
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <linux/delay.h>
5*4882a593Smuzhiyun #include <linux/hw_random.h>
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/iopoll.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/workqueue.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define BA431_RESET_DELAY			1 /* usec */
15*4882a593Smuzhiyun #define BA431_RESET_READ_STATUS_TIMEOUT		1000 /* usec */
16*4882a593Smuzhiyun #define BA431_RESET_READ_STATUS_INTERVAL	10 /* usec */
17*4882a593Smuzhiyun #define BA431_READ_RETRY_INTERVAL		1 /* usec */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define BA431_REG_CTRL				0x00
20*4882a593Smuzhiyun #define BA431_REG_FIFO_LEVEL			0x04
21*4882a593Smuzhiyun #define BA431_REG_STATUS			0x30
22*4882a593Smuzhiyun #define BA431_REG_FIFODATA			0x80
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define BA431_CTRL_ENABLE			BIT(0)
25*4882a593Smuzhiyun #define BA431_CTRL_SOFTRESET			BIT(8)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define BA431_STATUS_STATE_MASK			(BIT(1) | BIT(2) | BIT(3))
28*4882a593Smuzhiyun #define BA431_STATUS_STATE_OFFSET		1
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun enum ba431_state {
31*4882a593Smuzhiyun 	BA431_STATE_RESET,
32*4882a593Smuzhiyun 	BA431_STATE_STARTUP,
33*4882a593Smuzhiyun 	BA431_STATE_FIFOFULLON,
34*4882a593Smuzhiyun 	BA431_STATE_FIFOFULLOFF,
35*4882a593Smuzhiyun 	BA431_STATE_RUNNING,
36*4882a593Smuzhiyun 	BA431_STATE_ERROR
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun struct ba431_trng {
40*4882a593Smuzhiyun 	struct device *dev;
41*4882a593Smuzhiyun 	void __iomem *base;
42*4882a593Smuzhiyun 	struct hwrng rng;
43*4882a593Smuzhiyun 	atomic_t reset_pending;
44*4882a593Smuzhiyun 	struct work_struct reset_work;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
ba431_trng_read_reg(struct ba431_trng * ba431,u32 reg)47*4882a593Smuzhiyun static inline u32 ba431_trng_read_reg(struct ba431_trng *ba431, u32 reg)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	return ioread32(ba431->base + reg);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun 
ba431_trng_write_reg(struct ba431_trng * ba431,u32 reg,u32 val)52*4882a593Smuzhiyun static inline void ba431_trng_write_reg(struct ba431_trng *ba431, u32 reg,
53*4882a593Smuzhiyun 					u32 val)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	iowrite32(val, ba431->base + reg);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
ba431_trng_get_state(struct ba431_trng * ba431)58*4882a593Smuzhiyun static inline enum ba431_state ba431_trng_get_state(struct ba431_trng *ba431)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	u32 status = ba431_trng_read_reg(ba431, BA431_REG_STATUS);
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	return (status & BA431_STATUS_STATE_MASK) >> BA431_STATUS_STATE_OFFSET;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
ba431_trng_is_in_error(struct ba431_trng * ba431)65*4882a593Smuzhiyun static int ba431_trng_is_in_error(struct ba431_trng *ba431)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	enum ba431_state state = ba431_trng_get_state(ba431);
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	if ((state < BA431_STATE_STARTUP) ||
70*4882a593Smuzhiyun 	    (state >= BA431_STATE_ERROR))
71*4882a593Smuzhiyun 		return 1;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
ba431_trng_reset(struct ba431_trng * ba431)76*4882a593Smuzhiyun static int ba431_trng_reset(struct ba431_trng *ba431)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	int ret;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* Disable interrupts, random generation and enable the softreset */
81*4882a593Smuzhiyun 	ba431_trng_write_reg(ba431, BA431_REG_CTRL, BA431_CTRL_SOFTRESET);
82*4882a593Smuzhiyun 	udelay(BA431_RESET_DELAY);
83*4882a593Smuzhiyun 	ba431_trng_write_reg(ba431, BA431_REG_CTRL, BA431_CTRL_ENABLE);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* Wait until the state changed */
86*4882a593Smuzhiyun 	if (readx_poll_timeout(ba431_trng_is_in_error, ba431, ret, !ret,
87*4882a593Smuzhiyun 			       BA431_RESET_READ_STATUS_INTERVAL,
88*4882a593Smuzhiyun 			       BA431_RESET_READ_STATUS_TIMEOUT)) {
89*4882a593Smuzhiyun 		dev_err(ba431->dev, "reset failed (state: %d)\n",
90*4882a593Smuzhiyun 			ba431_trng_get_state(ba431));
91*4882a593Smuzhiyun 		return -ETIMEDOUT;
92*4882a593Smuzhiyun 	}
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	dev_info(ba431->dev, "reset done\n");
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
ba431_trng_reset_work(struct work_struct * work)99*4882a593Smuzhiyun static void ba431_trng_reset_work(struct work_struct *work)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	struct ba431_trng *ba431 = container_of(work, struct ba431_trng,
102*4882a593Smuzhiyun 						reset_work);
103*4882a593Smuzhiyun 	ba431_trng_reset(ba431);
104*4882a593Smuzhiyun 	atomic_set(&ba431->reset_pending, 0);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
ba431_trng_schedule_reset(struct ba431_trng * ba431)107*4882a593Smuzhiyun static void ba431_trng_schedule_reset(struct ba431_trng *ba431)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	if (atomic_cmpxchg(&ba431->reset_pending, 0, 1))
110*4882a593Smuzhiyun 		return;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	schedule_work(&ba431->reset_work);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
ba431_trng_read(struct hwrng * rng,void * buf,size_t max,bool wait)115*4882a593Smuzhiyun static int ba431_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	struct ba431_trng *ba431 = container_of(rng, struct ba431_trng, rng);
118*4882a593Smuzhiyun 	u32 *data = buf;
119*4882a593Smuzhiyun 	unsigned int level, i;
120*4882a593Smuzhiyun 	int n = 0;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	while (max > 0) {
123*4882a593Smuzhiyun 		level = ba431_trng_read_reg(ba431, BA431_REG_FIFO_LEVEL);
124*4882a593Smuzhiyun 		if (!level) {
125*4882a593Smuzhiyun 			if (ba431_trng_is_in_error(ba431)) {
126*4882a593Smuzhiyun 				ba431_trng_schedule_reset(ba431);
127*4882a593Smuzhiyun 				break;
128*4882a593Smuzhiyun 			}
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 			if (!wait)
131*4882a593Smuzhiyun 				break;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 			udelay(BA431_READ_RETRY_INTERVAL);
134*4882a593Smuzhiyun 			continue;
135*4882a593Smuzhiyun 		}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 		i = level;
138*4882a593Smuzhiyun 		do {
139*4882a593Smuzhiyun 			data[n++] = ba431_trng_read_reg(ba431,
140*4882a593Smuzhiyun 							BA431_REG_FIFODATA);
141*4882a593Smuzhiyun 			max -= sizeof(*data);
142*4882a593Smuzhiyun 		} while (--i && (max > 0));
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 		if (ba431_trng_is_in_error(ba431)) {
145*4882a593Smuzhiyun 			n -= (level - i);
146*4882a593Smuzhiyun 			ba431_trng_schedule_reset(ba431);
147*4882a593Smuzhiyun 			break;
148*4882a593Smuzhiyun 		}
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	n *= sizeof(data);
152*4882a593Smuzhiyun 	return (n || !wait) ? n : -EIO;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
ba431_trng_cleanup(struct hwrng * rng)155*4882a593Smuzhiyun static void ba431_trng_cleanup(struct hwrng *rng)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct ba431_trng *ba431 = container_of(rng, struct ba431_trng, rng);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	ba431_trng_write_reg(ba431, BA431_REG_CTRL, 0);
160*4882a593Smuzhiyun 	cancel_work_sync(&ba431->reset_work);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
ba431_trng_init(struct hwrng * rng)163*4882a593Smuzhiyun static int ba431_trng_init(struct hwrng *rng)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	struct ba431_trng *ba431 = container_of(rng, struct ba431_trng, rng);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return ba431_trng_reset(ba431);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
ba431_trng_probe(struct platform_device * pdev)170*4882a593Smuzhiyun static int ba431_trng_probe(struct platform_device *pdev)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	struct ba431_trng *ba431;
173*4882a593Smuzhiyun 	struct resource *res;
174*4882a593Smuzhiyun 	int ret;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	ba431 = devm_kzalloc(&pdev->dev, sizeof(*ba431), GFP_KERNEL);
177*4882a593Smuzhiyun 	if (!ba431)
178*4882a593Smuzhiyun 		return -ENOMEM;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ba431->dev = &pdev->dev;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
183*4882a593Smuzhiyun 	ba431->base = devm_ioremap_resource(&pdev->dev, res);
184*4882a593Smuzhiyun 	if (IS_ERR(ba431->base))
185*4882a593Smuzhiyun 		return PTR_ERR(ba431->base);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	atomic_set(&ba431->reset_pending, 0);
188*4882a593Smuzhiyun 	INIT_WORK(&ba431->reset_work, ba431_trng_reset_work);
189*4882a593Smuzhiyun 	ba431->rng.name = pdev->name;
190*4882a593Smuzhiyun 	ba431->rng.init = ba431_trng_init;
191*4882a593Smuzhiyun 	ba431->rng.cleanup = ba431_trng_cleanup;
192*4882a593Smuzhiyun 	ba431->rng.read = ba431_trng_read;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	platform_set_drvdata(pdev, ba431);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	ret = hwrng_register(&ba431->rng);
197*4882a593Smuzhiyun 	if (ret) {
198*4882a593Smuzhiyun 		dev_err(&pdev->dev, "BA431 registration failed (%d)\n", ret);
199*4882a593Smuzhiyun 		return ret;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	dev_info(&pdev->dev, "BA431 TRNG registered\n");
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	return 0;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
ba431_trng_remove(struct platform_device * pdev)207*4882a593Smuzhiyun static int ba431_trng_remove(struct platform_device *pdev)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	struct ba431_trng *ba431 = platform_get_drvdata(pdev);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	hwrng_unregister(&ba431->rng);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	return 0;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct of_device_id ba431_trng_dt_ids[] = {
217*4882a593Smuzhiyun 	{ .compatible = "silex-insight,ba431-rng", .data = NULL },
218*4882a593Smuzhiyun 	{ /* sentinel */ }
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ba431_trng_dt_ids);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun static struct platform_driver ba431_trng_driver = {
223*4882a593Smuzhiyun 	.driver = {
224*4882a593Smuzhiyun 		.name = "ba431-rng",
225*4882a593Smuzhiyun 		.of_match_table = ba431_trng_dt_ids,
226*4882a593Smuzhiyun 	},
227*4882a593Smuzhiyun 	.probe = ba431_trng_probe,
228*4882a593Smuzhiyun 	.remove = ba431_trng_remove,
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun module_platform_driver(ba431_trng_driver);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun MODULE_AUTHOR("Olivier Sobrie <olivier@sobrie.be>");
234*4882a593Smuzhiyun MODULE_DESCRIPTION("TRNG driver for Silex Insight BA431");
235*4882a593Smuzhiyun MODULE_LICENSE("GPL");
236