1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2011 Peter Korsgaard <jacmet@sunsite.dk>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
6*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/hw_random.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define TRNG_CR 0x00
21*4882a593Smuzhiyun #define TRNG_MR 0x04
22*4882a593Smuzhiyun #define TRNG_ISR 0x1c
23*4882a593Smuzhiyun #define TRNG_ODATA 0x50
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define TRNG_KEY 0x524e4700 /* RNG */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define TRNG_HALFR BIT(0) /* generate RN every 168 cycles */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct atmel_trng_data {
30*4882a593Smuzhiyun bool has_half_rate;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct atmel_trng {
34*4882a593Smuzhiyun struct clk *clk;
35*4882a593Smuzhiyun void __iomem *base;
36*4882a593Smuzhiyun struct hwrng rng;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
atmel_trng_read(struct hwrng * rng,void * buf,size_t max,bool wait)39*4882a593Smuzhiyun static int atmel_trng_read(struct hwrng *rng, void *buf, size_t max,
40*4882a593Smuzhiyun bool wait)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct atmel_trng *trng = container_of(rng, struct atmel_trng, rng);
43*4882a593Smuzhiyun u32 *data = buf;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* data ready? */
46*4882a593Smuzhiyun if (readl(trng->base + TRNG_ISR) & 1) {
47*4882a593Smuzhiyun *data = readl(trng->base + TRNG_ODATA);
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun ensure data ready is only set again AFTER the next data
50*4882a593Smuzhiyun word is ready in case it got set between checking ISR
51*4882a593Smuzhiyun and reading ODATA, so we don't risk re-reading the
52*4882a593Smuzhiyun same word
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun readl(trng->base + TRNG_ISR);
55*4882a593Smuzhiyun return 4;
56*4882a593Smuzhiyun } else
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
atmel_trng_enable(struct atmel_trng * trng)60*4882a593Smuzhiyun static void atmel_trng_enable(struct atmel_trng *trng)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun writel(TRNG_KEY | 1, trng->base + TRNG_CR);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
atmel_trng_disable(struct atmel_trng * trng)65*4882a593Smuzhiyun static void atmel_trng_disable(struct atmel_trng *trng)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun writel(TRNG_KEY, trng->base + TRNG_CR);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
atmel_trng_probe(struct platform_device * pdev)70*4882a593Smuzhiyun static int atmel_trng_probe(struct platform_device *pdev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct atmel_trng *trng;
73*4882a593Smuzhiyun const struct atmel_trng_data *data;
74*4882a593Smuzhiyun int ret;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
77*4882a593Smuzhiyun if (!trng)
78*4882a593Smuzhiyun return -ENOMEM;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun trng->base = devm_platform_ioremap_resource(pdev, 0);
81*4882a593Smuzhiyun if (IS_ERR(trng->base))
82*4882a593Smuzhiyun return PTR_ERR(trng->base);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun trng->clk = devm_clk_get(&pdev->dev, NULL);
85*4882a593Smuzhiyun if (IS_ERR(trng->clk))
86*4882a593Smuzhiyun return PTR_ERR(trng->clk);
87*4882a593Smuzhiyun data = of_device_get_match_data(&pdev->dev);
88*4882a593Smuzhiyun if (!data)
89*4882a593Smuzhiyun return -ENODEV;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (data->has_half_rate) {
92*4882a593Smuzhiyun unsigned long rate = clk_get_rate(trng->clk);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* if peripheral clk is above 100MHz, set HALFR */
95*4882a593Smuzhiyun if (rate > 100000000)
96*4882a593Smuzhiyun writel(TRNG_HALFR, trng->base + TRNG_MR);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = clk_prepare_enable(trng->clk);
100*4882a593Smuzhiyun if (ret)
101*4882a593Smuzhiyun return ret;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun atmel_trng_enable(trng);
104*4882a593Smuzhiyun trng->rng.name = pdev->name;
105*4882a593Smuzhiyun trng->rng.read = atmel_trng_read;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun ret = devm_hwrng_register(&pdev->dev, &trng->rng);
108*4882a593Smuzhiyun if (ret)
109*4882a593Smuzhiyun goto err_register;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun platform_set_drvdata(pdev, trng);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun err_register:
116*4882a593Smuzhiyun clk_disable_unprepare(trng->clk);
117*4882a593Smuzhiyun atmel_trng_disable(trng);
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
atmel_trng_remove(struct platform_device * pdev)121*4882a593Smuzhiyun static int atmel_trng_remove(struct platform_device *pdev)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct atmel_trng *trng = platform_get_drvdata(pdev);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun atmel_trng_disable(trng);
127*4882a593Smuzhiyun clk_disable_unprepare(trng->clk);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #ifdef CONFIG_PM
atmel_trng_suspend(struct device * dev)133*4882a593Smuzhiyun static int atmel_trng_suspend(struct device *dev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct atmel_trng *trng = dev_get_drvdata(dev);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun atmel_trng_disable(trng);
138*4882a593Smuzhiyun clk_disable_unprepare(trng->clk);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
atmel_trng_resume(struct device * dev)143*4882a593Smuzhiyun static int atmel_trng_resume(struct device *dev)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct atmel_trng *trng = dev_get_drvdata(dev);
146*4882a593Smuzhiyun int ret;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun ret = clk_prepare_enable(trng->clk);
149*4882a593Smuzhiyun if (ret)
150*4882a593Smuzhiyun return ret;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun atmel_trng_enable(trng);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct dev_pm_ops atmel_trng_pm_ops = {
158*4882a593Smuzhiyun .suspend = atmel_trng_suspend,
159*4882a593Smuzhiyun .resume = atmel_trng_resume,
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun #endif /* CONFIG_PM */
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const struct atmel_trng_data at91sam9g45_config = {
164*4882a593Smuzhiyun .has_half_rate = false,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const struct atmel_trng_data sam9x60_config = {
168*4882a593Smuzhiyun .has_half_rate = true,
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const struct of_device_id atmel_trng_dt_ids[] = {
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun .compatible = "atmel,at91sam9g45-trng",
174*4882a593Smuzhiyun .data = &at91sam9g45_config,
175*4882a593Smuzhiyun }, {
176*4882a593Smuzhiyun .compatible = "microchip,sam9x60-trng",
177*4882a593Smuzhiyun .data = &sam9x60_config,
178*4882a593Smuzhiyun }, {
179*4882a593Smuzhiyun /* sentinel */
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, atmel_trng_dt_ids);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static struct platform_driver atmel_trng_driver = {
185*4882a593Smuzhiyun .probe = atmel_trng_probe,
186*4882a593Smuzhiyun .remove = atmel_trng_remove,
187*4882a593Smuzhiyun .driver = {
188*4882a593Smuzhiyun .name = "atmel-trng",
189*4882a593Smuzhiyun #ifdef CONFIG_PM
190*4882a593Smuzhiyun .pm = &atmel_trng_pm_ops,
191*4882a593Smuzhiyun #endif /* CONFIG_PM */
192*4882a593Smuzhiyun .of_match_table = atmel_trng_dt_ids,
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun module_platform_driver(atmel_trng_driver);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun MODULE_LICENSE("GPL");
199*4882a593Smuzhiyun MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
200*4882a593Smuzhiyun MODULE_DESCRIPTION("Atmel true random number generator driver");
201