1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * RNG driver for AMD RNGs
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2005 (c) MontaVista Software, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * with the majority of the code coming from:
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
9*4882a593Smuzhiyun * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * derived from
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Hardware driver for the AMD 768 Random Number Generator (RNG)
14*4882a593Smuzhiyun * (c) Copyright 2001 Red Hat Inc
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * derived from
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * Hardware driver for Intel i810 Random Number Generator (RNG)
19*4882a593Smuzhiyun * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
20*4882a593Smuzhiyun * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
23*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
24*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/delay.h>
28*4882a593Smuzhiyun #include <linux/hw_random.h>
29*4882a593Smuzhiyun #include <linux/kernel.h>
30*4882a593Smuzhiyun #include <linux/module.h>
31*4882a593Smuzhiyun #include <linux/pci.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define DRV_NAME "AMD768-HWRNG"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define RNGDATA 0x00
36*4882a593Smuzhiyun #define RNGDONE 0x04
37*4882a593Smuzhiyun #define PMBASE_OFFSET 0xF0
38*4882a593Smuzhiyun #define PMBASE_SIZE 8
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * Data for PCI driver interface
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * This data only exists for exporting the supported
44*4882a593Smuzhiyun * PCI ids via MODULE_DEVICE_TABLE. We do not actually
45*4882a593Smuzhiyun * register a pci_driver, because someone else might one day
46*4882a593Smuzhiyun * want to register another driver on the same PCI id.
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun static const struct pci_device_id pci_tbl[] = {
49*4882a593Smuzhiyun { PCI_VDEVICE(AMD, 0x7443), 0, },
50*4882a593Smuzhiyun { PCI_VDEVICE(AMD, 0x746b), 0, },
51*4882a593Smuzhiyun { 0, }, /* terminate list */
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pci_tbl);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct amd768_priv {
56*4882a593Smuzhiyun void __iomem *iobase;
57*4882a593Smuzhiyun struct pci_dev *pcidev;
58*4882a593Smuzhiyun u32 pmbase;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
amd_rng_read(struct hwrng * rng,void * buf,size_t max,bool wait)61*4882a593Smuzhiyun static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun u32 *data = buf;
64*4882a593Smuzhiyun struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
65*4882a593Smuzhiyun size_t read = 0;
66*4882a593Smuzhiyun /* We will wait at maximum one time per read */
67*4882a593Smuzhiyun int timeout = max / 4 + 1;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * RNG data is available when RNGDONE is set to 1
71*4882a593Smuzhiyun * New random numbers are generated approximately 128 microseconds
72*4882a593Smuzhiyun * after RNGDATA is read
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun while (read < max) {
75*4882a593Smuzhiyun if (ioread32(priv->iobase + RNGDONE) == 0) {
76*4882a593Smuzhiyun if (wait) {
77*4882a593Smuzhiyun /* Delay given by datasheet */
78*4882a593Smuzhiyun usleep_range(128, 196);
79*4882a593Smuzhiyun if (timeout-- == 0)
80*4882a593Smuzhiyun return read;
81*4882a593Smuzhiyun } else {
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun } else {
85*4882a593Smuzhiyun *data = ioread32(priv->iobase + RNGDATA);
86*4882a593Smuzhiyun data++;
87*4882a593Smuzhiyun read += 4;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return read;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
amd_rng_init(struct hwrng * rng)94*4882a593Smuzhiyun static int amd_rng_init(struct hwrng *rng)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
97*4882a593Smuzhiyun u8 rnen;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun pci_read_config_byte(priv->pcidev, 0x40, &rnen);
100*4882a593Smuzhiyun rnen |= BIT(7); /* RNG on */
101*4882a593Smuzhiyun pci_write_config_byte(priv->pcidev, 0x40, rnen);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun pci_read_config_byte(priv->pcidev, 0x41, &rnen);
104*4882a593Smuzhiyun rnen |= BIT(7); /* PMIO enable */
105*4882a593Smuzhiyun pci_write_config_byte(priv->pcidev, 0x41, rnen);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
amd_rng_cleanup(struct hwrng * rng)110*4882a593Smuzhiyun static void amd_rng_cleanup(struct hwrng *rng)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
113*4882a593Smuzhiyun u8 rnen;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun pci_read_config_byte(priv->pcidev, 0x40, &rnen);
116*4882a593Smuzhiyun rnen &= ~BIT(7); /* RNG off */
117*4882a593Smuzhiyun pci_write_config_byte(priv->pcidev, 0x40, rnen);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static struct hwrng amd_rng = {
121*4882a593Smuzhiyun .name = "amd",
122*4882a593Smuzhiyun .init = amd_rng_init,
123*4882a593Smuzhiyun .cleanup = amd_rng_cleanup,
124*4882a593Smuzhiyun .read = amd_rng_read,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
mod_init(void)127*4882a593Smuzhiyun static int __init mod_init(void)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun int err = -ENODEV;
130*4882a593Smuzhiyun struct pci_dev *pdev = NULL;
131*4882a593Smuzhiyun const struct pci_device_id *ent;
132*4882a593Smuzhiyun u32 pmbase;
133*4882a593Smuzhiyun struct amd768_priv *priv;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun for_each_pci_dev(pdev) {
136*4882a593Smuzhiyun ent = pci_match_id(pci_tbl, pdev);
137*4882a593Smuzhiyun if (ent)
138*4882a593Smuzhiyun goto found;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun /* Device not found. */
141*4882a593Smuzhiyun return -ENODEV;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun found:
144*4882a593Smuzhiyun err = pci_read_config_dword(pdev, 0x58, &pmbase);
145*4882a593Smuzhiyun if (err)
146*4882a593Smuzhiyun return err;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun pmbase &= 0x0000FF00;
149*4882a593Smuzhiyun if (pmbase == 0)
150*4882a593Smuzhiyun return -EIO;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun priv = kzalloc(sizeof(*priv), GFP_KERNEL);
153*4882a593Smuzhiyun if (!priv)
154*4882a593Smuzhiyun return -ENOMEM;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
157*4882a593Smuzhiyun dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
158*4882a593Smuzhiyun pmbase + 0xF0);
159*4882a593Smuzhiyun err = -EBUSY;
160*4882a593Smuzhiyun goto out;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
164*4882a593Smuzhiyun if (!priv->iobase) {
165*4882a593Smuzhiyun pr_err(DRV_NAME "Cannot map ioport\n");
166*4882a593Smuzhiyun err = -EINVAL;
167*4882a593Smuzhiyun goto err_iomap;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun amd_rng.priv = (unsigned long)priv;
171*4882a593Smuzhiyun priv->pmbase = pmbase;
172*4882a593Smuzhiyun priv->pcidev = pdev;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun pr_info(DRV_NAME " detected\n");
175*4882a593Smuzhiyun err = hwrng_register(&amd_rng);
176*4882a593Smuzhiyun if (err) {
177*4882a593Smuzhiyun pr_err(DRV_NAME " registering failed (%d)\n", err);
178*4882a593Smuzhiyun goto err_hwrng;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun return 0;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun err_hwrng:
183*4882a593Smuzhiyun ioport_unmap(priv->iobase);
184*4882a593Smuzhiyun err_iomap:
185*4882a593Smuzhiyun release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
186*4882a593Smuzhiyun out:
187*4882a593Smuzhiyun kfree(priv);
188*4882a593Smuzhiyun return err;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
mod_exit(void)191*4882a593Smuzhiyun static void __exit mod_exit(void)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct amd768_priv *priv;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun priv = (struct amd768_priv *)amd_rng.priv;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun hwrng_unregister(&amd_rng);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ioport_unmap(priv->iobase);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun kfree(priv);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun module_init(mod_init);
207*4882a593Smuzhiyun module_exit(mod_exit);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun MODULE_AUTHOR("The Linux Kernel team");
210*4882a593Smuzhiyun MODULE_DESCRIPTION("H/W RNG driver for AMD chipsets");
211*4882a593Smuzhiyun MODULE_LICENSE("GPL");
212