1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ALi AGPGART routines.
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/types.h>
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/pci.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/agp_backend.h>
10*4882a593Smuzhiyun #include <asm/page.h> /* PAGE_SIZE */
11*4882a593Smuzhiyun #include "agp.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define ALI_AGPCTRL 0xb8
14*4882a593Smuzhiyun #define ALI_ATTBASE 0xbc
15*4882a593Smuzhiyun #define ALI_TLBCTRL 0xc0
16*4882a593Smuzhiyun #define ALI_TAGCTRL 0xc4
17*4882a593Smuzhiyun #define ALI_CACHE_FLUSH_CTRL 0xD0
18*4882a593Smuzhiyun #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000
19*4882a593Smuzhiyun #define ALI_CACHE_FLUSH_EN 0x100
20*4882a593Smuzhiyun
ali_fetch_size(void)21*4882a593Smuzhiyun static int ali_fetch_size(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun int i;
24*4882a593Smuzhiyun u32 temp;
25*4882a593Smuzhiyun struct aper_size_info_32 *values;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
28*4882a593Smuzhiyun temp &= ~(0xfffffff0);
29*4882a593Smuzhiyun values = A_SIZE_32(agp_bridge->driver->aperture_sizes);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
32*4882a593Smuzhiyun if (temp == values[i].size_value) {
33*4882a593Smuzhiyun agp_bridge->previous_size =
34*4882a593Smuzhiyun agp_bridge->current_size = (void *) (values + i);
35*4882a593Smuzhiyun agp_bridge->aperture_size_idx = i;
36*4882a593Smuzhiyun return values[i].size;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
ali_tlbflush(struct agp_memory * mem)43*4882a593Smuzhiyun static void ali_tlbflush(struct agp_memory *mem)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun u32 temp;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
48*4882a593Smuzhiyun temp &= 0xfffffff0;
49*4882a593Smuzhiyun temp |= (1<<0 | 1<<1);
50*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, temp);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
ali_cleanup(void)53*4882a593Smuzhiyun static void ali_cleanup(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct aper_size_info_32 *previous_size;
56*4882a593Smuzhiyun u32 temp;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun previous_size = A_SIZE_32(agp_bridge->previous_size);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
61*4882a593Smuzhiyun // clear tag
62*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
63*4882a593Smuzhiyun ((temp & 0xffffff00) | 0x00000001|0x00000002));
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
66*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
67*4882a593Smuzhiyun ((temp & 0x00000ff0) | previous_size->size_value));
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
ali_configure(void)70*4882a593Smuzhiyun static int ali_configure(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u32 temp;
73*4882a593Smuzhiyun struct aper_size_info_32 *current_size;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun current_size = A_SIZE_32(agp_bridge->current_size);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* aperture size and gatt addr */
78*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
79*4882a593Smuzhiyun temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
80*4882a593Smuzhiyun | (current_size->size_value & 0xf));
81*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* tlb control */
84*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
85*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* address to map to */
88*4882a593Smuzhiyun agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
89*4882a593Smuzhiyun AGP_APERTURE_BAR);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #if 0
92*4882a593Smuzhiyun if (agp_bridge->type == ALI_M1541) {
93*4882a593Smuzhiyun u32 nlvm_addr = 0;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun switch (current_size->size_value) {
96*4882a593Smuzhiyun case 0: break;
97*4882a593Smuzhiyun case 1: nlvm_addr = 0x100000;break;
98*4882a593Smuzhiyun case 2: nlvm_addr = 0x200000;break;
99*4882a593Smuzhiyun case 3: nlvm_addr = 0x400000;break;
100*4882a593Smuzhiyun case 4: nlvm_addr = 0x800000;break;
101*4882a593Smuzhiyun case 6: nlvm_addr = 0x1000000;break;
102*4882a593Smuzhiyun case 7: nlvm_addr = 0x2000000;break;
103*4882a593Smuzhiyun case 8: nlvm_addr = 0x4000000;break;
104*4882a593Smuzhiyun case 9: nlvm_addr = 0x8000000;break;
105*4882a593Smuzhiyun case 10: nlvm_addr = 0x10000000;break;
106*4882a593Smuzhiyun default: break;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun nlvm_addr--;
109*4882a593Smuzhiyun nlvm_addr&=0xfff00000;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun nlvm_addr+= agp_bridge->gart_bus_addr;
112*4882a593Smuzhiyun nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
113*4882a593Smuzhiyun dev_info(&agp_bridge->dev->dev, "nlvm top &base = %8x\n",
114*4882a593Smuzhiyun nlvm_addr);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun #endif
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
119*4882a593Smuzhiyun temp &= 0xffffff7f; //enable TLB
120*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun
m1541_cache_flush(void)126*4882a593Smuzhiyun static void m1541_cache_flush(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun int i, page_count;
129*4882a593Smuzhiyun u32 temp;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun global_cache_flush();
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
134*4882a593Smuzhiyun for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
135*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
136*4882a593Smuzhiyun &temp);
137*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
138*4882a593Smuzhiyun (((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
139*4882a593Smuzhiyun (agp_bridge->gatt_bus_addr + i)) |
140*4882a593Smuzhiyun ALI_CACHE_FLUSH_EN));
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
m1541_alloc_page(struct agp_bridge_data * bridge)144*4882a593Smuzhiyun static struct page *m1541_alloc_page(struct agp_bridge_data *bridge)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct page *page = agp_generic_alloc_page(agp_bridge);
147*4882a593Smuzhiyun u32 temp;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun if (!page)
150*4882a593Smuzhiyun return NULL;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
153*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
154*4882a593Smuzhiyun (((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
155*4882a593Smuzhiyun page_to_phys(page)) | ALI_CACHE_FLUSH_EN ));
156*4882a593Smuzhiyun return page;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
ali_destroy_page(struct page * page,int flags)159*4882a593Smuzhiyun static void ali_destroy_page(struct page *page, int flags)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun if (page) {
162*4882a593Smuzhiyun if (flags & AGP_PAGE_DESTROY_UNMAP) {
163*4882a593Smuzhiyun global_cache_flush(); /* is this really needed? --hch */
164*4882a593Smuzhiyun agp_generic_destroy_page(page, flags);
165*4882a593Smuzhiyun } else
166*4882a593Smuzhiyun agp_generic_destroy_page(page, flags);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
m1541_destroy_page(struct page * page,int flags)170*4882a593Smuzhiyun static void m1541_destroy_page(struct page *page, int flags)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun u32 temp;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (page == NULL)
175*4882a593Smuzhiyun return;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (flags & AGP_PAGE_DESTROY_UNMAP) {
178*4882a593Smuzhiyun global_cache_flush();
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
181*4882a593Smuzhiyun pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
182*4882a593Smuzhiyun (((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
183*4882a593Smuzhiyun page_to_phys(page)) | ALI_CACHE_FLUSH_EN));
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun agp_generic_destroy_page(page, flags);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* Setup function */
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static const struct aper_size_info_32 ali_generic_sizes[7] =
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun {256, 65536, 6, 10},
194*4882a593Smuzhiyun {128, 32768, 5, 9},
195*4882a593Smuzhiyun {64, 16384, 4, 8},
196*4882a593Smuzhiyun {32, 8192, 3, 7},
197*4882a593Smuzhiyun {16, 4096, 2, 6},
198*4882a593Smuzhiyun {8, 2048, 1, 4},
199*4882a593Smuzhiyun {4, 1024, 0, 3}
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun static const struct agp_bridge_driver ali_generic_bridge = {
203*4882a593Smuzhiyun .owner = THIS_MODULE,
204*4882a593Smuzhiyun .aperture_sizes = ali_generic_sizes,
205*4882a593Smuzhiyun .size_type = U32_APER_SIZE,
206*4882a593Smuzhiyun .num_aperture_sizes = 7,
207*4882a593Smuzhiyun .needs_scratch_page = true,
208*4882a593Smuzhiyun .configure = ali_configure,
209*4882a593Smuzhiyun .fetch_size = ali_fetch_size,
210*4882a593Smuzhiyun .cleanup = ali_cleanup,
211*4882a593Smuzhiyun .tlb_flush = ali_tlbflush,
212*4882a593Smuzhiyun .mask_memory = agp_generic_mask_memory,
213*4882a593Smuzhiyun .masks = NULL,
214*4882a593Smuzhiyun .agp_enable = agp_generic_enable,
215*4882a593Smuzhiyun .cache_flush = global_cache_flush,
216*4882a593Smuzhiyun .create_gatt_table = agp_generic_create_gatt_table,
217*4882a593Smuzhiyun .free_gatt_table = agp_generic_free_gatt_table,
218*4882a593Smuzhiyun .insert_memory = agp_generic_insert_memory,
219*4882a593Smuzhiyun .remove_memory = agp_generic_remove_memory,
220*4882a593Smuzhiyun .alloc_by_type = agp_generic_alloc_by_type,
221*4882a593Smuzhiyun .free_by_type = agp_generic_free_by_type,
222*4882a593Smuzhiyun .agp_alloc_page = agp_generic_alloc_page,
223*4882a593Smuzhiyun .agp_destroy_page = ali_destroy_page,
224*4882a593Smuzhiyun .agp_type_to_mask_type = agp_generic_type_to_mask_type,
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun static const struct agp_bridge_driver ali_m1541_bridge = {
228*4882a593Smuzhiyun .owner = THIS_MODULE,
229*4882a593Smuzhiyun .aperture_sizes = ali_generic_sizes,
230*4882a593Smuzhiyun .size_type = U32_APER_SIZE,
231*4882a593Smuzhiyun .num_aperture_sizes = 7,
232*4882a593Smuzhiyun .configure = ali_configure,
233*4882a593Smuzhiyun .fetch_size = ali_fetch_size,
234*4882a593Smuzhiyun .cleanup = ali_cleanup,
235*4882a593Smuzhiyun .tlb_flush = ali_tlbflush,
236*4882a593Smuzhiyun .mask_memory = agp_generic_mask_memory,
237*4882a593Smuzhiyun .masks = NULL,
238*4882a593Smuzhiyun .agp_enable = agp_generic_enable,
239*4882a593Smuzhiyun .cache_flush = m1541_cache_flush,
240*4882a593Smuzhiyun .create_gatt_table = agp_generic_create_gatt_table,
241*4882a593Smuzhiyun .free_gatt_table = agp_generic_free_gatt_table,
242*4882a593Smuzhiyun .insert_memory = agp_generic_insert_memory,
243*4882a593Smuzhiyun .remove_memory = agp_generic_remove_memory,
244*4882a593Smuzhiyun .alloc_by_type = agp_generic_alloc_by_type,
245*4882a593Smuzhiyun .free_by_type = agp_generic_free_by_type,
246*4882a593Smuzhiyun .agp_alloc_page = m1541_alloc_page,
247*4882a593Smuzhiyun .agp_destroy_page = m1541_destroy_page,
248*4882a593Smuzhiyun .agp_type_to_mask_type = agp_generic_type_to_mask_type,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static struct agp_device_ids ali_agp_device_ids[] =
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1541,
256*4882a593Smuzhiyun .chipset_name = "M1541",
257*4882a593Smuzhiyun },
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1621,
260*4882a593Smuzhiyun .chipset_name = "M1621",
261*4882a593Smuzhiyun },
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1631,
264*4882a593Smuzhiyun .chipset_name = "M1631",
265*4882a593Smuzhiyun },
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1632,
268*4882a593Smuzhiyun .chipset_name = "M1632",
269*4882a593Smuzhiyun },
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1641,
272*4882a593Smuzhiyun .chipset_name = "M1641",
273*4882a593Smuzhiyun },
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1644,
276*4882a593Smuzhiyun .chipset_name = "M1644",
277*4882a593Smuzhiyun },
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1647,
280*4882a593Smuzhiyun .chipset_name = "M1647",
281*4882a593Smuzhiyun },
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1651,
284*4882a593Smuzhiyun .chipset_name = "M1651",
285*4882a593Smuzhiyun },
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1671,
288*4882a593Smuzhiyun .chipset_name = "M1671",
289*4882a593Smuzhiyun },
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1681,
292*4882a593Smuzhiyun .chipset_name = "M1681",
293*4882a593Smuzhiyun },
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun .device_id = PCI_DEVICE_ID_AL_M1683,
296*4882a593Smuzhiyun .chipset_name = "M1683",
297*4882a593Smuzhiyun },
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun { }, /* dummy final entry, always present */
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun
agp_ali_probe(struct pci_dev * pdev,const struct pci_device_id * ent)302*4882a593Smuzhiyun static int agp_ali_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct agp_device_ids *devs = ali_agp_device_ids;
305*4882a593Smuzhiyun struct agp_bridge_data *bridge;
306*4882a593Smuzhiyun u8 hidden_1621_id, cap_ptr;
307*4882a593Smuzhiyun int j;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
310*4882a593Smuzhiyun if (!cap_ptr)
311*4882a593Smuzhiyun return -ENODEV;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /* probe for known chipsets */
314*4882a593Smuzhiyun for (j = 0; devs[j].chipset_name; j++) {
315*4882a593Smuzhiyun if (pdev->device == devs[j].device_id)
316*4882a593Smuzhiyun goto found;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun dev_err(&pdev->dev, "unsupported ALi chipset [%04x/%04x])\n",
320*4882a593Smuzhiyun pdev->vendor, pdev->device);
321*4882a593Smuzhiyun return -ENODEV;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun found:
325*4882a593Smuzhiyun bridge = agp_alloc_bridge();
326*4882a593Smuzhiyun if (!bridge)
327*4882a593Smuzhiyun return -ENOMEM;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun bridge->dev = pdev;
330*4882a593Smuzhiyun bridge->capndx = cap_ptr;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun switch (pdev->device) {
333*4882a593Smuzhiyun case PCI_DEVICE_ID_AL_M1541:
334*4882a593Smuzhiyun bridge->driver = &ali_m1541_bridge;
335*4882a593Smuzhiyun break;
336*4882a593Smuzhiyun case PCI_DEVICE_ID_AL_M1621:
337*4882a593Smuzhiyun pci_read_config_byte(pdev, 0xFB, &hidden_1621_id);
338*4882a593Smuzhiyun switch (hidden_1621_id) {
339*4882a593Smuzhiyun case 0x31:
340*4882a593Smuzhiyun devs[j].chipset_name = "M1631";
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun case 0x32:
343*4882a593Smuzhiyun devs[j].chipset_name = "M1632";
344*4882a593Smuzhiyun break;
345*4882a593Smuzhiyun case 0x41:
346*4882a593Smuzhiyun devs[j].chipset_name = "M1641";
347*4882a593Smuzhiyun break;
348*4882a593Smuzhiyun case 0x43:
349*4882a593Smuzhiyun devs[j].chipset_name = "M1621";
350*4882a593Smuzhiyun break;
351*4882a593Smuzhiyun case 0x47:
352*4882a593Smuzhiyun devs[j].chipset_name = "M1647";
353*4882a593Smuzhiyun break;
354*4882a593Smuzhiyun case 0x51:
355*4882a593Smuzhiyun devs[j].chipset_name = "M1651";
356*4882a593Smuzhiyun break;
357*4882a593Smuzhiyun default:
358*4882a593Smuzhiyun break;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun fallthrough;
361*4882a593Smuzhiyun default:
362*4882a593Smuzhiyun bridge->driver = &ali_generic_bridge;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun dev_info(&pdev->dev, "ALi %s chipset\n", devs[j].chipset_name);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* Fill in the mode register */
368*4882a593Smuzhiyun pci_read_config_dword(pdev,
369*4882a593Smuzhiyun bridge->capndx+PCI_AGP_STATUS,
370*4882a593Smuzhiyun &bridge->mode);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun pci_set_drvdata(pdev, bridge);
373*4882a593Smuzhiyun return agp_add_bridge(bridge);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
agp_ali_remove(struct pci_dev * pdev)376*4882a593Smuzhiyun static void agp_ali_remove(struct pci_dev *pdev)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun agp_remove_bridge(bridge);
381*4882a593Smuzhiyun agp_put_bridge(bridge);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun static const struct pci_device_id agp_ali_pci_table[] = {
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun .class = (PCI_CLASS_BRIDGE_HOST << 8),
387*4882a593Smuzhiyun .class_mask = ~0,
388*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_AL,
389*4882a593Smuzhiyun .device = PCI_ANY_ID,
390*4882a593Smuzhiyun .subvendor = PCI_ANY_ID,
391*4882a593Smuzhiyun .subdevice = PCI_ANY_ID,
392*4882a593Smuzhiyun },
393*4882a593Smuzhiyun { }
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, agp_ali_pci_table);
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun static struct pci_driver agp_ali_pci_driver = {
399*4882a593Smuzhiyun .name = "agpgart-ali",
400*4882a593Smuzhiyun .id_table = agp_ali_pci_table,
401*4882a593Smuzhiyun .probe = agp_ali_probe,
402*4882a593Smuzhiyun .remove = agp_ali_remove,
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun
agp_ali_init(void)405*4882a593Smuzhiyun static int __init agp_ali_init(void)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun if (agp_off)
408*4882a593Smuzhiyun return -EINVAL;
409*4882a593Smuzhiyun return pci_register_driver(&agp_ali_pci_driver);
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
agp_ali_cleanup(void)412*4882a593Smuzhiyun static void __exit agp_ali_cleanup(void)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun pci_unregister_driver(&agp_ali_pci_driver);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun module_init(agp_ali_init);
418*4882a593Smuzhiyun module_exit(agp_ali_cleanup);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun MODULE_AUTHOR("Dave Jones");
421*4882a593Smuzhiyun MODULE_LICENSE("GPL and additional rights");
422*4882a593Smuzhiyun
423