xref: /OK3568_Linux_fs/kernel/drivers/bus/ts-nbus.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * NBUS driver for TS-4600 based boards
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (c) 2016 - Savoir-faire Linux
5*4882a593Smuzhiyun  * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public
8*4882a593Smuzhiyun  * License version 2. This program is licensed "as is" without any
9*4882a593Smuzhiyun  * warranty of any kind, whether express or implied.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This driver implements a GPIOs bit-banged bus, called the NBUS by Technologic
12*4882a593Smuzhiyun  * Systems. It is used to communicate with the peripherals in the FPGA on the
13*4882a593Smuzhiyun  * TS-4600 SoM.
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/bitops.h>
17*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/mutex.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/pwm.h>
24*4882a593Smuzhiyun #include <linux/ts-nbus.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define TS_NBUS_DIRECTION_IN  0
27*4882a593Smuzhiyun #define TS_NBUS_DIRECTION_OUT 1
28*4882a593Smuzhiyun #define TS_NBUS_WRITE_ADR 0
29*4882a593Smuzhiyun #define TS_NBUS_WRITE_VAL 1
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct ts_nbus {
32*4882a593Smuzhiyun 	struct pwm_device *pwm;
33*4882a593Smuzhiyun 	struct gpio_descs *data;
34*4882a593Smuzhiyun 	struct gpio_desc *csn;
35*4882a593Smuzhiyun 	struct gpio_desc *txrx;
36*4882a593Smuzhiyun 	struct gpio_desc *strobe;
37*4882a593Smuzhiyun 	struct gpio_desc *ale;
38*4882a593Smuzhiyun 	struct gpio_desc *rdy;
39*4882a593Smuzhiyun 	struct mutex lock;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun  * request all gpios required by the bus.
44*4882a593Smuzhiyun  */
ts_nbus_init_pdata(struct platform_device * pdev,struct ts_nbus * ts_nbus)45*4882a593Smuzhiyun static int ts_nbus_init_pdata(struct platform_device *pdev, struct ts_nbus
46*4882a593Smuzhiyun 		*ts_nbus)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	ts_nbus->data = devm_gpiod_get_array(&pdev->dev, "ts,data",
49*4882a593Smuzhiyun 			GPIOD_OUT_HIGH);
50*4882a593Smuzhiyun 	if (IS_ERR(ts_nbus->data)) {
51*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to retrieve ts,data-gpio from dts\n");
52*4882a593Smuzhiyun 		return PTR_ERR(ts_nbus->data);
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	ts_nbus->csn = devm_gpiod_get(&pdev->dev, "ts,csn", GPIOD_OUT_HIGH);
56*4882a593Smuzhiyun 	if (IS_ERR(ts_nbus->csn)) {
57*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to retrieve ts,csn-gpio from dts\n");
58*4882a593Smuzhiyun 		return PTR_ERR(ts_nbus->csn);
59*4882a593Smuzhiyun 	}
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	ts_nbus->txrx = devm_gpiod_get(&pdev->dev, "ts,txrx", GPIOD_OUT_HIGH);
62*4882a593Smuzhiyun 	if (IS_ERR(ts_nbus->txrx)) {
63*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to retrieve ts,txrx-gpio from dts\n");
64*4882a593Smuzhiyun 		return PTR_ERR(ts_nbus->txrx);
65*4882a593Smuzhiyun 	}
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	ts_nbus->strobe = devm_gpiod_get(&pdev->dev, "ts,strobe", GPIOD_OUT_HIGH);
68*4882a593Smuzhiyun 	if (IS_ERR(ts_nbus->strobe)) {
69*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to retrieve ts,strobe-gpio from dts\n");
70*4882a593Smuzhiyun 		return PTR_ERR(ts_nbus->strobe);
71*4882a593Smuzhiyun 	}
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	ts_nbus->ale = devm_gpiod_get(&pdev->dev, "ts,ale", GPIOD_OUT_HIGH);
74*4882a593Smuzhiyun 	if (IS_ERR(ts_nbus->ale)) {
75*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to retrieve ts,ale-gpio from dts\n");
76*4882a593Smuzhiyun 		return PTR_ERR(ts_nbus->ale);
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	ts_nbus->rdy = devm_gpiod_get(&pdev->dev, "ts,rdy", GPIOD_IN);
80*4882a593Smuzhiyun 	if (IS_ERR(ts_nbus->rdy)) {
81*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to retrieve ts,rdy-gpio from dts\n");
82*4882a593Smuzhiyun 		return PTR_ERR(ts_nbus->rdy);
83*4882a593Smuzhiyun 	}
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun  * the data gpios are used for reading and writing values, their directions
90*4882a593Smuzhiyun  * should be adjusted accordingly.
91*4882a593Smuzhiyun  */
ts_nbus_set_direction(struct ts_nbus * ts_nbus,int direction)92*4882a593Smuzhiyun static void ts_nbus_set_direction(struct ts_nbus *ts_nbus, int direction)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	int i;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	for (i = 0; i < 8; i++) {
97*4882a593Smuzhiyun 		if (direction == TS_NBUS_DIRECTION_IN)
98*4882a593Smuzhiyun 			gpiod_direction_input(ts_nbus->data->desc[i]);
99*4882a593Smuzhiyun 		else
100*4882a593Smuzhiyun 			/* when used as output the default state of the data
101*4882a593Smuzhiyun 			 * lines are set to high */
102*4882a593Smuzhiyun 			gpiod_direction_output(ts_nbus->data->desc[i], 1);
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun  * reset the bus in its initial state.
108*4882a593Smuzhiyun  * The data, csn, strobe and ale lines must be zero'ed to let the FPGA knows a
109*4882a593Smuzhiyun  * new transaction can be process.
110*4882a593Smuzhiyun  */
ts_nbus_reset_bus(struct ts_nbus * ts_nbus)111*4882a593Smuzhiyun static void ts_nbus_reset_bus(struct ts_nbus *ts_nbus)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	DECLARE_BITMAP(values, 8);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	values[0] = 0;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	gpiod_set_array_value_cansleep(8, ts_nbus->data->desc,
118*4882a593Smuzhiyun 				       ts_nbus->data->info, values);
119*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->csn, 0);
120*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->strobe, 0);
121*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->ale, 0);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun  * let the FPGA knows it can process.
126*4882a593Smuzhiyun  */
ts_nbus_start_transaction(struct ts_nbus * ts_nbus)127*4882a593Smuzhiyun static void ts_nbus_start_transaction(struct ts_nbus *ts_nbus)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->strobe, 1);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun  * read a byte value from the data gpios.
134*4882a593Smuzhiyun  * return 0 on success or negative errno on failure.
135*4882a593Smuzhiyun  */
ts_nbus_read_byte(struct ts_nbus * ts_nbus,u8 * val)136*4882a593Smuzhiyun static int ts_nbus_read_byte(struct ts_nbus *ts_nbus, u8 *val)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	struct gpio_descs *gpios = ts_nbus->data;
139*4882a593Smuzhiyun 	int ret, i;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	*val = 0;
142*4882a593Smuzhiyun 	for (i = 0; i < 8; i++) {
143*4882a593Smuzhiyun 		ret = gpiod_get_value_cansleep(gpios->desc[i]);
144*4882a593Smuzhiyun 		if (ret < 0)
145*4882a593Smuzhiyun 			return ret;
146*4882a593Smuzhiyun 		if (ret)
147*4882a593Smuzhiyun 			*val |= BIT(i);
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun /*
154*4882a593Smuzhiyun  * set the data gpios accordingly to the byte value.
155*4882a593Smuzhiyun  */
ts_nbus_write_byte(struct ts_nbus * ts_nbus,u8 byte)156*4882a593Smuzhiyun static void ts_nbus_write_byte(struct ts_nbus *ts_nbus, u8 byte)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	struct gpio_descs *gpios = ts_nbus->data;
159*4882a593Smuzhiyun 	DECLARE_BITMAP(values, 8);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	values[0] = byte;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	gpiod_set_array_value_cansleep(8, gpios->desc, gpios->info, values);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun  * reading the bus consists of resetting the bus, then notifying the FPGA to
168*4882a593Smuzhiyun  * send the data in the data gpios and return the read value.
169*4882a593Smuzhiyun  * return 0 on success or negative errno on failure.
170*4882a593Smuzhiyun  */
ts_nbus_read_bus(struct ts_nbus * ts_nbus,u8 * val)171*4882a593Smuzhiyun static int ts_nbus_read_bus(struct ts_nbus *ts_nbus, u8 *val)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	ts_nbus_reset_bus(ts_nbus);
174*4882a593Smuzhiyun 	ts_nbus_start_transaction(ts_nbus);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	return ts_nbus_read_byte(ts_nbus, val);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun  * writing to the bus consists of resetting the bus, then define the type of
181*4882a593Smuzhiyun  * command (address/value), write the data and notify the FPGA to retrieve the
182*4882a593Smuzhiyun  * value in the data gpios.
183*4882a593Smuzhiyun  */
ts_nbus_write_bus(struct ts_nbus * ts_nbus,int cmd,u8 val)184*4882a593Smuzhiyun static void ts_nbus_write_bus(struct ts_nbus *ts_nbus, int cmd, u8 val)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	ts_nbus_reset_bus(ts_nbus);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	if (cmd == TS_NBUS_WRITE_ADR)
189*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ts_nbus->ale, 1);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	ts_nbus_write_byte(ts_nbus, val);
192*4882a593Smuzhiyun 	ts_nbus_start_transaction(ts_nbus);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun  * read the value in the FPGA register at the given address.
197*4882a593Smuzhiyun  * return 0 on success or negative errno on failure.
198*4882a593Smuzhiyun  */
ts_nbus_read(struct ts_nbus * ts_nbus,u8 adr,u16 * val)199*4882a593Smuzhiyun int ts_nbus_read(struct ts_nbus *ts_nbus, u8 adr, u16 *val)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun 	int ret, i;
202*4882a593Smuzhiyun 	u8 byte;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	/* bus access must be atomic */
205*4882a593Smuzhiyun 	mutex_lock(&ts_nbus->lock);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* set the bus in read mode */
208*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->txrx, 0);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	/* write address */
211*4882a593Smuzhiyun 	ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_ADR, adr);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	/* set the data gpios direction as input before reading */
214*4882a593Smuzhiyun 	ts_nbus_set_direction(ts_nbus, TS_NBUS_DIRECTION_IN);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* reading value MSB first */
217*4882a593Smuzhiyun 	do {
218*4882a593Smuzhiyun 		*val = 0;
219*4882a593Smuzhiyun 		byte = 0;
220*4882a593Smuzhiyun 		for (i = 1; i >= 0; i--) {
221*4882a593Smuzhiyun 			/* read a byte from the bus, leave on error */
222*4882a593Smuzhiyun 			ret = ts_nbus_read_bus(ts_nbus, &byte);
223*4882a593Smuzhiyun 			if (ret < 0)
224*4882a593Smuzhiyun 				goto err;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 			/* append the byte read to the final value */
227*4882a593Smuzhiyun 			*val |= byte << (i * 8);
228*4882a593Smuzhiyun 		}
229*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ts_nbus->csn, 1);
230*4882a593Smuzhiyun 		ret = gpiod_get_value_cansleep(ts_nbus->rdy);
231*4882a593Smuzhiyun 	} while (ret);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun err:
234*4882a593Smuzhiyun 	/* restore the data gpios direction as output after reading */
235*4882a593Smuzhiyun 	ts_nbus_set_direction(ts_nbus, TS_NBUS_DIRECTION_OUT);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	mutex_unlock(&ts_nbus->lock);
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ts_nbus_read);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /*
244*4882a593Smuzhiyun  * write the desired value in the FPGA register at the given address.
245*4882a593Smuzhiyun  */
ts_nbus_write(struct ts_nbus * ts_nbus,u8 adr,u16 val)246*4882a593Smuzhiyun int ts_nbus_write(struct ts_nbus *ts_nbus, u8 adr, u16 val)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	int i;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	/* bus access must be atomic */
251*4882a593Smuzhiyun 	mutex_lock(&ts_nbus->lock);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	/* set the bus in write mode */
254*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->txrx, 1);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	/* write address */
257*4882a593Smuzhiyun 	ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_ADR, adr);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	/* writing value MSB first */
260*4882a593Smuzhiyun 	for (i = 1; i >= 0; i--)
261*4882a593Smuzhiyun 		ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_VAL, (u8)(val >> (i * 8)));
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	/* wait for completion */
264*4882a593Smuzhiyun 	gpiod_set_value_cansleep(ts_nbus->csn, 1);
265*4882a593Smuzhiyun 	while (gpiod_get_value_cansleep(ts_nbus->rdy) != 0) {
266*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ts_nbus->csn, 0);
267*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ts_nbus->csn, 1);
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	mutex_unlock(&ts_nbus->lock);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	return 0;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ts_nbus_write);
275*4882a593Smuzhiyun 
ts_nbus_probe(struct platform_device * pdev)276*4882a593Smuzhiyun static int ts_nbus_probe(struct platform_device *pdev)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun 	struct pwm_device *pwm;
279*4882a593Smuzhiyun 	struct pwm_args pargs;
280*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
281*4882a593Smuzhiyun 	struct ts_nbus *ts_nbus;
282*4882a593Smuzhiyun 	int ret;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	ts_nbus = devm_kzalloc(dev, sizeof(*ts_nbus), GFP_KERNEL);
285*4882a593Smuzhiyun 	if (!ts_nbus)
286*4882a593Smuzhiyun 		return -ENOMEM;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	mutex_init(&ts_nbus->lock);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	ret = ts_nbus_init_pdata(pdev, ts_nbus);
291*4882a593Smuzhiyun 	if (ret < 0)
292*4882a593Smuzhiyun 		return ret;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	pwm = devm_pwm_get(dev, NULL);
295*4882a593Smuzhiyun 	if (IS_ERR(pwm)) {
296*4882a593Smuzhiyun 		ret = PTR_ERR(pwm);
297*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
298*4882a593Smuzhiyun 			dev_err(dev, "unable to request PWM\n");
299*4882a593Smuzhiyun 		return ret;
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	pwm_get_args(pwm, &pargs);
303*4882a593Smuzhiyun 	if (!pargs.period) {
304*4882a593Smuzhiyun 		dev_err(&pdev->dev, "invalid PWM period\n");
305*4882a593Smuzhiyun 		return -EINVAL;
306*4882a593Smuzhiyun 	}
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/*
309*4882a593Smuzhiyun 	 * FIXME: pwm_apply_args() should be removed when switching to
310*4882a593Smuzhiyun 	 * the atomic PWM API.
311*4882a593Smuzhiyun 	 */
312*4882a593Smuzhiyun 	pwm_apply_args(pwm);
313*4882a593Smuzhiyun 	ret = pwm_config(pwm, pargs.period, pargs.period);
314*4882a593Smuzhiyun 	if (ret < 0)
315*4882a593Smuzhiyun 		return ret;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	/*
318*4882a593Smuzhiyun 	 * we can now start the FPGA and populate the peripherals.
319*4882a593Smuzhiyun 	 */
320*4882a593Smuzhiyun 	pwm_enable(pwm);
321*4882a593Smuzhiyun 	ts_nbus->pwm = pwm;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	/*
324*4882a593Smuzhiyun 	 * let the child nodes retrieve this instance of the ts-nbus.
325*4882a593Smuzhiyun 	 */
326*4882a593Smuzhiyun 	dev_set_drvdata(dev, ts_nbus);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
329*4882a593Smuzhiyun 	if (ret < 0)
330*4882a593Smuzhiyun 		return ret;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	dev_info(dev, "initialized\n");
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	return 0;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun 
ts_nbus_remove(struct platform_device * pdev)337*4882a593Smuzhiyun static int ts_nbus_remove(struct platform_device *pdev)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun 	struct ts_nbus *ts_nbus = dev_get_drvdata(&pdev->dev);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	/* shutdown the FPGA */
342*4882a593Smuzhiyun 	mutex_lock(&ts_nbus->lock);
343*4882a593Smuzhiyun 	pwm_disable(ts_nbus->pwm);
344*4882a593Smuzhiyun 	mutex_unlock(&ts_nbus->lock);
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun static const struct of_device_id ts_nbus_of_match[] = {
350*4882a593Smuzhiyun 	{ .compatible = "technologic,ts-nbus", },
351*4882a593Smuzhiyun 	{ },
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ts_nbus_of_match);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static struct platform_driver ts_nbus_driver = {
356*4882a593Smuzhiyun 	.probe		= ts_nbus_probe,
357*4882a593Smuzhiyun 	.remove		= ts_nbus_remove,
358*4882a593Smuzhiyun 	.driver		= {
359*4882a593Smuzhiyun 		.name	= "ts_nbus",
360*4882a593Smuzhiyun 		.of_match_table = ts_nbus_of_match,
361*4882a593Smuzhiyun 	},
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun module_platform_driver(ts_nbus_driver);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun MODULE_ALIAS("platform:ts_nbus");
367*4882a593Smuzhiyun MODULE_AUTHOR("Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>");
368*4882a593Smuzhiyun MODULE_DESCRIPTION("Technologic Systems NBUS");
369*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
370