1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) 2001 San Mehat <nettwerk@valinux.com>
6*4882a593Smuzhiyun * (C) 2001 Johannes Erdfelt <jerdfelt@valinux.com>
7*4882a593Smuzhiyun * (C) 2001 NeilBrown <neilb@cse.unsw.edu.au>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This driver for the Micro Memory PCI Memory Module with Battery Backup
10*4882a593Smuzhiyun * is Copyright Micro Memory Inc 2001-2002. All rights reserved.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This driver provides a standard block device interface for Micro Memory(tm)
13*4882a593Smuzhiyun * PCI based RAM boards.
14*4882a593Smuzhiyun * 10/05/01: Phap Nguyen - Rebuilt the driver
15*4882a593Smuzhiyun * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning
16*4882a593Smuzhiyun * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn
17*4882a593Smuzhiyun * - use stand disk partitioning (so fdisk works).
18*4882a593Smuzhiyun * 08nov2001:NeilBrown - change driver name from "mm" to "umem"
19*4882a593Smuzhiyun * - incorporate into main kernel
20*4882a593Smuzhiyun * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet
21*4882a593Smuzhiyun * - use spin_lock_bh instead of _irq
22*4882a593Smuzhiyun * - Never block on make_request. queue
23*4882a593Smuzhiyun * bh's instead.
24*4882a593Smuzhiyun * - unregister umem from devfs at mod unload
25*4882a593Smuzhiyun * - Change version to 2.3
26*4882a593Smuzhiyun * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal)
27*4882a593Smuzhiyun * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA
28*4882a593Smuzhiyun * 15May2002:NeilBrown - convert to bio for 2.5
29*4882a593Smuzhiyun * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect
30*4882a593Smuzhiyun * - a sequence of writes that cover the card, and
31*4882a593Smuzhiyun * - set initialised bit then.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */
35*4882a593Smuzhiyun #include <linux/fs.h>
36*4882a593Smuzhiyun #include <linux/bio.h>
37*4882a593Smuzhiyun #include <linux/kernel.h>
38*4882a593Smuzhiyun #include <linux/mm.h>
39*4882a593Smuzhiyun #include <linux/mman.h>
40*4882a593Smuzhiyun #include <linux/gfp.h>
41*4882a593Smuzhiyun #include <linux/ioctl.h>
42*4882a593Smuzhiyun #include <linux/module.h>
43*4882a593Smuzhiyun #include <linux/init.h>
44*4882a593Smuzhiyun #include <linux/interrupt.h>
45*4882a593Smuzhiyun #include <linux/timer.h>
46*4882a593Smuzhiyun #include <linux/pci.h>
47*4882a593Smuzhiyun #include <linux/dma-mapping.h>
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include <linux/fcntl.h> /* O_ACCMODE */
50*4882a593Smuzhiyun #include <linux/hdreg.h> /* HDIO_GETGEO */
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #include "umem.h"
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #include <linux/uaccess.h>
55*4882a593Smuzhiyun #include <asm/io.h>
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define MM_MAXCARDS 4
58*4882a593Smuzhiyun #define MM_RAHEAD 2 /* two sectors */
59*4882a593Smuzhiyun #define MM_BLKSIZE 1024 /* 1k blocks */
60*4882a593Smuzhiyun #define MM_HARDSECT 512 /* 512-byte hardware sectors */
61*4882a593Smuzhiyun #define MM_SHIFT 6 /* max 64 partitions on 4 cards */
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * Version Information
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define DRIVER_NAME "umem"
68*4882a593Smuzhiyun #define DRIVER_VERSION "v2.3"
69*4882a593Smuzhiyun #define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown"
70*4882a593Smuzhiyun #define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver"
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static int debug;
73*4882a593Smuzhiyun /* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */
74*4882a593Smuzhiyun #define HW_TRACE(x)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define DEBUG_LED_ON_TRANSFER 0x01
77*4882a593Smuzhiyun #define DEBUG_BATTERY_POLLING 0x02
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun module_param(debug, int, 0644);
80*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug bitmask");
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static int pci_read_cmd = 0x0C; /* Read Multiple */
83*4882a593Smuzhiyun module_param(pci_read_cmd, int, 0);
84*4882a593Smuzhiyun MODULE_PARM_DESC(pci_read_cmd, "PCI read command");
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static int pci_write_cmd = 0x0F; /* Write and Invalidate */
87*4882a593Smuzhiyun module_param(pci_write_cmd, int, 0);
88*4882a593Smuzhiyun MODULE_PARM_DESC(pci_write_cmd, "PCI write command");
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static int pci_cmds;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static int major_nr;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #include <linux/blkdev.h>
95*4882a593Smuzhiyun #include <linux/blkpg.h>
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun struct cardinfo {
98*4882a593Smuzhiyun struct pci_dev *dev;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun unsigned char __iomem *csr_remap;
101*4882a593Smuzhiyun unsigned int mm_size; /* size in kbytes */
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun unsigned int init_size; /* initial segment, in sectors,
104*4882a593Smuzhiyun * that we know to
105*4882a593Smuzhiyun * have been written
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun struct bio *bio, *currentbio, **biotail;
108*4882a593Smuzhiyun struct bvec_iter current_iter;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct request_queue *queue;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun struct mm_page {
113*4882a593Smuzhiyun dma_addr_t page_dma;
114*4882a593Smuzhiyun struct mm_dma_desc *desc;
115*4882a593Smuzhiyun int cnt, headcnt;
116*4882a593Smuzhiyun struct bio *bio, **biotail;
117*4882a593Smuzhiyun struct bvec_iter iter;
118*4882a593Smuzhiyun } mm_pages[2];
119*4882a593Smuzhiyun #define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc))
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun int Active, Ready;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct tasklet_struct tasklet;
124*4882a593Smuzhiyun unsigned int dma_status;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun struct {
127*4882a593Smuzhiyun int good;
128*4882a593Smuzhiyun int warned;
129*4882a593Smuzhiyun unsigned long last_change;
130*4882a593Smuzhiyun } battery[2];
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun spinlock_t lock;
133*4882a593Smuzhiyun int check_batteries;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun int flags;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static struct cardinfo cards[MM_MAXCARDS];
139*4882a593Smuzhiyun static struct timer_list battery_timer;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun static int num_cards;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun static struct gendisk *mm_gendisk[MM_MAXCARDS];
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static void check_batteries(struct cardinfo *card);
146*4882a593Smuzhiyun
get_userbit(struct cardinfo * card,int bit)147*4882a593Smuzhiyun static int get_userbit(struct cardinfo *card, int bit)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun unsigned char led;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
152*4882a593Smuzhiyun return led & bit;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
set_userbit(struct cardinfo * card,int bit,unsigned char state)155*4882a593Smuzhiyun static int set_userbit(struct cardinfo *card, int bit, unsigned char state)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun unsigned char led;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
160*4882a593Smuzhiyun if (state)
161*4882a593Smuzhiyun led |= bit;
162*4882a593Smuzhiyun else
163*4882a593Smuzhiyun led &= ~bit;
164*4882a593Smuzhiyun writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun * NOTE: For the power LED, use the LED_POWER_* macros since they differ
171*4882a593Smuzhiyun */
set_led(struct cardinfo * card,int shift,unsigned char state)172*4882a593Smuzhiyun static void set_led(struct cardinfo *card, int shift, unsigned char state)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun unsigned char led;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
177*4882a593Smuzhiyun if (state == LED_FLIP)
178*4882a593Smuzhiyun led ^= (1<<shift);
179*4882a593Smuzhiyun else {
180*4882a593Smuzhiyun led &= ~(0x03 << shift);
181*4882a593Smuzhiyun led |= (state << shift);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #ifdef MM_DIAG
dump_regs(struct cardinfo * card)188*4882a593Smuzhiyun static void dump_regs(struct cardinfo *card)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun unsigned char *p;
191*4882a593Smuzhiyun int i, i1;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun p = card->csr_remap;
194*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
195*4882a593Smuzhiyun printk(KERN_DEBUG "%p ", p);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun for (i1 = 0; i1 < 16; i1++)
198*4882a593Smuzhiyun printk("%02x ", *p++);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun printk("\n");
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun #endif
204*4882a593Smuzhiyun
dump_dmastat(struct cardinfo * card,unsigned int dmastat)205*4882a593Smuzhiyun static void dump_dmastat(struct cardinfo *card, unsigned int dmastat)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - ");
208*4882a593Smuzhiyun if (dmastat & DMASCR_ANY_ERR)
209*4882a593Smuzhiyun printk(KERN_CONT "ANY_ERR ");
210*4882a593Smuzhiyun if (dmastat & DMASCR_MBE_ERR)
211*4882a593Smuzhiyun printk(KERN_CONT "MBE_ERR ");
212*4882a593Smuzhiyun if (dmastat & DMASCR_PARITY_ERR_REP)
213*4882a593Smuzhiyun printk(KERN_CONT "PARITY_ERR_REP ");
214*4882a593Smuzhiyun if (dmastat & DMASCR_PARITY_ERR_DET)
215*4882a593Smuzhiyun printk(KERN_CONT "PARITY_ERR_DET ");
216*4882a593Smuzhiyun if (dmastat & DMASCR_SYSTEM_ERR_SIG)
217*4882a593Smuzhiyun printk(KERN_CONT "SYSTEM_ERR_SIG ");
218*4882a593Smuzhiyun if (dmastat & DMASCR_TARGET_ABT)
219*4882a593Smuzhiyun printk(KERN_CONT "TARGET_ABT ");
220*4882a593Smuzhiyun if (dmastat & DMASCR_MASTER_ABT)
221*4882a593Smuzhiyun printk(KERN_CONT "MASTER_ABT ");
222*4882a593Smuzhiyun if (dmastat & DMASCR_CHAIN_COMPLETE)
223*4882a593Smuzhiyun printk(KERN_CONT "CHAIN_COMPLETE ");
224*4882a593Smuzhiyun if (dmastat & DMASCR_DMA_COMPLETE)
225*4882a593Smuzhiyun printk(KERN_CONT "DMA_COMPLETE ");
226*4882a593Smuzhiyun printk("\n");
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /*
230*4882a593Smuzhiyun * Theory of request handling
231*4882a593Smuzhiyun *
232*4882a593Smuzhiyun * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME
233*4882a593Smuzhiyun * We have two pages of mm_dma_desc, holding about 64 descriptors
234*4882a593Smuzhiyun * each. These are allocated at init time.
235*4882a593Smuzhiyun * One page is "Ready" and is either full, or can have request added.
236*4882a593Smuzhiyun * The other page might be "Active", which DMA is happening on it.
237*4882a593Smuzhiyun *
238*4882a593Smuzhiyun * Whenever IO on the active page completes, the Ready page is activated
239*4882a593Smuzhiyun * and the ex-Active page is clean out and made Ready.
240*4882a593Smuzhiyun * Otherwise the Ready page is only activated when it becomes full.
241*4882a593Smuzhiyun *
242*4882a593Smuzhiyun * If a request arrives while both pages a full, it is queued, and b_rdev is
243*4882a593Smuzhiyun * overloaded to record whether it was a read or a write.
244*4882a593Smuzhiyun *
245*4882a593Smuzhiyun * The interrupt handler only polls the device to clear the interrupt.
246*4882a593Smuzhiyun * The processing of the result is done in a tasklet.
247*4882a593Smuzhiyun */
248*4882a593Smuzhiyun
mm_start_io(struct cardinfo * card)249*4882a593Smuzhiyun static void mm_start_io(struct cardinfo *card)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun /* we have the lock, we know there is
252*4882a593Smuzhiyun * no IO active, and we know that card->Active
253*4882a593Smuzhiyun * is set
254*4882a593Smuzhiyun */
255*4882a593Smuzhiyun struct mm_dma_desc *desc;
256*4882a593Smuzhiyun struct mm_page *page;
257*4882a593Smuzhiyun int offset;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /* make the last descriptor end the chain */
260*4882a593Smuzhiyun page = &card->mm_pages[card->Active];
261*4882a593Smuzhiyun pr_debug("start_io: %d %d->%d\n",
262*4882a593Smuzhiyun card->Active, page->headcnt, page->cnt - 1);
263*4882a593Smuzhiyun desc = &page->desc[page->cnt-1];
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN);
266*4882a593Smuzhiyun desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN);
267*4882a593Smuzhiyun desc->sem_control_bits = desc->control_bits;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun if (debug & DEBUG_LED_ON_TRANSFER)
271*4882a593Smuzhiyun set_led(card, LED_REMOVE, LED_ON);
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun desc = &page->desc[page->headcnt];
274*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_PCI_ADDR);
275*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_PCI_ADDR + 4);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_LOCAL_ADDR);
278*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_TRANSFER_SIZE);
281*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR);
284*4882a593Smuzhiyun writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun offset = ((char *)desc) - ((char *)page->desc);
287*4882a593Smuzhiyun writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff),
288*4882a593Smuzhiyun card->csr_remap + DMA_DESCRIPTOR_ADDR);
289*4882a593Smuzhiyun /* Force the value to u64 before shifting otherwise >> 32 is undefined C
290*4882a593Smuzhiyun * and on some ports will do nothing ! */
291*4882a593Smuzhiyun writel(cpu_to_le32(((u64)page->page_dma)>>32),
292*4882a593Smuzhiyun card->csr_remap + DMA_DESCRIPTOR_ADDR + 4);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* Go, go, go */
295*4882a593Smuzhiyun writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds),
296*4882a593Smuzhiyun card->csr_remap + DMA_STATUS_CTRL);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun static int add_bio(struct cardinfo *card);
300*4882a593Smuzhiyun
activate(struct cardinfo * card)301*4882a593Smuzhiyun static void activate(struct cardinfo *card)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun /* if No page is Active, and Ready is
304*4882a593Smuzhiyun * not empty, then switch Ready page
305*4882a593Smuzhiyun * to active and start IO.
306*4882a593Smuzhiyun * Then add any bh's that are available to Ready
307*4882a593Smuzhiyun */
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun do {
310*4882a593Smuzhiyun while (add_bio(card))
311*4882a593Smuzhiyun ;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (card->Active == -1 &&
314*4882a593Smuzhiyun card->mm_pages[card->Ready].cnt > 0) {
315*4882a593Smuzhiyun card->Active = card->Ready;
316*4882a593Smuzhiyun card->Ready = 1-card->Ready;
317*4882a593Smuzhiyun mm_start_io(card);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun } while (card->Active == -1 && add_bio(card));
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
reset_page(struct mm_page * page)323*4882a593Smuzhiyun static inline void reset_page(struct mm_page *page)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun page->cnt = 0;
326*4882a593Smuzhiyun page->headcnt = 0;
327*4882a593Smuzhiyun page->bio = NULL;
328*4882a593Smuzhiyun page->biotail = &page->bio;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /*
332*4882a593Smuzhiyun * If there is room on Ready page, take
333*4882a593Smuzhiyun * one bh off list and add it.
334*4882a593Smuzhiyun * return 1 if there was room, else 0.
335*4882a593Smuzhiyun */
add_bio(struct cardinfo * card)336*4882a593Smuzhiyun static int add_bio(struct cardinfo *card)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun struct mm_page *p;
339*4882a593Smuzhiyun struct mm_dma_desc *desc;
340*4882a593Smuzhiyun dma_addr_t dma_handle;
341*4882a593Smuzhiyun int offset;
342*4882a593Smuzhiyun struct bio *bio;
343*4882a593Smuzhiyun struct bio_vec vec;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun bio = card->currentbio;
346*4882a593Smuzhiyun if (!bio && card->bio) {
347*4882a593Smuzhiyun card->currentbio = card->bio;
348*4882a593Smuzhiyun card->current_iter = card->bio->bi_iter;
349*4882a593Smuzhiyun card->bio = card->bio->bi_next;
350*4882a593Smuzhiyun if (card->bio == NULL)
351*4882a593Smuzhiyun card->biotail = &card->bio;
352*4882a593Smuzhiyun card->currentbio->bi_next = NULL;
353*4882a593Smuzhiyun return 1;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun if (!bio)
356*4882a593Smuzhiyun return 0;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE)
359*4882a593Smuzhiyun return 0;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun vec = bio_iter_iovec(bio, card->current_iter);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun dma_handle = dma_map_page(&card->dev->dev,
364*4882a593Smuzhiyun vec.bv_page,
365*4882a593Smuzhiyun vec.bv_offset,
366*4882a593Smuzhiyun vec.bv_len,
367*4882a593Smuzhiyun bio_op(bio) == REQ_OP_READ ?
368*4882a593Smuzhiyun DMA_FROM_DEVICE : DMA_TO_DEVICE);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun p = &card->mm_pages[card->Ready];
371*4882a593Smuzhiyun desc = &p->desc[p->cnt];
372*4882a593Smuzhiyun p->cnt++;
373*4882a593Smuzhiyun if (p->bio == NULL)
374*4882a593Smuzhiyun p->iter = card->current_iter;
375*4882a593Smuzhiyun if ((p->biotail) != &bio->bi_next) {
376*4882a593Smuzhiyun *(p->biotail) = bio;
377*4882a593Smuzhiyun p->biotail = &(bio->bi_next);
378*4882a593Smuzhiyun bio->bi_next = NULL;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun desc->data_dma_handle = dma_handle;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle);
384*4882a593Smuzhiyun desc->local_addr = cpu_to_le64(card->current_iter.bi_sector << 9);
385*4882a593Smuzhiyun desc->transfer_size = cpu_to_le32(vec.bv_len);
386*4882a593Smuzhiyun offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc));
387*4882a593Smuzhiyun desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset));
388*4882a593Smuzhiyun desc->zero1 = desc->zero2 = 0;
389*4882a593Smuzhiyun offset = (((char *)(desc+1)) - ((char *)p->desc));
390*4882a593Smuzhiyun desc->next_desc_addr = cpu_to_le64(p->page_dma+offset);
391*4882a593Smuzhiyun desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN|
392*4882a593Smuzhiyun DMASCR_PARITY_INT_EN|
393*4882a593Smuzhiyun DMASCR_CHAIN_EN |
394*4882a593Smuzhiyun DMASCR_SEM_EN |
395*4882a593Smuzhiyun pci_cmds);
396*4882a593Smuzhiyun if (bio_op(bio) == REQ_OP_WRITE)
397*4882a593Smuzhiyun desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ);
398*4882a593Smuzhiyun desc->sem_control_bits = desc->control_bits;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun bio_advance_iter(bio, &card->current_iter, vec.bv_len);
402*4882a593Smuzhiyun if (!card->current_iter.bi_size)
403*4882a593Smuzhiyun card->currentbio = NULL;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun return 1;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
process_page(unsigned long data)408*4882a593Smuzhiyun static void process_page(unsigned long data)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun /* check if any of the requests in the page are DMA_COMPLETE,
411*4882a593Smuzhiyun * and deal with them appropriately.
412*4882a593Smuzhiyun * If we find a descriptor without DMA_COMPLETE in the semaphore, then
413*4882a593Smuzhiyun * dma must have hit an error on that descriptor, so use dma_status
414*4882a593Smuzhiyun * instead and assume that all following descriptors must be re-tried.
415*4882a593Smuzhiyun */
416*4882a593Smuzhiyun struct mm_page *page;
417*4882a593Smuzhiyun struct bio *return_bio = NULL;
418*4882a593Smuzhiyun struct cardinfo *card = (struct cardinfo *)data;
419*4882a593Smuzhiyun unsigned int dma_status = card->dma_status;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun spin_lock(&card->lock);
422*4882a593Smuzhiyun if (card->Active < 0)
423*4882a593Smuzhiyun goto out_unlock;
424*4882a593Smuzhiyun page = &card->mm_pages[card->Active];
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun while (page->headcnt < page->cnt) {
427*4882a593Smuzhiyun struct bio *bio = page->bio;
428*4882a593Smuzhiyun struct mm_dma_desc *desc = &page->desc[page->headcnt];
429*4882a593Smuzhiyun int control = le32_to_cpu(desc->sem_control_bits);
430*4882a593Smuzhiyun int last = 0;
431*4882a593Smuzhiyun struct bio_vec vec;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (!(control & DMASCR_DMA_COMPLETE)) {
434*4882a593Smuzhiyun control = dma_status;
435*4882a593Smuzhiyun last = 1;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun page->headcnt++;
439*4882a593Smuzhiyun vec = bio_iter_iovec(bio, page->iter);
440*4882a593Smuzhiyun bio_advance_iter(bio, &page->iter, vec.bv_len);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun if (!page->iter.bi_size) {
443*4882a593Smuzhiyun page->bio = bio->bi_next;
444*4882a593Smuzhiyun if (page->bio)
445*4882a593Smuzhiyun page->iter = page->bio->bi_iter;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun dma_unmap_page(&card->dev->dev, desc->data_dma_handle,
449*4882a593Smuzhiyun vec.bv_len,
450*4882a593Smuzhiyun (control & DMASCR_TRANSFER_READ) ?
451*4882a593Smuzhiyun DMA_TO_DEVICE : DMA_FROM_DEVICE);
452*4882a593Smuzhiyun if (control & DMASCR_HARD_ERROR) {
453*4882a593Smuzhiyun /* error */
454*4882a593Smuzhiyun bio->bi_status = BLK_STS_IOERR;
455*4882a593Smuzhiyun dev_printk(KERN_WARNING, &card->dev->dev,
456*4882a593Smuzhiyun "I/O error on sector %d/%d\n",
457*4882a593Smuzhiyun le32_to_cpu(desc->local_addr)>>9,
458*4882a593Smuzhiyun le32_to_cpu(desc->transfer_size));
459*4882a593Smuzhiyun dump_dmastat(card, control);
460*4882a593Smuzhiyun } else if (op_is_write(bio_op(bio)) &&
461*4882a593Smuzhiyun le32_to_cpu(desc->local_addr) >> 9 ==
462*4882a593Smuzhiyun card->init_size) {
463*4882a593Smuzhiyun card->init_size += le32_to_cpu(desc->transfer_size) >> 9;
464*4882a593Smuzhiyun if (card->init_size >> 1 >= card->mm_size) {
465*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
466*4882a593Smuzhiyun "memory now initialised\n");
467*4882a593Smuzhiyun set_userbit(card, MEMORY_INITIALIZED, 1);
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun if (bio != page->bio) {
471*4882a593Smuzhiyun bio->bi_next = return_bio;
472*4882a593Smuzhiyun return_bio = bio;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun if (last)
476*4882a593Smuzhiyun break;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun if (debug & DEBUG_LED_ON_TRANSFER)
480*4882a593Smuzhiyun set_led(card, LED_REMOVE, LED_OFF);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (card->check_batteries) {
483*4882a593Smuzhiyun card->check_batteries = 0;
484*4882a593Smuzhiyun check_batteries(card);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun if (page->headcnt >= page->cnt) {
487*4882a593Smuzhiyun reset_page(page);
488*4882a593Smuzhiyun card->Active = -1;
489*4882a593Smuzhiyun activate(card);
490*4882a593Smuzhiyun } else {
491*4882a593Smuzhiyun /* haven't finished with this one yet */
492*4882a593Smuzhiyun pr_debug("do some more\n");
493*4882a593Smuzhiyun mm_start_io(card);
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun out_unlock:
496*4882a593Smuzhiyun spin_unlock(&card->lock);
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun while (return_bio) {
499*4882a593Smuzhiyun struct bio *bio = return_bio;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun return_bio = bio->bi_next;
502*4882a593Smuzhiyun bio->bi_next = NULL;
503*4882a593Smuzhiyun bio_endio(bio);
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
mm_unplug(struct blk_plug_cb * cb,bool from_schedule)507*4882a593Smuzhiyun static void mm_unplug(struct blk_plug_cb *cb, bool from_schedule)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun struct cardinfo *card = cb->data;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun spin_lock_irq(&card->lock);
512*4882a593Smuzhiyun activate(card);
513*4882a593Smuzhiyun spin_unlock_irq(&card->lock);
514*4882a593Smuzhiyun kfree(cb);
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
mm_check_plugged(struct cardinfo * card)517*4882a593Smuzhiyun static int mm_check_plugged(struct cardinfo *card)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun return !!blk_check_plugged(mm_unplug, card, sizeof(struct blk_plug_cb));
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
mm_submit_bio(struct bio * bio)522*4882a593Smuzhiyun static blk_qc_t mm_submit_bio(struct bio *bio)
523*4882a593Smuzhiyun {
524*4882a593Smuzhiyun struct cardinfo *card = bio->bi_disk->private_data;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun pr_debug("mm_make_request %llu %u\n",
527*4882a593Smuzhiyun (unsigned long long)bio->bi_iter.bi_sector,
528*4882a593Smuzhiyun bio->bi_iter.bi_size);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun blk_queue_split(&bio);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun spin_lock_irq(&card->lock);
533*4882a593Smuzhiyun *card->biotail = bio;
534*4882a593Smuzhiyun bio->bi_next = NULL;
535*4882a593Smuzhiyun card->biotail = &bio->bi_next;
536*4882a593Smuzhiyun if (op_is_sync(bio->bi_opf) || !mm_check_plugged(card))
537*4882a593Smuzhiyun activate(card);
538*4882a593Smuzhiyun spin_unlock_irq(&card->lock);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun return BLK_QC_T_NONE;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
mm_interrupt(int irq,void * __card)543*4882a593Smuzhiyun static irqreturn_t mm_interrupt(int irq, void *__card)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun struct cardinfo *card = (struct cardinfo *) __card;
546*4882a593Smuzhiyun unsigned int dma_status;
547*4882a593Smuzhiyun unsigned short cfg_status;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun HW_TRACE(0x30);
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL));
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) {
554*4882a593Smuzhiyun /* interrupt wasn't for me ... */
555*4882a593Smuzhiyun return IRQ_NONE;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun /* clear COMPLETION interrupts */
559*4882a593Smuzhiyun if (card->flags & UM_FLAG_NO_BYTE_STATUS)
560*4882a593Smuzhiyun writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE),
561*4882a593Smuzhiyun card->csr_remap + DMA_STATUS_CTRL);
562*4882a593Smuzhiyun else
563*4882a593Smuzhiyun writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16,
564*4882a593Smuzhiyun card->csr_remap + DMA_STATUS_CTRL + 2);
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* log errors and clear interrupt status */
567*4882a593Smuzhiyun if (dma_status & DMASCR_ANY_ERR) {
568*4882a593Smuzhiyun unsigned int data_log1, data_log2;
569*4882a593Smuzhiyun unsigned int addr_log1, addr_log2;
570*4882a593Smuzhiyun unsigned char stat, count, syndrome, check;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun data_log1 = le32_to_cpu(readl(card->csr_remap +
575*4882a593Smuzhiyun ERROR_DATA_LOG));
576*4882a593Smuzhiyun data_log2 = le32_to_cpu(readl(card->csr_remap +
577*4882a593Smuzhiyun ERROR_DATA_LOG + 4));
578*4882a593Smuzhiyun addr_log1 = le32_to_cpu(readl(card->csr_remap +
579*4882a593Smuzhiyun ERROR_ADDR_LOG));
580*4882a593Smuzhiyun addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4);
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun count = readb(card->csr_remap + ERROR_COUNT);
583*4882a593Smuzhiyun syndrome = readb(card->csr_remap + ERROR_SYNDROME);
584*4882a593Smuzhiyun check = readb(card->csr_remap + ERROR_CHECK);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun dump_dmastat(card, dma_status);
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun if (stat & 0x01)
589*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
590*4882a593Smuzhiyun "Memory access error detected (err count %d)\n",
591*4882a593Smuzhiyun count);
592*4882a593Smuzhiyun if (stat & 0x02)
593*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
594*4882a593Smuzhiyun "Multi-bit EDC error\n");
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
597*4882a593Smuzhiyun "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n",
598*4882a593Smuzhiyun addr_log2, addr_log1, data_log2, data_log1);
599*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
600*4882a593Smuzhiyun "Fault Check 0x%02x, Fault Syndrome 0x%02x\n",
601*4882a593Smuzhiyun check, syndrome);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun writeb(0, card->csr_remap + ERROR_COUNT);
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun if (dma_status & DMASCR_PARITY_ERR_REP) {
607*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
608*4882a593Smuzhiyun "PARITY ERROR REPORTED\n");
609*4882a593Smuzhiyun pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
610*4882a593Smuzhiyun pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun if (dma_status & DMASCR_PARITY_ERR_DET) {
614*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
615*4882a593Smuzhiyun "PARITY ERROR DETECTED\n");
616*4882a593Smuzhiyun pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
617*4882a593Smuzhiyun pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (dma_status & DMASCR_SYSTEM_ERR_SIG) {
621*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n");
622*4882a593Smuzhiyun pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
623*4882a593Smuzhiyun pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun if (dma_status & DMASCR_TARGET_ABT) {
627*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n");
628*4882a593Smuzhiyun pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
629*4882a593Smuzhiyun pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun if (dma_status & DMASCR_MASTER_ABT) {
633*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n");
634*4882a593Smuzhiyun pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
635*4882a593Smuzhiyun pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /* and process the DMA descriptors */
639*4882a593Smuzhiyun card->dma_status = dma_status;
640*4882a593Smuzhiyun tasklet_schedule(&card->tasklet);
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun HW_TRACE(0x36);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun return IRQ_HANDLED;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /*
648*4882a593Smuzhiyun * If both batteries are good, no LED
649*4882a593Smuzhiyun * If either battery has been warned, solid LED
650*4882a593Smuzhiyun * If both batteries are bad, flash the LED quickly
651*4882a593Smuzhiyun * If either battery is bad, flash the LED semi quickly
652*4882a593Smuzhiyun */
set_fault_to_battery_status(struct cardinfo * card)653*4882a593Smuzhiyun static void set_fault_to_battery_status(struct cardinfo *card)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun if (card->battery[0].good && card->battery[1].good)
656*4882a593Smuzhiyun set_led(card, LED_FAULT, LED_OFF);
657*4882a593Smuzhiyun else if (card->battery[0].warned || card->battery[1].warned)
658*4882a593Smuzhiyun set_led(card, LED_FAULT, LED_ON);
659*4882a593Smuzhiyun else if (!card->battery[0].good && !card->battery[1].good)
660*4882a593Smuzhiyun set_led(card, LED_FAULT, LED_FLASH_7_0);
661*4882a593Smuzhiyun else
662*4882a593Smuzhiyun set_led(card, LED_FAULT, LED_FLASH_3_5);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun static void init_battery_timer(void);
666*4882a593Smuzhiyun
check_battery(struct cardinfo * card,int battery,int status)667*4882a593Smuzhiyun static int check_battery(struct cardinfo *card, int battery, int status)
668*4882a593Smuzhiyun {
669*4882a593Smuzhiyun if (status != card->battery[battery].good) {
670*4882a593Smuzhiyun card->battery[battery].good = !card->battery[battery].good;
671*4882a593Smuzhiyun card->battery[battery].last_change = jiffies;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun if (card->battery[battery].good) {
674*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
675*4882a593Smuzhiyun "Battery %d now good\n", battery + 1);
676*4882a593Smuzhiyun card->battery[battery].warned = 0;
677*4882a593Smuzhiyun } else
678*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
679*4882a593Smuzhiyun "Battery %d now FAILED\n", battery + 1);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun return 1;
682*4882a593Smuzhiyun } else if (!card->battery[battery].good &&
683*4882a593Smuzhiyun !card->battery[battery].warned &&
684*4882a593Smuzhiyun time_after_eq(jiffies, card->battery[battery].last_change +
685*4882a593Smuzhiyun (HZ * 60 * 60 * 5))) {
686*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
687*4882a593Smuzhiyun "Battery %d still FAILED after 5 hours\n", battery + 1);
688*4882a593Smuzhiyun card->battery[battery].warned = 1;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun return 1;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun return 0;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
check_batteries(struct cardinfo * card)696*4882a593Smuzhiyun static void check_batteries(struct cardinfo *card)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun /* NOTE: this must *never* be called while the card
699*4882a593Smuzhiyun * is doing (bus-to-card) DMA, or you will need the
700*4882a593Smuzhiyun * reset switch
701*4882a593Smuzhiyun */
702*4882a593Smuzhiyun unsigned char status;
703*4882a593Smuzhiyun int ret1, ret2;
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY);
706*4882a593Smuzhiyun if (debug & DEBUG_BATTERY_POLLING)
707*4882a593Smuzhiyun dev_printk(KERN_DEBUG, &card->dev->dev,
708*4882a593Smuzhiyun "checking battery status, 1 = %s, 2 = %s\n",
709*4882a593Smuzhiyun (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK",
710*4882a593Smuzhiyun (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK");
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE));
713*4882a593Smuzhiyun ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE));
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun if (ret1 || ret2)
716*4882a593Smuzhiyun set_fault_to_battery_status(card);
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun
check_all_batteries(struct timer_list * unused)719*4882a593Smuzhiyun static void check_all_batteries(struct timer_list *unused)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun int i;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun for (i = 0; i < num_cards; i++)
724*4882a593Smuzhiyun if (!(cards[i].flags & UM_FLAG_NO_BATT)) {
725*4882a593Smuzhiyun struct cardinfo *card = &cards[i];
726*4882a593Smuzhiyun spin_lock_bh(&card->lock);
727*4882a593Smuzhiyun if (card->Active >= 0)
728*4882a593Smuzhiyun card->check_batteries = 1;
729*4882a593Smuzhiyun else
730*4882a593Smuzhiyun check_batteries(card);
731*4882a593Smuzhiyun spin_unlock_bh(&card->lock);
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun init_battery_timer();
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun
init_battery_timer(void)737*4882a593Smuzhiyun static void init_battery_timer(void)
738*4882a593Smuzhiyun {
739*4882a593Smuzhiyun timer_setup(&battery_timer, check_all_batteries, 0);
740*4882a593Smuzhiyun battery_timer.expires = jiffies + (HZ * 60);
741*4882a593Smuzhiyun add_timer(&battery_timer);
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
del_battery_timer(void)744*4882a593Smuzhiyun static void del_battery_timer(void)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun del_timer(&battery_timer);
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun /*
750*4882a593Smuzhiyun * Note no locks taken out here. In a worst case scenario, we could drop
751*4882a593Smuzhiyun * a chunk of system memory. But that should never happen, since validation
752*4882a593Smuzhiyun * happens at open or mount time, when locks are held.
753*4882a593Smuzhiyun *
754*4882a593Smuzhiyun * That's crap, since doing that while some partitions are opened
755*4882a593Smuzhiyun * or mounted will give you really nasty results.
756*4882a593Smuzhiyun */
mm_revalidate(struct gendisk * disk)757*4882a593Smuzhiyun static int mm_revalidate(struct gendisk *disk)
758*4882a593Smuzhiyun {
759*4882a593Smuzhiyun struct cardinfo *card = disk->private_data;
760*4882a593Smuzhiyun set_capacity(disk, card->mm_size << 1);
761*4882a593Smuzhiyun return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
mm_getgeo(struct block_device * bdev,struct hd_geometry * geo)764*4882a593Smuzhiyun static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun struct cardinfo *card = bdev->bd_disk->private_data;
767*4882a593Smuzhiyun int size = card->mm_size * (1024 / MM_HARDSECT);
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun /*
770*4882a593Smuzhiyun * get geometry: we have to fake one... trim the size to a
771*4882a593Smuzhiyun * multiple of 2048 (1M): tell we have 32 sectors, 64 heads,
772*4882a593Smuzhiyun * whatever cylinders.
773*4882a593Smuzhiyun */
774*4882a593Smuzhiyun geo->heads = 64;
775*4882a593Smuzhiyun geo->sectors = 32;
776*4882a593Smuzhiyun geo->cylinders = size / (geo->heads * geo->sectors);
777*4882a593Smuzhiyun return 0;
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun static const struct block_device_operations mm_fops = {
781*4882a593Smuzhiyun .owner = THIS_MODULE,
782*4882a593Smuzhiyun .submit_bio = mm_submit_bio,
783*4882a593Smuzhiyun .getgeo = mm_getgeo,
784*4882a593Smuzhiyun .revalidate_disk = mm_revalidate,
785*4882a593Smuzhiyun };
786*4882a593Smuzhiyun
mm_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)787*4882a593Smuzhiyun static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
788*4882a593Smuzhiyun {
789*4882a593Smuzhiyun int ret;
790*4882a593Smuzhiyun struct cardinfo *card = &cards[num_cards];
791*4882a593Smuzhiyun unsigned char mem_present;
792*4882a593Smuzhiyun unsigned char batt_status;
793*4882a593Smuzhiyun unsigned int saved_bar, data;
794*4882a593Smuzhiyun unsigned long csr_base;
795*4882a593Smuzhiyun unsigned long csr_len;
796*4882a593Smuzhiyun int magic_number;
797*4882a593Smuzhiyun static int printed_version;
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun if (!printed_version++)
800*4882a593Smuzhiyun printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n");
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun ret = pci_enable_device(dev);
803*4882a593Smuzhiyun if (ret)
804*4882a593Smuzhiyun return ret;
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8);
807*4882a593Smuzhiyun pci_set_master(dev);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun card->dev = dev;
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun csr_base = pci_resource_start(dev, 0);
812*4882a593Smuzhiyun csr_len = pci_resource_len(dev, 0);
813*4882a593Smuzhiyun if (!csr_base || !csr_len)
814*4882a593Smuzhiyun return -ENODEV;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun dev_printk(KERN_INFO, &dev->dev,
817*4882a593Smuzhiyun "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n");
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun if (dma_set_mask(&dev->dev, DMA_BIT_MASK(64)) &&
820*4882a593Smuzhiyun dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) {
821*4882a593Smuzhiyun dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n");
822*4882a593Smuzhiyun return -ENOMEM;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun ret = pci_request_regions(dev, DRIVER_NAME);
826*4882a593Smuzhiyun if (ret) {
827*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
828*4882a593Smuzhiyun "Unable to request memory region\n");
829*4882a593Smuzhiyun goto failed_req_csr;
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun card->csr_remap = ioremap(csr_base, csr_len);
833*4882a593Smuzhiyun if (!card->csr_remap) {
834*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
835*4882a593Smuzhiyun "Unable to remap memory region\n");
836*4882a593Smuzhiyun ret = -ENOMEM;
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun goto failed_remap_csr;
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
842*4882a593Smuzhiyun "CSR 0x%08lx -> 0x%p (0x%lx)\n",
843*4882a593Smuzhiyun csr_base, card->csr_remap, csr_len);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun switch (card->dev->device) {
846*4882a593Smuzhiyun case 0x5415:
847*4882a593Smuzhiyun card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG;
848*4882a593Smuzhiyun magic_number = 0x59;
849*4882a593Smuzhiyun break;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun case 0x5425:
852*4882a593Smuzhiyun card->flags |= UM_FLAG_NO_BYTE_STATUS;
853*4882a593Smuzhiyun magic_number = 0x5C;
854*4882a593Smuzhiyun break;
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun case 0x6155:
857*4882a593Smuzhiyun card->flags |= UM_FLAG_NO_BYTE_STATUS |
858*4882a593Smuzhiyun UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT;
859*4882a593Smuzhiyun magic_number = 0x99;
860*4882a593Smuzhiyun break;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun default:
863*4882a593Smuzhiyun magic_number = 0x100;
864*4882a593Smuzhiyun break;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) {
868*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n");
869*4882a593Smuzhiyun ret = -ENOMEM;
870*4882a593Smuzhiyun goto failed_magic;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun card->mm_pages[0].desc = dma_alloc_coherent(&card->dev->dev,
874*4882a593Smuzhiyun PAGE_SIZE * 2, &card->mm_pages[0].page_dma, GFP_KERNEL);
875*4882a593Smuzhiyun card->mm_pages[1].desc = dma_alloc_coherent(&card->dev->dev,
876*4882a593Smuzhiyun PAGE_SIZE * 2, &card->mm_pages[1].page_dma, GFP_KERNEL);
877*4882a593Smuzhiyun if (card->mm_pages[0].desc == NULL ||
878*4882a593Smuzhiyun card->mm_pages[1].desc == NULL) {
879*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n");
880*4882a593Smuzhiyun ret = -ENOMEM;
881*4882a593Smuzhiyun goto failed_alloc;
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun reset_page(&card->mm_pages[0]);
884*4882a593Smuzhiyun reset_page(&card->mm_pages[1]);
885*4882a593Smuzhiyun card->Ready = 0; /* page 0 is ready */
886*4882a593Smuzhiyun card->Active = -1; /* no page is active */
887*4882a593Smuzhiyun card->bio = NULL;
888*4882a593Smuzhiyun card->biotail = &card->bio;
889*4882a593Smuzhiyun spin_lock_init(&card->lock);
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun card->queue = blk_alloc_queue(NUMA_NO_NODE);
892*4882a593Smuzhiyun if (!card->queue) {
893*4882a593Smuzhiyun ret = -ENOMEM;
894*4882a593Smuzhiyun goto failed_alloc;
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun tasklet_init(&card->tasklet, process_page, (unsigned long)card);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun card->check_batteries = 0;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY);
902*4882a593Smuzhiyun switch (mem_present) {
903*4882a593Smuzhiyun case MEM_128_MB:
904*4882a593Smuzhiyun card->mm_size = 1024 * 128;
905*4882a593Smuzhiyun break;
906*4882a593Smuzhiyun case MEM_256_MB:
907*4882a593Smuzhiyun card->mm_size = 1024 * 256;
908*4882a593Smuzhiyun break;
909*4882a593Smuzhiyun case MEM_512_MB:
910*4882a593Smuzhiyun card->mm_size = 1024 * 512;
911*4882a593Smuzhiyun break;
912*4882a593Smuzhiyun case MEM_1_GB:
913*4882a593Smuzhiyun card->mm_size = 1024 * 1024;
914*4882a593Smuzhiyun break;
915*4882a593Smuzhiyun case MEM_2_GB:
916*4882a593Smuzhiyun card->mm_size = 1024 * 2048;
917*4882a593Smuzhiyun break;
918*4882a593Smuzhiyun default:
919*4882a593Smuzhiyun card->mm_size = 0;
920*4882a593Smuzhiyun break;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun /* Clear the LED's we control */
924*4882a593Smuzhiyun set_led(card, LED_REMOVE, LED_OFF);
925*4882a593Smuzhiyun set_led(card, LED_FAULT, LED_OFF);
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun card->battery[0].good = !(batt_status & BATTERY_1_FAILURE);
930*4882a593Smuzhiyun card->battery[1].good = !(batt_status & BATTERY_2_FAILURE);
931*4882a593Smuzhiyun card->battery[0].last_change = card->battery[1].last_change = jiffies;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun if (card->flags & UM_FLAG_NO_BATT)
934*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
935*4882a593Smuzhiyun "Size %d KB\n", card->mm_size);
936*4882a593Smuzhiyun else {
937*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
938*4882a593Smuzhiyun "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n",
939*4882a593Smuzhiyun card->mm_size,
940*4882a593Smuzhiyun batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled",
941*4882a593Smuzhiyun card->battery[0].good ? "OK" : "FAILURE",
942*4882a593Smuzhiyun batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled",
943*4882a593Smuzhiyun card->battery[1].good ? "OK" : "FAILURE");
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun set_fault_to_battery_status(card);
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar);
949*4882a593Smuzhiyun data = 0xffffffff;
950*4882a593Smuzhiyun pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data);
951*4882a593Smuzhiyun pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data);
952*4882a593Smuzhiyun pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar);
953*4882a593Smuzhiyun data &= 0xfffffff0;
954*4882a593Smuzhiyun data = ~data;
955*4882a593Smuzhiyun data += 1;
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME,
958*4882a593Smuzhiyun card)) {
959*4882a593Smuzhiyun dev_printk(KERN_ERR, &card->dev->dev,
960*4882a593Smuzhiyun "Unable to allocate IRQ\n");
961*4882a593Smuzhiyun ret = -ENODEV;
962*4882a593Smuzhiyun goto failed_req_irq;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
966*4882a593Smuzhiyun "Window size %d bytes, IRQ %d\n", data, dev->irq);
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun pci_set_drvdata(dev, card);
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */
971*4882a593Smuzhiyun pci_write_cmd = 0x07; /* then Memory Write command */
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */
974*4882a593Smuzhiyun unsigned short cfg_command;
975*4882a593Smuzhiyun pci_read_config_word(dev, PCI_COMMAND, &cfg_command);
976*4882a593Smuzhiyun cfg_command |= 0x10; /* Memory Write & Invalidate Enable */
977*4882a593Smuzhiyun pci_write_config_word(dev, PCI_COMMAND, cfg_command);
978*4882a593Smuzhiyun }
979*4882a593Smuzhiyun pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun num_cards++;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (!get_userbit(card, MEMORY_INITIALIZED)) {
984*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
985*4882a593Smuzhiyun "memory NOT initialized. Consider over-writing whole device.\n");
986*4882a593Smuzhiyun card->init_size = 0;
987*4882a593Smuzhiyun } else {
988*4882a593Smuzhiyun dev_printk(KERN_INFO, &card->dev->dev,
989*4882a593Smuzhiyun "memory already initialized\n");
990*4882a593Smuzhiyun card->init_size = card->mm_size;
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun /* Enable ECC */
994*4882a593Smuzhiyun writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL);
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun return 0;
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun failed_req_irq:
999*4882a593Smuzhiyun failed_alloc:
1000*4882a593Smuzhiyun if (card->mm_pages[0].desc)
1001*4882a593Smuzhiyun dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2,
1002*4882a593Smuzhiyun card->mm_pages[0].desc,
1003*4882a593Smuzhiyun card->mm_pages[0].page_dma);
1004*4882a593Smuzhiyun if (card->mm_pages[1].desc)
1005*4882a593Smuzhiyun dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2,
1006*4882a593Smuzhiyun card->mm_pages[1].desc,
1007*4882a593Smuzhiyun card->mm_pages[1].page_dma);
1008*4882a593Smuzhiyun failed_magic:
1009*4882a593Smuzhiyun iounmap(card->csr_remap);
1010*4882a593Smuzhiyun failed_remap_csr:
1011*4882a593Smuzhiyun pci_release_regions(dev);
1012*4882a593Smuzhiyun failed_req_csr:
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun return ret;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun
mm_pci_remove(struct pci_dev * dev)1017*4882a593Smuzhiyun static void mm_pci_remove(struct pci_dev *dev)
1018*4882a593Smuzhiyun {
1019*4882a593Smuzhiyun struct cardinfo *card = pci_get_drvdata(dev);
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun tasklet_kill(&card->tasklet);
1022*4882a593Smuzhiyun free_irq(dev->irq, card);
1023*4882a593Smuzhiyun iounmap(card->csr_remap);
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun if (card->mm_pages[0].desc)
1026*4882a593Smuzhiyun dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2,
1027*4882a593Smuzhiyun card->mm_pages[0].desc,
1028*4882a593Smuzhiyun card->mm_pages[0].page_dma);
1029*4882a593Smuzhiyun if (card->mm_pages[1].desc)
1030*4882a593Smuzhiyun dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2,
1031*4882a593Smuzhiyun card->mm_pages[1].desc,
1032*4882a593Smuzhiyun card->mm_pages[1].page_dma);
1033*4882a593Smuzhiyun blk_cleanup_queue(card->queue);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun pci_release_regions(dev);
1036*4882a593Smuzhiyun pci_disable_device(dev);
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun static const struct pci_device_id mm_pci_ids[] = {
1040*4882a593Smuzhiyun {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)},
1041*4882a593Smuzhiyun {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)},
1042*4882a593Smuzhiyun {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)},
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun .vendor = 0x8086,
1045*4882a593Smuzhiyun .device = 0xB555,
1046*4882a593Smuzhiyun .subvendor = 0x1332,
1047*4882a593Smuzhiyun .subdevice = 0x5460,
1048*4882a593Smuzhiyun .class = 0x050000,
1049*4882a593Smuzhiyun .class_mask = 0,
1050*4882a593Smuzhiyun }, { /* end: all zeroes */ }
1051*4882a593Smuzhiyun };
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mm_pci_ids);
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun static struct pci_driver mm_pci_driver = {
1056*4882a593Smuzhiyun .name = DRIVER_NAME,
1057*4882a593Smuzhiyun .id_table = mm_pci_ids,
1058*4882a593Smuzhiyun .probe = mm_pci_probe,
1059*4882a593Smuzhiyun .remove = mm_pci_remove,
1060*4882a593Smuzhiyun };
1061*4882a593Smuzhiyun
mm_init(void)1062*4882a593Smuzhiyun static int __init mm_init(void)
1063*4882a593Smuzhiyun {
1064*4882a593Smuzhiyun int retval, i;
1065*4882a593Smuzhiyun int err;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun retval = pci_register_driver(&mm_pci_driver);
1068*4882a593Smuzhiyun if (retval)
1069*4882a593Smuzhiyun return -ENOMEM;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun err = major_nr = register_blkdev(0, DRIVER_NAME);
1072*4882a593Smuzhiyun if (err < 0) {
1073*4882a593Smuzhiyun pci_unregister_driver(&mm_pci_driver);
1074*4882a593Smuzhiyun return -EIO;
1075*4882a593Smuzhiyun }
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun for (i = 0; i < num_cards; i++) {
1078*4882a593Smuzhiyun mm_gendisk[i] = alloc_disk(1 << MM_SHIFT);
1079*4882a593Smuzhiyun if (!mm_gendisk[i])
1080*4882a593Smuzhiyun goto out;
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun for (i = 0; i < num_cards; i++) {
1084*4882a593Smuzhiyun struct gendisk *disk = mm_gendisk[i];
1085*4882a593Smuzhiyun sprintf(disk->disk_name, "umem%c", 'a'+i);
1086*4882a593Smuzhiyun spin_lock_init(&cards[i].lock);
1087*4882a593Smuzhiyun disk->major = major_nr;
1088*4882a593Smuzhiyun disk->first_minor = i << MM_SHIFT;
1089*4882a593Smuzhiyun disk->fops = &mm_fops;
1090*4882a593Smuzhiyun disk->private_data = &cards[i];
1091*4882a593Smuzhiyun disk->queue = cards[i].queue;
1092*4882a593Smuzhiyun set_capacity(disk, cards[i].mm_size << 1);
1093*4882a593Smuzhiyun add_disk(disk);
1094*4882a593Smuzhiyun }
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun init_battery_timer();
1097*4882a593Smuzhiyun printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE);
1098*4882a593Smuzhiyun /* printk("mm_init: Done. 10-19-01 9:00\n"); */
1099*4882a593Smuzhiyun return 0;
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun out:
1102*4882a593Smuzhiyun pci_unregister_driver(&mm_pci_driver);
1103*4882a593Smuzhiyun unregister_blkdev(major_nr, DRIVER_NAME);
1104*4882a593Smuzhiyun while (i--)
1105*4882a593Smuzhiyun put_disk(mm_gendisk[i]);
1106*4882a593Smuzhiyun return -ENOMEM;
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun
mm_cleanup(void)1109*4882a593Smuzhiyun static void __exit mm_cleanup(void)
1110*4882a593Smuzhiyun {
1111*4882a593Smuzhiyun int i;
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun del_battery_timer();
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun for (i = 0; i < num_cards ; i++) {
1116*4882a593Smuzhiyun del_gendisk(mm_gendisk[i]);
1117*4882a593Smuzhiyun put_disk(mm_gendisk[i]);
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun pci_unregister_driver(&mm_pci_driver);
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun unregister_blkdev(major_nr, DRIVER_NAME);
1123*4882a593Smuzhiyun }
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun module_init(mm_init);
1126*4882a593Smuzhiyun module_exit(mm_cleanup);
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun MODULE_AUTHOR(DRIVER_AUTHOR);
1129*4882a593Smuzhiyun MODULE_DESCRIPTION(DRIVER_DESC);
1130*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1131