xref: /OK3568_Linux_fs/kernel/drivers/block/sx8.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright 2004-2005 Red Hat, Inc.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *  Author/maintainer:  Jeff Garzik <jgarzik@pobox.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *  This file is subject to the terms and conditions of the GNU General Public
9*4882a593Smuzhiyun  *  License.  See the file "COPYING" in the main directory of this archive
10*4882a593Smuzhiyun  *  for more details.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/pci.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/spinlock.h>
19*4882a593Smuzhiyun #include <linux/blk-mq.h>
20*4882a593Smuzhiyun #include <linux/sched.h>
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/compiler.h>
23*4882a593Smuzhiyun #include <linux/workqueue.h>
24*4882a593Smuzhiyun #include <linux/bitops.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun #include <linux/ktime.h>
27*4882a593Smuzhiyun #include <linux/hdreg.h>
28*4882a593Smuzhiyun #include <linux/dma-mapping.h>
29*4882a593Smuzhiyun #include <linux/completion.h>
30*4882a593Smuzhiyun #include <linux/scatterlist.h>
31*4882a593Smuzhiyun #include <asm/io.h>
32*4882a593Smuzhiyun #include <linux/uaccess.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #if 0
35*4882a593Smuzhiyun #define CARM_DEBUG
36*4882a593Smuzhiyun #define CARM_VERBOSE_DEBUG
37*4882a593Smuzhiyun #else
38*4882a593Smuzhiyun #undef CARM_DEBUG
39*4882a593Smuzhiyun #undef CARM_VERBOSE_DEBUG
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun #undef CARM_NDEBUG
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define DRV_NAME "sx8"
44*4882a593Smuzhiyun #define DRV_VERSION "1.0"
45*4882a593Smuzhiyun #define PFX DRV_NAME ": "
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun MODULE_AUTHOR("Jeff Garzik");
48*4882a593Smuzhiyun MODULE_LICENSE("GPL");
49*4882a593Smuzhiyun MODULE_DESCRIPTION("Promise SATA SX8 block driver");
50*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun  * SX8 hardware has a single message queue for all ATA ports.
54*4882a593Smuzhiyun  * When this driver was written, the hardware (firmware?) would
55*4882a593Smuzhiyun  * corrupt data eventually, if more than one request was outstanding.
56*4882a593Smuzhiyun  * As one can imagine, having 8 ports bottlenecking on a single
57*4882a593Smuzhiyun  * command hurts performance.
58*4882a593Smuzhiyun  *
59*4882a593Smuzhiyun  * Based on user reports, later versions of the hardware (firmware?)
60*4882a593Smuzhiyun  * seem to be able to survive with more than one command queued.
61*4882a593Smuzhiyun  *
62*4882a593Smuzhiyun  * Therefore, we default to the safe option -- 1 command -- but
63*4882a593Smuzhiyun  * allow the user to increase this.
64*4882a593Smuzhiyun  *
65*4882a593Smuzhiyun  * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ),
66*4882a593Smuzhiyun  * but problems seem to occur when you exceed ~30, even on newer hardware.
67*4882a593Smuzhiyun  */
68*4882a593Smuzhiyun static int max_queue = 1;
69*4882a593Smuzhiyun module_param(max_queue, int, 0444);
70*4882a593Smuzhiyun MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)");
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define NEXT_RESP(idx)	((idx + 1) % RMSG_Q_LEN)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */
76*4882a593Smuzhiyun #define TAG_ENCODE(tag)	(((tag) << 16) | 0xf)
77*4882a593Smuzhiyun #define TAG_DECODE(tag)	(((tag) >> 16) & 0x1f)
78*4882a593Smuzhiyun #define TAG_VALID(tag)	((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* note: prints function name for you */
81*4882a593Smuzhiyun #ifdef CARM_DEBUG
82*4882a593Smuzhiyun #define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
83*4882a593Smuzhiyun #ifdef CARM_VERBOSE_DEBUG
84*4882a593Smuzhiyun #define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
85*4882a593Smuzhiyun #else
86*4882a593Smuzhiyun #define VPRINTK(fmt, args...)
87*4882a593Smuzhiyun #endif	/* CARM_VERBOSE_DEBUG */
88*4882a593Smuzhiyun #else
89*4882a593Smuzhiyun #define DPRINTK(fmt, args...)
90*4882a593Smuzhiyun #define VPRINTK(fmt, args...)
91*4882a593Smuzhiyun #endif	/* CARM_DEBUG */
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #ifdef CARM_NDEBUG
94*4882a593Smuzhiyun #define assert(expr)
95*4882a593Smuzhiyun #else
96*4882a593Smuzhiyun #define assert(expr) \
97*4882a593Smuzhiyun         if(unlikely(!(expr))) {                                   \
98*4882a593Smuzhiyun         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
99*4882a593Smuzhiyun 	#expr, __FILE__, __func__, __LINE__);          \
100*4882a593Smuzhiyun         }
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* defines only for the constants which don't work well as enums */
104*4882a593Smuzhiyun struct carm_host;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun enum {
107*4882a593Smuzhiyun 	/* adapter-wide limits */
108*4882a593Smuzhiyun 	CARM_MAX_PORTS		= 8,
109*4882a593Smuzhiyun 	CARM_SHM_SIZE		= (4096 << 7),
110*4882a593Smuzhiyun 	CARM_MINORS_PER_MAJOR	= 256 / CARM_MAX_PORTS,
111*4882a593Smuzhiyun 	CARM_MAX_WAIT_Q		= CARM_MAX_PORTS + 1,
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	/* command message queue limits */
114*4882a593Smuzhiyun 	CARM_MAX_REQ		= 64,	       /* max command msgs per host */
115*4882a593Smuzhiyun 	CARM_MSG_LOW_WATER	= (CARM_MAX_REQ / 4),	     /* refill mark */
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* S/G limits, host-wide and per-request */
118*4882a593Smuzhiyun 	CARM_MAX_REQ_SG		= 32,	     /* max s/g entries per request */
119*4882a593Smuzhiyun 	CARM_MAX_HOST_SG	= 600,		/* max s/g entries per host */
120*4882a593Smuzhiyun 	CARM_SG_LOW_WATER	= (CARM_MAX_HOST_SG / 4),   /* re-fill mark */
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/* hardware registers */
123*4882a593Smuzhiyun 	CARM_IHQP		= 0x1c,
124*4882a593Smuzhiyun 	CARM_INT_STAT		= 0x10, /* interrupt status */
125*4882a593Smuzhiyun 	CARM_INT_MASK		= 0x14, /* interrupt mask */
126*4882a593Smuzhiyun 	CARM_HMUC		= 0x18, /* host message unit control */
127*4882a593Smuzhiyun 	RBUF_ADDR_LO		= 0x20, /* response msg DMA buf low 32 bits */
128*4882a593Smuzhiyun 	RBUF_ADDR_HI		= 0x24, /* response msg DMA buf high 32 bits */
129*4882a593Smuzhiyun 	RBUF_BYTE_SZ		= 0x28,
130*4882a593Smuzhiyun 	CARM_RESP_IDX		= 0x2c,
131*4882a593Smuzhiyun 	CARM_CMS0		= 0x30, /* command message size reg 0 */
132*4882a593Smuzhiyun 	CARM_LMUC		= 0x48,
133*4882a593Smuzhiyun 	CARM_HMPHA		= 0x6c,
134*4882a593Smuzhiyun 	CARM_INITC		= 0xb5,
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* bits in CARM_INT_{STAT,MASK} */
137*4882a593Smuzhiyun 	INT_RESERVED		= 0xfffffff0,
138*4882a593Smuzhiyun 	INT_WATCHDOG		= (1 << 3),	/* watchdog timer */
139*4882a593Smuzhiyun 	INT_Q_OVERFLOW		= (1 << 2),	/* cmd msg q overflow */
140*4882a593Smuzhiyun 	INT_Q_AVAILABLE		= (1 << 1),	/* cmd msg q has free space */
141*4882a593Smuzhiyun 	INT_RESPONSE		= (1 << 0),	/* response msg available */
142*4882a593Smuzhiyun 	INT_ACK_MASK		= INT_WATCHDOG | INT_Q_OVERFLOW,
143*4882a593Smuzhiyun 	INT_DEF_MASK		= INT_RESERVED | INT_Q_OVERFLOW |
144*4882a593Smuzhiyun 				  INT_RESPONSE,
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	/* command messages, and related register bits */
147*4882a593Smuzhiyun 	CARM_HAVE_RESP		= 0x01,
148*4882a593Smuzhiyun 	CARM_MSG_READ		= 1,
149*4882a593Smuzhiyun 	CARM_MSG_WRITE		= 2,
150*4882a593Smuzhiyun 	CARM_MSG_VERIFY		= 3,
151*4882a593Smuzhiyun 	CARM_MSG_GET_CAPACITY	= 4,
152*4882a593Smuzhiyun 	CARM_MSG_FLUSH		= 5,
153*4882a593Smuzhiyun 	CARM_MSG_IOCTL		= 6,
154*4882a593Smuzhiyun 	CARM_MSG_ARRAY		= 8,
155*4882a593Smuzhiyun 	CARM_MSG_MISC		= 9,
156*4882a593Smuzhiyun 	CARM_CME		= (1 << 2),
157*4882a593Smuzhiyun 	CARM_RME		= (1 << 1),
158*4882a593Smuzhiyun 	CARM_WZBC		= (1 << 0),
159*4882a593Smuzhiyun 	CARM_RMI		= (1 << 0),
160*4882a593Smuzhiyun 	CARM_Q_FULL		= (1 << 3),
161*4882a593Smuzhiyun 	CARM_MSG_SIZE		= 288,
162*4882a593Smuzhiyun 	CARM_Q_LEN		= 48,
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* CARM_MSG_IOCTL messages */
165*4882a593Smuzhiyun 	CARM_IOC_SCAN_CHAN	= 5,	/* scan channels for devices */
166*4882a593Smuzhiyun 	CARM_IOC_GET_TCQ	= 13,	/* get tcq/ncq depth */
167*4882a593Smuzhiyun 	CARM_IOC_SET_TCQ	= 14,	/* set tcq/ncq depth */
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	IOC_SCAN_CHAN_NODEV	= 0x1f,
170*4882a593Smuzhiyun 	IOC_SCAN_CHAN_OFFSET	= 0x40,
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* CARM_MSG_ARRAY messages */
173*4882a593Smuzhiyun 	CARM_ARRAY_INFO		= 0,
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	ARRAY_NO_EXIST		= (1 << 31),
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* response messages */
178*4882a593Smuzhiyun 	RMSG_SZ			= 8,	/* sizeof(struct carm_response) */
179*4882a593Smuzhiyun 	RMSG_Q_LEN		= 48,	/* resp. msg list length */
180*4882a593Smuzhiyun 	RMSG_OK			= 1,	/* bit indicating msg was successful */
181*4882a593Smuzhiyun 					/* length of entire resp. msg buffer */
182*4882a593Smuzhiyun 	RBUF_LEN		= RMSG_SZ * RMSG_Q_LEN,
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	PDC_SHM_SIZE		= (4096 << 7), /* length of entire h/w buffer */
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	/* CARM_MSG_MISC messages */
187*4882a593Smuzhiyun 	MISC_GET_FW_VER		= 2,
188*4882a593Smuzhiyun 	MISC_ALLOC_MEM		= 3,
189*4882a593Smuzhiyun 	MISC_SET_TIME		= 5,
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	/* MISC_GET_FW_VER feature bits */
192*4882a593Smuzhiyun 	FW_VER_4PORT		= (1 << 2), /* 1=4 ports, 0=8 ports */
193*4882a593Smuzhiyun 	FW_VER_NON_RAID		= (1 << 1), /* 1=non-RAID firmware, 0=RAID */
194*4882a593Smuzhiyun 	FW_VER_ZCR		= (1 << 0), /* zero channel RAID (whatever that is) */
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* carm_host flags */
197*4882a593Smuzhiyun 	FL_NON_RAID		= FW_VER_NON_RAID,
198*4882a593Smuzhiyun 	FL_4PORT		= FW_VER_4PORT,
199*4882a593Smuzhiyun 	FL_FW_VER_MASK		= (FW_VER_NON_RAID | FW_VER_4PORT),
200*4882a593Smuzhiyun 	FL_DYN_MAJOR		= (1 << 17),
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun enum {
204*4882a593Smuzhiyun 	CARM_SG_BOUNDARY	= 0xffffUL,	    /* s/g segment boundary */
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun enum scatter_gather_types {
208*4882a593Smuzhiyun 	SGT_32BIT		= 0,
209*4882a593Smuzhiyun 	SGT_64BIT		= 1,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun enum host_states {
213*4882a593Smuzhiyun 	HST_INVALID,		/* invalid state; never used */
214*4882a593Smuzhiyun 	HST_ALLOC_BUF,		/* setting up master SHM area */
215*4882a593Smuzhiyun 	HST_ERROR,		/* we never leave here */
216*4882a593Smuzhiyun 	HST_PORT_SCAN,		/* start dev scan */
217*4882a593Smuzhiyun 	HST_DEV_SCAN_START,	/* start per-device probe */
218*4882a593Smuzhiyun 	HST_DEV_SCAN,		/* continue per-device probe */
219*4882a593Smuzhiyun 	HST_DEV_ACTIVATE,	/* activate devices we found */
220*4882a593Smuzhiyun 	HST_PROBE_FINISHED,	/* probe is complete */
221*4882a593Smuzhiyun 	HST_PROBE_START,	/* initiate probe */
222*4882a593Smuzhiyun 	HST_SYNC_TIME,		/* tell firmware what time it is */
223*4882a593Smuzhiyun 	HST_GET_FW_VER,		/* get firmware version, adapter port cnt */
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun #ifdef CARM_DEBUG
227*4882a593Smuzhiyun static const char *state_name[] = {
228*4882a593Smuzhiyun 	"HST_INVALID",
229*4882a593Smuzhiyun 	"HST_ALLOC_BUF",
230*4882a593Smuzhiyun 	"HST_ERROR",
231*4882a593Smuzhiyun 	"HST_PORT_SCAN",
232*4882a593Smuzhiyun 	"HST_DEV_SCAN_START",
233*4882a593Smuzhiyun 	"HST_DEV_SCAN",
234*4882a593Smuzhiyun 	"HST_DEV_ACTIVATE",
235*4882a593Smuzhiyun 	"HST_PROBE_FINISHED",
236*4882a593Smuzhiyun 	"HST_PROBE_START",
237*4882a593Smuzhiyun 	"HST_SYNC_TIME",
238*4882a593Smuzhiyun 	"HST_GET_FW_VER",
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun #endif
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun struct carm_port {
243*4882a593Smuzhiyun 	unsigned int			port_no;
244*4882a593Smuzhiyun 	struct gendisk			*disk;
245*4882a593Smuzhiyun 	struct carm_host		*host;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	/* attached device characteristics */
248*4882a593Smuzhiyun 	u64				capacity;
249*4882a593Smuzhiyun 	char				name[41];
250*4882a593Smuzhiyun 	u16				dev_geom_head;
251*4882a593Smuzhiyun 	u16				dev_geom_sect;
252*4882a593Smuzhiyun 	u16				dev_geom_cyl;
253*4882a593Smuzhiyun };
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun struct carm_request {
256*4882a593Smuzhiyun 	int				n_elem;
257*4882a593Smuzhiyun 	unsigned int			msg_type;
258*4882a593Smuzhiyun 	unsigned int			msg_subtype;
259*4882a593Smuzhiyun 	unsigned int			msg_bucket;
260*4882a593Smuzhiyun 	struct scatterlist		sg[CARM_MAX_REQ_SG];
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun struct carm_host {
264*4882a593Smuzhiyun 	unsigned long			flags;
265*4882a593Smuzhiyun 	void				__iomem *mmio;
266*4882a593Smuzhiyun 	void				*shm;
267*4882a593Smuzhiyun 	dma_addr_t			shm_dma;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	int				major;
270*4882a593Smuzhiyun 	int				id;
271*4882a593Smuzhiyun 	char				name[32];
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	spinlock_t			lock;
274*4882a593Smuzhiyun 	struct pci_dev			*pdev;
275*4882a593Smuzhiyun 	unsigned int			state;
276*4882a593Smuzhiyun 	u32				fw_ver;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	struct blk_mq_tag_set		tag_set;
279*4882a593Smuzhiyun 	struct request_queue		*oob_q;
280*4882a593Smuzhiyun 	unsigned int			n_oob;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	unsigned int			hw_sg_used;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	unsigned int			resp_idx;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	unsigned int			wait_q_prod;
287*4882a593Smuzhiyun 	unsigned int			wait_q_cons;
288*4882a593Smuzhiyun 	struct request_queue		*wait_q[CARM_MAX_WAIT_Q];
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	void				*msg_base;
291*4882a593Smuzhiyun 	dma_addr_t			msg_dma;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	int				cur_scan_dev;
294*4882a593Smuzhiyun 	unsigned long			dev_active;
295*4882a593Smuzhiyun 	unsigned long			dev_present;
296*4882a593Smuzhiyun 	struct carm_port		port[CARM_MAX_PORTS];
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	struct work_struct		fsm_task;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	struct completion		probe_comp;
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun struct carm_response {
304*4882a593Smuzhiyun 	__le32 ret_handle;
305*4882a593Smuzhiyun 	__le32 status;
306*4882a593Smuzhiyun }  __attribute__((packed));
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun struct carm_msg_sg {
309*4882a593Smuzhiyun 	__le32 start;
310*4882a593Smuzhiyun 	__le32 len;
311*4882a593Smuzhiyun }  __attribute__((packed));
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun struct carm_msg_rw {
314*4882a593Smuzhiyun 	u8 type;
315*4882a593Smuzhiyun 	u8 id;
316*4882a593Smuzhiyun 	u8 sg_count;
317*4882a593Smuzhiyun 	u8 sg_type;
318*4882a593Smuzhiyun 	__le32 handle;
319*4882a593Smuzhiyun 	__le32 lba;
320*4882a593Smuzhiyun 	__le16 lba_count;
321*4882a593Smuzhiyun 	__le16 lba_high;
322*4882a593Smuzhiyun 	struct carm_msg_sg sg[32];
323*4882a593Smuzhiyun }  __attribute__((packed));
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun struct carm_msg_allocbuf {
326*4882a593Smuzhiyun 	u8 type;
327*4882a593Smuzhiyun 	u8 subtype;
328*4882a593Smuzhiyun 	u8 n_sg;
329*4882a593Smuzhiyun 	u8 sg_type;
330*4882a593Smuzhiyun 	__le32 handle;
331*4882a593Smuzhiyun 	__le32 addr;
332*4882a593Smuzhiyun 	__le32 len;
333*4882a593Smuzhiyun 	__le32 evt_pool;
334*4882a593Smuzhiyun 	__le32 n_evt;
335*4882a593Smuzhiyun 	__le32 rbuf_pool;
336*4882a593Smuzhiyun 	__le32 n_rbuf;
337*4882a593Smuzhiyun 	__le32 msg_pool;
338*4882a593Smuzhiyun 	__le32 n_msg;
339*4882a593Smuzhiyun 	struct carm_msg_sg sg[8];
340*4882a593Smuzhiyun }  __attribute__((packed));
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun struct carm_msg_ioctl {
343*4882a593Smuzhiyun 	u8 type;
344*4882a593Smuzhiyun 	u8 subtype;
345*4882a593Smuzhiyun 	u8 array_id;
346*4882a593Smuzhiyun 	u8 reserved1;
347*4882a593Smuzhiyun 	__le32 handle;
348*4882a593Smuzhiyun 	__le32 data_addr;
349*4882a593Smuzhiyun 	u32 reserved2;
350*4882a593Smuzhiyun }  __attribute__((packed));
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun struct carm_msg_sync_time {
353*4882a593Smuzhiyun 	u8 type;
354*4882a593Smuzhiyun 	u8 subtype;
355*4882a593Smuzhiyun 	u16 reserved1;
356*4882a593Smuzhiyun 	__le32 handle;
357*4882a593Smuzhiyun 	u32 reserved2;
358*4882a593Smuzhiyun 	__le32 timestamp;
359*4882a593Smuzhiyun }  __attribute__((packed));
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun struct carm_msg_get_fw_ver {
362*4882a593Smuzhiyun 	u8 type;
363*4882a593Smuzhiyun 	u8 subtype;
364*4882a593Smuzhiyun 	u16 reserved1;
365*4882a593Smuzhiyun 	__le32 handle;
366*4882a593Smuzhiyun 	__le32 data_addr;
367*4882a593Smuzhiyun 	u32 reserved2;
368*4882a593Smuzhiyun }  __attribute__((packed));
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun struct carm_fw_ver {
371*4882a593Smuzhiyun 	__le32 version;
372*4882a593Smuzhiyun 	u8 features;
373*4882a593Smuzhiyun 	u8 reserved1;
374*4882a593Smuzhiyun 	u16 reserved2;
375*4882a593Smuzhiyun }  __attribute__((packed));
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun struct carm_array_info {
378*4882a593Smuzhiyun 	__le32 size;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	__le16 size_hi;
381*4882a593Smuzhiyun 	__le16 stripe_size;
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	__le32 mode;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	__le16 stripe_blk_sz;
386*4882a593Smuzhiyun 	__le16 reserved1;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	__le16 cyl;
389*4882a593Smuzhiyun 	__le16 head;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	__le16 sect;
392*4882a593Smuzhiyun 	u8 array_id;
393*4882a593Smuzhiyun 	u8 reserved2;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	char name[40];
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	__le32 array_status;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	/* device list continues beyond this point? */
400*4882a593Smuzhiyun }  __attribute__((packed));
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
403*4882a593Smuzhiyun static void carm_remove_one (struct pci_dev *pdev);
404*4882a593Smuzhiyun static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun static const struct pci_device_id carm_pci_tbl[] = {
407*4882a593Smuzhiyun 	{ PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
408*4882a593Smuzhiyun 	{ PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
409*4882a593Smuzhiyun 	{ }	/* terminate list */
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun static struct pci_driver carm_driver = {
414*4882a593Smuzhiyun 	.name		= DRV_NAME,
415*4882a593Smuzhiyun 	.id_table	= carm_pci_tbl,
416*4882a593Smuzhiyun 	.probe		= carm_init_one,
417*4882a593Smuzhiyun 	.remove		= carm_remove_one,
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun static const struct block_device_operations carm_bd_ops = {
421*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
422*4882a593Smuzhiyun 	.getgeo		= carm_bdev_getgeo,
423*4882a593Smuzhiyun };
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun static unsigned int carm_host_id;
426*4882a593Smuzhiyun static unsigned long carm_major_alloc;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 
carm_bdev_getgeo(struct block_device * bdev,struct hd_geometry * geo)430*4882a593Smuzhiyun static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun 	struct carm_port *port = bdev->bd_disk->private_data;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	geo->heads = (u8) port->dev_geom_head;
435*4882a593Smuzhiyun 	geo->sectors = (u8) port->dev_geom_sect;
436*4882a593Smuzhiyun 	geo->cylinders = port->dev_geom_cyl;
437*4882a593Smuzhiyun 	return 0;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
441*4882a593Smuzhiyun 
carm_lookup_bucket(u32 msg_size)442*4882a593Smuzhiyun static inline int carm_lookup_bucket(u32 msg_size)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun 	int i;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
447*4882a593Smuzhiyun 		if (msg_size <= msg_sizes[i])
448*4882a593Smuzhiyun 			return i;
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	return -ENOENT;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
carm_init_buckets(void __iomem * mmio)453*4882a593Smuzhiyun static void carm_init_buckets(void __iomem *mmio)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	unsigned int i;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
458*4882a593Smuzhiyun 		writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun 
carm_ref_msg(struct carm_host * host,unsigned int msg_idx)461*4882a593Smuzhiyun static inline void *carm_ref_msg(struct carm_host *host,
462*4882a593Smuzhiyun 				 unsigned int msg_idx)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	return host->msg_base + (msg_idx * CARM_MSG_SIZE);
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
carm_ref_msg_dma(struct carm_host * host,unsigned int msg_idx)467*4882a593Smuzhiyun static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
468*4882a593Smuzhiyun 					  unsigned int msg_idx)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun 	return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun 
carm_send_msg(struct carm_host * host,struct carm_request * crq,unsigned tag)473*4882a593Smuzhiyun static int carm_send_msg(struct carm_host *host,
474*4882a593Smuzhiyun 			 struct carm_request *crq, unsigned tag)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun 	void __iomem *mmio = host->mmio;
477*4882a593Smuzhiyun 	u32 msg = (u32) carm_ref_msg_dma(host, tag);
478*4882a593Smuzhiyun 	u32 cm_bucket = crq->msg_bucket;
479*4882a593Smuzhiyun 	u32 tmp;
480*4882a593Smuzhiyun 	int rc = 0;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	VPRINTK("ENTER\n");
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	tmp = readl(mmio + CARM_HMUC);
485*4882a593Smuzhiyun 	if (tmp & CARM_Q_FULL) {
486*4882a593Smuzhiyun #if 0
487*4882a593Smuzhiyun 		tmp = readl(mmio + CARM_INT_MASK);
488*4882a593Smuzhiyun 		tmp |= INT_Q_AVAILABLE;
489*4882a593Smuzhiyun 		writel(tmp, mmio + CARM_INT_MASK);
490*4882a593Smuzhiyun 		readl(mmio + CARM_INT_MASK);	/* flush */
491*4882a593Smuzhiyun #endif
492*4882a593Smuzhiyun 		DPRINTK("host msg queue full\n");
493*4882a593Smuzhiyun 		rc = -EBUSY;
494*4882a593Smuzhiyun 	} else {
495*4882a593Smuzhiyun 		writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
496*4882a593Smuzhiyun 		readl(mmio + CARM_IHQP);	/* flush */
497*4882a593Smuzhiyun 	}
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	return rc;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun 
carm_array_info(struct carm_host * host,unsigned int array_idx)502*4882a593Smuzhiyun static int carm_array_info (struct carm_host *host, unsigned int array_idx)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun 	struct carm_msg_ioctl *ioc;
505*4882a593Smuzhiyun 	u32 msg_data;
506*4882a593Smuzhiyun 	dma_addr_t msg_dma;
507*4882a593Smuzhiyun 	struct carm_request *crq;
508*4882a593Smuzhiyun 	struct request *rq;
509*4882a593Smuzhiyun 	int rc;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	rq = blk_mq_alloc_request(host->oob_q, REQ_OP_DRV_OUT, 0);
512*4882a593Smuzhiyun 	if (IS_ERR(rq)) {
513*4882a593Smuzhiyun 		rc = -ENOMEM;
514*4882a593Smuzhiyun 		goto err_out;
515*4882a593Smuzhiyun 	}
516*4882a593Smuzhiyun 	crq = blk_mq_rq_to_pdu(rq);
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	ioc = carm_ref_msg(host, rq->tag);
519*4882a593Smuzhiyun 	msg_dma = carm_ref_msg_dma(host, rq->tag);
520*4882a593Smuzhiyun 	msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	crq->msg_type = CARM_MSG_ARRAY;
523*4882a593Smuzhiyun 	crq->msg_subtype = CARM_ARRAY_INFO;
524*4882a593Smuzhiyun 	rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
525*4882a593Smuzhiyun 				sizeof(struct carm_array_info));
526*4882a593Smuzhiyun 	BUG_ON(rc < 0);
527*4882a593Smuzhiyun 	crq->msg_bucket = (u32) rc;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	memset(ioc, 0, sizeof(*ioc));
530*4882a593Smuzhiyun 	ioc->type	= CARM_MSG_ARRAY;
531*4882a593Smuzhiyun 	ioc->subtype	= CARM_ARRAY_INFO;
532*4882a593Smuzhiyun 	ioc->array_id	= (u8) array_idx;
533*4882a593Smuzhiyun 	ioc->handle	= cpu_to_le32(TAG_ENCODE(rq->tag));
534*4882a593Smuzhiyun 	ioc->data_addr	= cpu_to_le32(msg_data);
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	spin_lock_irq(&host->lock);
537*4882a593Smuzhiyun 	assert(host->state == HST_DEV_SCAN_START ||
538*4882a593Smuzhiyun 	       host->state == HST_DEV_SCAN);
539*4882a593Smuzhiyun 	spin_unlock_irq(&host->lock);
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	DPRINTK("blk_execute_rq_nowait, tag == %u\n", rq->tag);
542*4882a593Smuzhiyun 	blk_execute_rq_nowait(host->oob_q, NULL, rq, true, NULL);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	return 0;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun err_out:
547*4882a593Smuzhiyun 	spin_lock_irq(&host->lock);
548*4882a593Smuzhiyun 	host->state = HST_ERROR;
549*4882a593Smuzhiyun 	spin_unlock_irq(&host->lock);
550*4882a593Smuzhiyun 	return rc;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
554*4882a593Smuzhiyun 
carm_send_special(struct carm_host * host,carm_sspc_t func)555*4882a593Smuzhiyun static int carm_send_special (struct carm_host *host, carm_sspc_t func)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun 	struct request *rq;
558*4882a593Smuzhiyun 	struct carm_request *crq;
559*4882a593Smuzhiyun 	struct carm_msg_ioctl *ioc;
560*4882a593Smuzhiyun 	void *mem;
561*4882a593Smuzhiyun 	unsigned int msg_size;
562*4882a593Smuzhiyun 	int rc;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	rq = blk_mq_alloc_request(host->oob_q, REQ_OP_DRV_OUT, 0);
565*4882a593Smuzhiyun 	if (IS_ERR(rq))
566*4882a593Smuzhiyun 		return -ENOMEM;
567*4882a593Smuzhiyun 	crq = blk_mq_rq_to_pdu(rq);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	mem = carm_ref_msg(host, rq->tag);
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	msg_size = func(host, rq->tag, mem);
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	ioc = mem;
574*4882a593Smuzhiyun 	crq->msg_type = ioc->type;
575*4882a593Smuzhiyun 	crq->msg_subtype = ioc->subtype;
576*4882a593Smuzhiyun 	rc = carm_lookup_bucket(msg_size);
577*4882a593Smuzhiyun 	BUG_ON(rc < 0);
578*4882a593Smuzhiyun 	crq->msg_bucket = (u32) rc;
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	DPRINTK("blk_execute_rq_nowait, tag == %u\n", rq->tag);
581*4882a593Smuzhiyun 	blk_execute_rq_nowait(host->oob_q, NULL, rq, true, NULL);
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	return 0;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun 
carm_fill_sync_time(struct carm_host * host,unsigned int idx,void * mem)586*4882a593Smuzhiyun static unsigned int carm_fill_sync_time(struct carm_host *host,
587*4882a593Smuzhiyun 					unsigned int idx, void *mem)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	struct carm_msg_sync_time *st = mem;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	time64_t tv = ktime_get_real_seconds();
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	memset(st, 0, sizeof(*st));
594*4882a593Smuzhiyun 	st->type	= CARM_MSG_MISC;
595*4882a593Smuzhiyun 	st->subtype	= MISC_SET_TIME;
596*4882a593Smuzhiyun 	st->handle	= cpu_to_le32(TAG_ENCODE(idx));
597*4882a593Smuzhiyun 	st->timestamp	= cpu_to_le32(tv);
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	return sizeof(struct carm_msg_sync_time);
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun 
carm_fill_alloc_buf(struct carm_host * host,unsigned int idx,void * mem)602*4882a593Smuzhiyun static unsigned int carm_fill_alloc_buf(struct carm_host *host,
603*4882a593Smuzhiyun 					unsigned int idx, void *mem)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun 	struct carm_msg_allocbuf *ab = mem;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	memset(ab, 0, sizeof(*ab));
608*4882a593Smuzhiyun 	ab->type	= CARM_MSG_MISC;
609*4882a593Smuzhiyun 	ab->subtype	= MISC_ALLOC_MEM;
610*4882a593Smuzhiyun 	ab->handle	= cpu_to_le32(TAG_ENCODE(idx));
611*4882a593Smuzhiyun 	ab->n_sg	= 1;
612*4882a593Smuzhiyun 	ab->sg_type	= SGT_32BIT;
613*4882a593Smuzhiyun 	ab->addr	= cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
614*4882a593Smuzhiyun 	ab->len		= cpu_to_le32(PDC_SHM_SIZE >> 1);
615*4882a593Smuzhiyun 	ab->evt_pool	= cpu_to_le32(host->shm_dma + (16 * 1024));
616*4882a593Smuzhiyun 	ab->n_evt	= cpu_to_le32(1024);
617*4882a593Smuzhiyun 	ab->rbuf_pool	= cpu_to_le32(host->shm_dma);
618*4882a593Smuzhiyun 	ab->n_rbuf	= cpu_to_le32(RMSG_Q_LEN);
619*4882a593Smuzhiyun 	ab->msg_pool	= cpu_to_le32(host->shm_dma + RBUF_LEN);
620*4882a593Smuzhiyun 	ab->n_msg	= cpu_to_le32(CARM_Q_LEN);
621*4882a593Smuzhiyun 	ab->sg[0].start	= cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
622*4882a593Smuzhiyun 	ab->sg[0].len	= cpu_to_le32(65536);
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	return sizeof(struct carm_msg_allocbuf);
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun 
carm_fill_scan_channels(struct carm_host * host,unsigned int idx,void * mem)627*4882a593Smuzhiyun static unsigned int carm_fill_scan_channels(struct carm_host *host,
628*4882a593Smuzhiyun 					    unsigned int idx, void *mem)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun 	struct carm_msg_ioctl *ioc = mem;
631*4882a593Smuzhiyun 	u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
632*4882a593Smuzhiyun 			      IOC_SCAN_CHAN_OFFSET);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	memset(ioc, 0, sizeof(*ioc));
635*4882a593Smuzhiyun 	ioc->type	= CARM_MSG_IOCTL;
636*4882a593Smuzhiyun 	ioc->subtype	= CARM_IOC_SCAN_CHAN;
637*4882a593Smuzhiyun 	ioc->handle	= cpu_to_le32(TAG_ENCODE(idx));
638*4882a593Smuzhiyun 	ioc->data_addr	= cpu_to_le32(msg_data);
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	/* fill output data area with "no device" default values */
641*4882a593Smuzhiyun 	mem += IOC_SCAN_CHAN_OFFSET;
642*4882a593Smuzhiyun 	memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun 
carm_fill_get_fw_ver(struct carm_host * host,unsigned int idx,void * mem)647*4882a593Smuzhiyun static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
648*4882a593Smuzhiyun 					 unsigned int idx, void *mem)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun 	struct carm_msg_get_fw_ver *ioc = mem;
651*4882a593Smuzhiyun 	u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	memset(ioc, 0, sizeof(*ioc));
654*4882a593Smuzhiyun 	ioc->type	= CARM_MSG_MISC;
655*4882a593Smuzhiyun 	ioc->subtype	= MISC_GET_FW_VER;
656*4882a593Smuzhiyun 	ioc->handle	= cpu_to_le32(TAG_ENCODE(idx));
657*4882a593Smuzhiyun 	ioc->data_addr	= cpu_to_le32(msg_data);
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	return sizeof(struct carm_msg_get_fw_ver) +
660*4882a593Smuzhiyun 	       sizeof(struct carm_fw_ver);
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun 
carm_push_q(struct carm_host * host,struct request_queue * q)663*4882a593Smuzhiyun static inline void carm_push_q (struct carm_host *host, struct request_queue *q)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun 	unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	blk_mq_stop_hw_queues(q);
668*4882a593Smuzhiyun 	VPRINTK("STOPPED QUEUE %p\n", q);
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	host->wait_q[idx] = q;
671*4882a593Smuzhiyun 	host->wait_q_prod++;
672*4882a593Smuzhiyun 	BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun 
carm_pop_q(struct carm_host * host)675*4882a593Smuzhiyun static inline struct request_queue *carm_pop_q(struct carm_host *host)
676*4882a593Smuzhiyun {
677*4882a593Smuzhiyun 	unsigned int idx;
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	if (host->wait_q_prod == host->wait_q_cons)
680*4882a593Smuzhiyun 		return NULL;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
683*4882a593Smuzhiyun 	host->wait_q_cons++;
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	return host->wait_q[idx];
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun 
carm_round_robin(struct carm_host * host)688*4882a593Smuzhiyun static inline void carm_round_robin(struct carm_host *host)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun 	struct request_queue *q = carm_pop_q(host);
691*4882a593Smuzhiyun 	if (q) {
692*4882a593Smuzhiyun 		blk_mq_start_hw_queues(q);
693*4882a593Smuzhiyun 		VPRINTK("STARTED QUEUE %p\n", q);
694*4882a593Smuzhiyun 	}
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun 
carm_rq_dir(struct request * rq)697*4882a593Smuzhiyun static inline enum dma_data_direction carm_rq_dir(struct request *rq)
698*4882a593Smuzhiyun {
699*4882a593Smuzhiyun 	return op_is_write(req_op(rq)) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun 
carm_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)702*4882a593Smuzhiyun static blk_status_t carm_queue_rq(struct blk_mq_hw_ctx *hctx,
703*4882a593Smuzhiyun 				  const struct blk_mq_queue_data *bd)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	struct request_queue *q = hctx->queue;
706*4882a593Smuzhiyun 	struct request *rq = bd->rq;
707*4882a593Smuzhiyun 	struct carm_port *port = q->queuedata;
708*4882a593Smuzhiyun 	struct carm_host *host = port->host;
709*4882a593Smuzhiyun 	struct carm_request *crq = blk_mq_rq_to_pdu(rq);
710*4882a593Smuzhiyun 	struct carm_msg_rw *msg;
711*4882a593Smuzhiyun 	struct scatterlist *sg;
712*4882a593Smuzhiyun 	int i, n_elem = 0, rc;
713*4882a593Smuzhiyun 	unsigned int msg_size;
714*4882a593Smuzhiyun 	u32 tmp;
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	crq->n_elem = 0;
717*4882a593Smuzhiyun 	sg_init_table(crq->sg, CARM_MAX_REQ_SG);
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	blk_mq_start_request(rq);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	spin_lock_irq(&host->lock);
722*4882a593Smuzhiyun 	if (req_op(rq) == REQ_OP_DRV_OUT)
723*4882a593Smuzhiyun 		goto send_msg;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	/* get scatterlist from block layer */
726*4882a593Smuzhiyun 	sg = &crq->sg[0];
727*4882a593Smuzhiyun 	n_elem = blk_rq_map_sg(q, rq, sg);
728*4882a593Smuzhiyun 	if (n_elem <= 0)
729*4882a593Smuzhiyun 		goto out_ioerr;
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	/* map scatterlist to PCI bus addresses */
732*4882a593Smuzhiyun 	n_elem = dma_map_sg(&host->pdev->dev, sg, n_elem, carm_rq_dir(rq));
733*4882a593Smuzhiyun 	if (n_elem <= 0)
734*4882a593Smuzhiyun 		goto out_ioerr;
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	/* obey global hardware limit on S/G entries */
737*4882a593Smuzhiyun 	if (host->hw_sg_used >= CARM_MAX_HOST_SG - n_elem)
738*4882a593Smuzhiyun 		goto out_resource;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	crq->n_elem = n_elem;
741*4882a593Smuzhiyun 	host->hw_sg_used += n_elem;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	/*
744*4882a593Smuzhiyun 	 * build read/write message
745*4882a593Smuzhiyun 	 */
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	VPRINTK("build msg\n");
748*4882a593Smuzhiyun 	msg = (struct carm_msg_rw *) carm_ref_msg(host, rq->tag);
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun 	if (rq_data_dir(rq) == WRITE) {
751*4882a593Smuzhiyun 		msg->type = CARM_MSG_WRITE;
752*4882a593Smuzhiyun 		crq->msg_type = CARM_MSG_WRITE;
753*4882a593Smuzhiyun 	} else {
754*4882a593Smuzhiyun 		msg->type = CARM_MSG_READ;
755*4882a593Smuzhiyun 		crq->msg_type = CARM_MSG_READ;
756*4882a593Smuzhiyun 	}
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	msg->id		= port->port_no;
759*4882a593Smuzhiyun 	msg->sg_count	= n_elem;
760*4882a593Smuzhiyun 	msg->sg_type	= SGT_32BIT;
761*4882a593Smuzhiyun 	msg->handle	= cpu_to_le32(TAG_ENCODE(rq->tag));
762*4882a593Smuzhiyun 	msg->lba	= cpu_to_le32(blk_rq_pos(rq) & 0xffffffff);
763*4882a593Smuzhiyun 	tmp		= (blk_rq_pos(rq) >> 16) >> 16;
764*4882a593Smuzhiyun 	msg->lba_high	= cpu_to_le16( (u16) tmp );
765*4882a593Smuzhiyun 	msg->lba_count	= cpu_to_le16(blk_rq_sectors(rq));
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 	msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
768*4882a593Smuzhiyun 	for (i = 0; i < n_elem; i++) {
769*4882a593Smuzhiyun 		struct carm_msg_sg *carm_sg = &msg->sg[i];
770*4882a593Smuzhiyun 		carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
771*4882a593Smuzhiyun 		carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
772*4882a593Smuzhiyun 		msg_size += sizeof(struct carm_msg_sg);
773*4882a593Smuzhiyun 	}
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun 	rc = carm_lookup_bucket(msg_size);
776*4882a593Smuzhiyun 	BUG_ON(rc < 0);
777*4882a593Smuzhiyun 	crq->msg_bucket = (u32) rc;
778*4882a593Smuzhiyun send_msg:
779*4882a593Smuzhiyun 	/*
780*4882a593Smuzhiyun 	 * queue read/write message to hardware
781*4882a593Smuzhiyun 	 */
782*4882a593Smuzhiyun 	VPRINTK("send msg, tag == %u\n", rq->tag);
783*4882a593Smuzhiyun 	rc = carm_send_msg(host, crq, rq->tag);
784*4882a593Smuzhiyun 	if (rc) {
785*4882a593Smuzhiyun 		host->hw_sg_used -= n_elem;
786*4882a593Smuzhiyun 		goto out_resource;
787*4882a593Smuzhiyun 	}
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 	spin_unlock_irq(&host->lock);
790*4882a593Smuzhiyun 	return BLK_STS_OK;
791*4882a593Smuzhiyun out_resource:
792*4882a593Smuzhiyun 	dma_unmap_sg(&host->pdev->dev, &crq->sg[0], n_elem, carm_rq_dir(rq));
793*4882a593Smuzhiyun 	carm_push_q(host, q);
794*4882a593Smuzhiyun 	spin_unlock_irq(&host->lock);
795*4882a593Smuzhiyun 	return BLK_STS_DEV_RESOURCE;
796*4882a593Smuzhiyun out_ioerr:
797*4882a593Smuzhiyun 	carm_round_robin(host);
798*4882a593Smuzhiyun 	spin_unlock_irq(&host->lock);
799*4882a593Smuzhiyun 	return BLK_STS_IOERR;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun 
carm_handle_array_info(struct carm_host * host,struct carm_request * crq,u8 * mem,blk_status_t error)802*4882a593Smuzhiyun static void carm_handle_array_info(struct carm_host *host,
803*4882a593Smuzhiyun 				   struct carm_request *crq, u8 *mem,
804*4882a593Smuzhiyun 				   blk_status_t error)
805*4882a593Smuzhiyun {
806*4882a593Smuzhiyun 	struct carm_port *port;
807*4882a593Smuzhiyun 	u8 *msg_data = mem + sizeof(struct carm_array_info);
808*4882a593Smuzhiyun 	struct carm_array_info *desc = (struct carm_array_info *) msg_data;
809*4882a593Smuzhiyun 	u64 lo, hi;
810*4882a593Smuzhiyun 	int cur_port;
811*4882a593Smuzhiyun 	size_t slen;
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	DPRINTK("ENTER\n");
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	if (error)
816*4882a593Smuzhiyun 		goto out;
817*4882a593Smuzhiyun 	if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
818*4882a593Smuzhiyun 		goto out;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	cur_port = host->cur_scan_dev;
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	/* should never occur */
823*4882a593Smuzhiyun 	if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
824*4882a593Smuzhiyun 		printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
825*4882a593Smuzhiyun 		       cur_port, (int) desc->array_id);
826*4882a593Smuzhiyun 		goto out;
827*4882a593Smuzhiyun 	}
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	port = &host->port[cur_port];
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	lo = (u64) le32_to_cpu(desc->size);
832*4882a593Smuzhiyun 	hi = (u64) le16_to_cpu(desc->size_hi);
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun 	port->capacity = lo | (hi << 32);
835*4882a593Smuzhiyun 	port->dev_geom_head = le16_to_cpu(desc->head);
836*4882a593Smuzhiyun 	port->dev_geom_sect = le16_to_cpu(desc->sect);
837*4882a593Smuzhiyun 	port->dev_geom_cyl = le16_to_cpu(desc->cyl);
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	host->dev_active |= (1 << cur_port);
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	strncpy(port->name, desc->name, sizeof(port->name));
842*4882a593Smuzhiyun 	port->name[sizeof(port->name) - 1] = 0;
843*4882a593Smuzhiyun 	slen = strlen(port->name);
844*4882a593Smuzhiyun 	while (slen && (port->name[slen - 1] == ' ')) {
845*4882a593Smuzhiyun 		port->name[slen - 1] = 0;
846*4882a593Smuzhiyun 		slen--;
847*4882a593Smuzhiyun 	}
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
850*4882a593Smuzhiyun 	       pci_name(host->pdev), port->port_no,
851*4882a593Smuzhiyun 	       (unsigned long long) port->capacity);
852*4882a593Smuzhiyun 	printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
853*4882a593Smuzhiyun 	       pci_name(host->pdev), port->port_no, port->name);
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun out:
856*4882a593Smuzhiyun 	assert(host->state == HST_DEV_SCAN);
857*4882a593Smuzhiyun 	schedule_work(&host->fsm_task);
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun 
carm_handle_scan_chan(struct carm_host * host,struct carm_request * crq,u8 * mem,blk_status_t error)860*4882a593Smuzhiyun static void carm_handle_scan_chan(struct carm_host *host,
861*4882a593Smuzhiyun 				  struct carm_request *crq, u8 *mem,
862*4882a593Smuzhiyun 				  blk_status_t error)
863*4882a593Smuzhiyun {
864*4882a593Smuzhiyun 	u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
865*4882a593Smuzhiyun 	unsigned int i, dev_count = 0;
866*4882a593Smuzhiyun 	int new_state = HST_DEV_SCAN_START;
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 	DPRINTK("ENTER\n");
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	if (error) {
871*4882a593Smuzhiyun 		new_state = HST_ERROR;
872*4882a593Smuzhiyun 		goto out;
873*4882a593Smuzhiyun 	}
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun 	/* TODO: scan and support non-disk devices */
876*4882a593Smuzhiyun 	for (i = 0; i < 8; i++)
877*4882a593Smuzhiyun 		if (msg_data[i] == 0) { /* direct-access device (disk) */
878*4882a593Smuzhiyun 			host->dev_present |= (1 << i);
879*4882a593Smuzhiyun 			dev_count++;
880*4882a593Smuzhiyun 		}
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
883*4882a593Smuzhiyun 	       pci_name(host->pdev), dev_count);
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun out:
886*4882a593Smuzhiyun 	assert(host->state == HST_PORT_SCAN);
887*4882a593Smuzhiyun 	host->state = new_state;
888*4882a593Smuzhiyun 	schedule_work(&host->fsm_task);
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun 
carm_handle_generic(struct carm_host * host,struct carm_request * crq,blk_status_t error,int cur_state,int next_state)891*4882a593Smuzhiyun static void carm_handle_generic(struct carm_host *host,
892*4882a593Smuzhiyun 				struct carm_request *crq, blk_status_t error,
893*4882a593Smuzhiyun 				int cur_state, int next_state)
894*4882a593Smuzhiyun {
895*4882a593Smuzhiyun 	DPRINTK("ENTER\n");
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 	assert(host->state == cur_state);
898*4882a593Smuzhiyun 	if (error)
899*4882a593Smuzhiyun 		host->state = HST_ERROR;
900*4882a593Smuzhiyun 	else
901*4882a593Smuzhiyun 		host->state = next_state;
902*4882a593Smuzhiyun 	schedule_work(&host->fsm_task);
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun 
carm_handle_resp(struct carm_host * host,__le32 ret_handle_le,u32 status)905*4882a593Smuzhiyun static inline void carm_handle_resp(struct carm_host *host,
906*4882a593Smuzhiyun 				    __le32 ret_handle_le, u32 status)
907*4882a593Smuzhiyun {
908*4882a593Smuzhiyun 	u32 handle = le32_to_cpu(ret_handle_le);
909*4882a593Smuzhiyun 	unsigned int msg_idx;
910*4882a593Smuzhiyun 	struct request *rq;
911*4882a593Smuzhiyun 	struct carm_request *crq;
912*4882a593Smuzhiyun 	blk_status_t error = (status == RMSG_OK) ? 0 : BLK_STS_IOERR;
913*4882a593Smuzhiyun 	u8 *mem;
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun 	VPRINTK("ENTER, handle == 0x%x\n", handle);
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 	if (unlikely(!TAG_VALID(handle))) {
918*4882a593Smuzhiyun 		printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
919*4882a593Smuzhiyun 		       pci_name(host->pdev), handle);
920*4882a593Smuzhiyun 		return;
921*4882a593Smuzhiyun 	}
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun 	msg_idx = TAG_DECODE(handle);
924*4882a593Smuzhiyun 	VPRINTK("tag == %u\n", msg_idx);
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 	rq = blk_mq_tag_to_rq(host->tag_set.tags[0], msg_idx);
927*4882a593Smuzhiyun 	crq = blk_mq_rq_to_pdu(rq);
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	/* fast path */
930*4882a593Smuzhiyun 	if (likely(crq->msg_type == CARM_MSG_READ ||
931*4882a593Smuzhiyun 		   crq->msg_type == CARM_MSG_WRITE)) {
932*4882a593Smuzhiyun 		dma_unmap_sg(&host->pdev->dev, &crq->sg[0], crq->n_elem,
933*4882a593Smuzhiyun 			     carm_rq_dir(rq));
934*4882a593Smuzhiyun 		goto done;
935*4882a593Smuzhiyun 	}
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun 	mem = carm_ref_msg(host, msg_idx);
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	switch (crq->msg_type) {
940*4882a593Smuzhiyun 	case CARM_MSG_IOCTL: {
941*4882a593Smuzhiyun 		switch (crq->msg_subtype) {
942*4882a593Smuzhiyun 		case CARM_IOC_SCAN_CHAN:
943*4882a593Smuzhiyun 			carm_handle_scan_chan(host, crq, mem, error);
944*4882a593Smuzhiyun 			goto done;
945*4882a593Smuzhiyun 		default:
946*4882a593Smuzhiyun 			/* unknown / invalid response */
947*4882a593Smuzhiyun 			goto err_out;
948*4882a593Smuzhiyun 		}
949*4882a593Smuzhiyun 		break;
950*4882a593Smuzhiyun 	}
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	case CARM_MSG_MISC: {
953*4882a593Smuzhiyun 		switch (crq->msg_subtype) {
954*4882a593Smuzhiyun 		case MISC_ALLOC_MEM:
955*4882a593Smuzhiyun 			carm_handle_generic(host, crq, error,
956*4882a593Smuzhiyun 					    HST_ALLOC_BUF, HST_SYNC_TIME);
957*4882a593Smuzhiyun 			goto done;
958*4882a593Smuzhiyun 		case MISC_SET_TIME:
959*4882a593Smuzhiyun 			carm_handle_generic(host, crq, error,
960*4882a593Smuzhiyun 					    HST_SYNC_TIME, HST_GET_FW_VER);
961*4882a593Smuzhiyun 			goto done;
962*4882a593Smuzhiyun 		case MISC_GET_FW_VER: {
963*4882a593Smuzhiyun 			struct carm_fw_ver *ver = (struct carm_fw_ver *)
964*4882a593Smuzhiyun 				(mem + sizeof(struct carm_msg_get_fw_ver));
965*4882a593Smuzhiyun 			if (!error) {
966*4882a593Smuzhiyun 				host->fw_ver = le32_to_cpu(ver->version);
967*4882a593Smuzhiyun 				host->flags |= (ver->features & FL_FW_VER_MASK);
968*4882a593Smuzhiyun 			}
969*4882a593Smuzhiyun 			carm_handle_generic(host, crq, error,
970*4882a593Smuzhiyun 					    HST_GET_FW_VER, HST_PORT_SCAN);
971*4882a593Smuzhiyun 			goto done;
972*4882a593Smuzhiyun 		}
973*4882a593Smuzhiyun 		default:
974*4882a593Smuzhiyun 			/* unknown / invalid response */
975*4882a593Smuzhiyun 			goto err_out;
976*4882a593Smuzhiyun 		}
977*4882a593Smuzhiyun 		break;
978*4882a593Smuzhiyun 	}
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	case CARM_MSG_ARRAY: {
981*4882a593Smuzhiyun 		switch (crq->msg_subtype) {
982*4882a593Smuzhiyun 		case CARM_ARRAY_INFO:
983*4882a593Smuzhiyun 			carm_handle_array_info(host, crq, mem, error);
984*4882a593Smuzhiyun 			break;
985*4882a593Smuzhiyun 		default:
986*4882a593Smuzhiyun 			/* unknown / invalid response */
987*4882a593Smuzhiyun 			goto err_out;
988*4882a593Smuzhiyun 		}
989*4882a593Smuzhiyun 		break;
990*4882a593Smuzhiyun 	}
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	default:
993*4882a593Smuzhiyun 		/* unknown / invalid response */
994*4882a593Smuzhiyun 		goto err_out;
995*4882a593Smuzhiyun 	}
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	return;
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun err_out:
1000*4882a593Smuzhiyun 	printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
1001*4882a593Smuzhiyun 	       pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
1002*4882a593Smuzhiyun 	error = BLK_STS_IOERR;
1003*4882a593Smuzhiyun done:
1004*4882a593Smuzhiyun 	host->hw_sg_used -= crq->n_elem;
1005*4882a593Smuzhiyun 	blk_mq_end_request(blk_mq_rq_from_pdu(crq), error);
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 	if (host->hw_sg_used <= CARM_SG_LOW_WATER)
1008*4882a593Smuzhiyun 		carm_round_robin(host);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun 
carm_handle_responses(struct carm_host * host)1011*4882a593Smuzhiyun static inline void carm_handle_responses(struct carm_host *host)
1012*4882a593Smuzhiyun {
1013*4882a593Smuzhiyun 	void __iomem *mmio = host->mmio;
1014*4882a593Smuzhiyun 	struct carm_response *resp = (struct carm_response *) host->shm;
1015*4882a593Smuzhiyun 	unsigned int work = 0;
1016*4882a593Smuzhiyun 	unsigned int idx = host->resp_idx % RMSG_Q_LEN;
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	while (1) {
1019*4882a593Smuzhiyun 		u32 status = le32_to_cpu(resp[idx].status);
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun 		if (status == 0xffffffff) {
1022*4882a593Smuzhiyun 			VPRINTK("ending response on index %u\n", idx);
1023*4882a593Smuzhiyun 			writel(idx << 3, mmio + CARM_RESP_IDX);
1024*4882a593Smuzhiyun 			break;
1025*4882a593Smuzhiyun 		}
1026*4882a593Smuzhiyun 
1027*4882a593Smuzhiyun 		/* response to a message we sent */
1028*4882a593Smuzhiyun 		else if ((status & (1 << 31)) == 0) {
1029*4882a593Smuzhiyun 			VPRINTK("handling msg response on index %u\n", idx);
1030*4882a593Smuzhiyun 			carm_handle_resp(host, resp[idx].ret_handle, status);
1031*4882a593Smuzhiyun 			resp[idx].status = cpu_to_le32(0xffffffff);
1032*4882a593Smuzhiyun 		}
1033*4882a593Smuzhiyun 
1034*4882a593Smuzhiyun 		/* asynchronous events the hardware throws our way */
1035*4882a593Smuzhiyun 		else if ((status & 0xff000000) == (1 << 31)) {
1036*4882a593Smuzhiyun 			u8 *evt_type_ptr = (u8 *) &resp[idx];
1037*4882a593Smuzhiyun 			u8 evt_type = *evt_type_ptr;
1038*4882a593Smuzhiyun 			printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
1039*4882a593Smuzhiyun 			       pci_name(host->pdev), (int) evt_type);
1040*4882a593Smuzhiyun 			resp[idx].status = cpu_to_le32(0xffffffff);
1041*4882a593Smuzhiyun 		}
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 		idx = NEXT_RESP(idx);
1044*4882a593Smuzhiyun 		work++;
1045*4882a593Smuzhiyun 	}
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	VPRINTK("EXIT, work==%u\n", work);
1048*4882a593Smuzhiyun 	host->resp_idx += work;
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun 
carm_interrupt(int irq,void * __host)1051*4882a593Smuzhiyun static irqreturn_t carm_interrupt(int irq, void *__host)
1052*4882a593Smuzhiyun {
1053*4882a593Smuzhiyun 	struct carm_host *host = __host;
1054*4882a593Smuzhiyun 	void __iomem *mmio;
1055*4882a593Smuzhiyun 	u32 mask;
1056*4882a593Smuzhiyun 	int handled = 0;
1057*4882a593Smuzhiyun 	unsigned long flags;
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	if (!host) {
1060*4882a593Smuzhiyun 		VPRINTK("no host\n");
1061*4882a593Smuzhiyun 		return IRQ_NONE;
1062*4882a593Smuzhiyun 	}
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun 	spin_lock_irqsave(&host->lock, flags);
1065*4882a593Smuzhiyun 
1066*4882a593Smuzhiyun 	mmio = host->mmio;
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	/* reading should also clear interrupts */
1069*4882a593Smuzhiyun 	mask = readl(mmio + CARM_INT_STAT);
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	if (mask == 0 || mask == 0xffffffff) {
1072*4882a593Smuzhiyun 		VPRINTK("no work, mask == 0x%x\n", mask);
1073*4882a593Smuzhiyun 		goto out;
1074*4882a593Smuzhiyun 	}
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 	if (mask & INT_ACK_MASK)
1077*4882a593Smuzhiyun 		writel(mask, mmio + CARM_INT_STAT);
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	if (unlikely(host->state == HST_INVALID)) {
1080*4882a593Smuzhiyun 		VPRINTK("not initialized yet, mask = 0x%x\n", mask);
1081*4882a593Smuzhiyun 		goto out;
1082*4882a593Smuzhiyun 	}
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun 	if (mask & CARM_HAVE_RESP) {
1085*4882a593Smuzhiyun 		handled = 1;
1086*4882a593Smuzhiyun 		carm_handle_responses(host);
1087*4882a593Smuzhiyun 	}
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun out:
1090*4882a593Smuzhiyun 	spin_unlock_irqrestore(&host->lock, flags);
1091*4882a593Smuzhiyun 	VPRINTK("EXIT\n");
1092*4882a593Smuzhiyun 	return IRQ_RETVAL(handled);
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun 
carm_fsm_task(struct work_struct * work)1095*4882a593Smuzhiyun static void carm_fsm_task (struct work_struct *work)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun 	struct carm_host *host =
1098*4882a593Smuzhiyun 		container_of(work, struct carm_host, fsm_task);
1099*4882a593Smuzhiyun 	unsigned long flags;
1100*4882a593Smuzhiyun 	unsigned int state;
1101*4882a593Smuzhiyun 	int rc, i, next_dev;
1102*4882a593Smuzhiyun 	int reschedule = 0;
1103*4882a593Smuzhiyun 	int new_state = HST_INVALID;
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	spin_lock_irqsave(&host->lock, flags);
1106*4882a593Smuzhiyun 	state = host->state;
1107*4882a593Smuzhiyun 	spin_unlock_irqrestore(&host->lock, flags);
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun 	DPRINTK("ENTER, state == %s\n", state_name[state]);
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 	switch (state) {
1112*4882a593Smuzhiyun 	case HST_PROBE_START:
1113*4882a593Smuzhiyun 		new_state = HST_ALLOC_BUF;
1114*4882a593Smuzhiyun 		reschedule = 1;
1115*4882a593Smuzhiyun 		break;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	case HST_ALLOC_BUF:
1118*4882a593Smuzhiyun 		rc = carm_send_special(host, carm_fill_alloc_buf);
1119*4882a593Smuzhiyun 		if (rc) {
1120*4882a593Smuzhiyun 			new_state = HST_ERROR;
1121*4882a593Smuzhiyun 			reschedule = 1;
1122*4882a593Smuzhiyun 		}
1123*4882a593Smuzhiyun 		break;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	case HST_SYNC_TIME:
1126*4882a593Smuzhiyun 		rc = carm_send_special(host, carm_fill_sync_time);
1127*4882a593Smuzhiyun 		if (rc) {
1128*4882a593Smuzhiyun 			new_state = HST_ERROR;
1129*4882a593Smuzhiyun 			reschedule = 1;
1130*4882a593Smuzhiyun 		}
1131*4882a593Smuzhiyun 		break;
1132*4882a593Smuzhiyun 
1133*4882a593Smuzhiyun 	case HST_GET_FW_VER:
1134*4882a593Smuzhiyun 		rc = carm_send_special(host, carm_fill_get_fw_ver);
1135*4882a593Smuzhiyun 		if (rc) {
1136*4882a593Smuzhiyun 			new_state = HST_ERROR;
1137*4882a593Smuzhiyun 			reschedule = 1;
1138*4882a593Smuzhiyun 		}
1139*4882a593Smuzhiyun 		break;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	case HST_PORT_SCAN:
1142*4882a593Smuzhiyun 		rc = carm_send_special(host, carm_fill_scan_channels);
1143*4882a593Smuzhiyun 		if (rc) {
1144*4882a593Smuzhiyun 			new_state = HST_ERROR;
1145*4882a593Smuzhiyun 			reschedule = 1;
1146*4882a593Smuzhiyun 		}
1147*4882a593Smuzhiyun 		break;
1148*4882a593Smuzhiyun 
1149*4882a593Smuzhiyun 	case HST_DEV_SCAN_START:
1150*4882a593Smuzhiyun 		host->cur_scan_dev = -1;
1151*4882a593Smuzhiyun 		new_state = HST_DEV_SCAN;
1152*4882a593Smuzhiyun 		reschedule = 1;
1153*4882a593Smuzhiyun 		break;
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 	case HST_DEV_SCAN:
1156*4882a593Smuzhiyun 		next_dev = -1;
1157*4882a593Smuzhiyun 		for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
1158*4882a593Smuzhiyun 			if (host->dev_present & (1 << i)) {
1159*4882a593Smuzhiyun 				next_dev = i;
1160*4882a593Smuzhiyun 				break;
1161*4882a593Smuzhiyun 			}
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun 		if (next_dev >= 0) {
1164*4882a593Smuzhiyun 			host->cur_scan_dev = next_dev;
1165*4882a593Smuzhiyun 			rc = carm_array_info(host, next_dev);
1166*4882a593Smuzhiyun 			if (rc) {
1167*4882a593Smuzhiyun 				new_state = HST_ERROR;
1168*4882a593Smuzhiyun 				reschedule = 1;
1169*4882a593Smuzhiyun 			}
1170*4882a593Smuzhiyun 		} else {
1171*4882a593Smuzhiyun 			new_state = HST_DEV_ACTIVATE;
1172*4882a593Smuzhiyun 			reschedule = 1;
1173*4882a593Smuzhiyun 		}
1174*4882a593Smuzhiyun 		break;
1175*4882a593Smuzhiyun 
1176*4882a593Smuzhiyun 	case HST_DEV_ACTIVATE: {
1177*4882a593Smuzhiyun 		int activated = 0;
1178*4882a593Smuzhiyun 		for (i = 0; i < CARM_MAX_PORTS; i++)
1179*4882a593Smuzhiyun 			if (host->dev_active & (1 << i)) {
1180*4882a593Smuzhiyun 				struct carm_port *port = &host->port[i];
1181*4882a593Smuzhiyun 				struct gendisk *disk = port->disk;
1182*4882a593Smuzhiyun 
1183*4882a593Smuzhiyun 				set_capacity(disk, port->capacity);
1184*4882a593Smuzhiyun 				add_disk(disk);
1185*4882a593Smuzhiyun 				activated++;
1186*4882a593Smuzhiyun 			}
1187*4882a593Smuzhiyun 
1188*4882a593Smuzhiyun 		printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
1189*4882a593Smuzhiyun 		       pci_name(host->pdev), activated);
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 		new_state = HST_PROBE_FINISHED;
1192*4882a593Smuzhiyun 		reschedule = 1;
1193*4882a593Smuzhiyun 		break;
1194*4882a593Smuzhiyun 	}
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 	case HST_PROBE_FINISHED:
1197*4882a593Smuzhiyun 		complete(&host->probe_comp);
1198*4882a593Smuzhiyun 		break;
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun 	case HST_ERROR:
1201*4882a593Smuzhiyun 		/* FIXME: TODO */
1202*4882a593Smuzhiyun 		break;
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	default:
1205*4882a593Smuzhiyun 		/* should never occur */
1206*4882a593Smuzhiyun 		printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
1207*4882a593Smuzhiyun 		assert(0);
1208*4882a593Smuzhiyun 		break;
1209*4882a593Smuzhiyun 	}
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	if (new_state != HST_INVALID) {
1212*4882a593Smuzhiyun 		spin_lock_irqsave(&host->lock, flags);
1213*4882a593Smuzhiyun 		host->state = new_state;
1214*4882a593Smuzhiyun 		spin_unlock_irqrestore(&host->lock, flags);
1215*4882a593Smuzhiyun 	}
1216*4882a593Smuzhiyun 	if (reschedule)
1217*4882a593Smuzhiyun 		schedule_work(&host->fsm_task);
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun 
carm_init_wait(void __iomem * mmio,u32 bits,unsigned int test_bit)1220*4882a593Smuzhiyun static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
1221*4882a593Smuzhiyun {
1222*4882a593Smuzhiyun 	unsigned int i;
1223*4882a593Smuzhiyun 
1224*4882a593Smuzhiyun 	for (i = 0; i < 50000; i++) {
1225*4882a593Smuzhiyun 		u32 tmp = readl(mmio + CARM_LMUC);
1226*4882a593Smuzhiyun 		udelay(100);
1227*4882a593Smuzhiyun 
1228*4882a593Smuzhiyun 		if (test_bit) {
1229*4882a593Smuzhiyun 			if ((tmp & bits) == bits)
1230*4882a593Smuzhiyun 				return 0;
1231*4882a593Smuzhiyun 		} else {
1232*4882a593Smuzhiyun 			if ((tmp & bits) == 0)
1233*4882a593Smuzhiyun 				return 0;
1234*4882a593Smuzhiyun 		}
1235*4882a593Smuzhiyun 
1236*4882a593Smuzhiyun 		cond_resched();
1237*4882a593Smuzhiyun 	}
1238*4882a593Smuzhiyun 
1239*4882a593Smuzhiyun 	printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
1240*4882a593Smuzhiyun 	       bits, test_bit ? "yes" : "no");
1241*4882a593Smuzhiyun 	return -EBUSY;
1242*4882a593Smuzhiyun }
1243*4882a593Smuzhiyun 
carm_init_responses(struct carm_host * host)1244*4882a593Smuzhiyun static void carm_init_responses(struct carm_host *host)
1245*4882a593Smuzhiyun {
1246*4882a593Smuzhiyun 	void __iomem *mmio = host->mmio;
1247*4882a593Smuzhiyun 	unsigned int i;
1248*4882a593Smuzhiyun 	struct carm_response *resp = (struct carm_response *) host->shm;
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun 	for (i = 0; i < RMSG_Q_LEN; i++)
1251*4882a593Smuzhiyun 		resp[i].status = cpu_to_le32(0xffffffff);
1252*4882a593Smuzhiyun 
1253*4882a593Smuzhiyun 	writel(0, mmio + CARM_RESP_IDX);
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun 
carm_init_host(struct carm_host * host)1256*4882a593Smuzhiyun static int carm_init_host(struct carm_host *host)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun 	void __iomem *mmio = host->mmio;
1259*4882a593Smuzhiyun 	u32 tmp;
1260*4882a593Smuzhiyun 	u8 tmp8;
1261*4882a593Smuzhiyun 	int rc;
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	DPRINTK("ENTER\n");
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	writel(0, mmio + CARM_INT_MASK);
1266*4882a593Smuzhiyun 
1267*4882a593Smuzhiyun 	tmp8 = readb(mmio + CARM_INITC);
1268*4882a593Smuzhiyun 	if (tmp8 & 0x01) {
1269*4882a593Smuzhiyun 		tmp8 &= ~0x01;
1270*4882a593Smuzhiyun 		writeb(tmp8, mmio + CARM_INITC);
1271*4882a593Smuzhiyun 		readb(mmio + CARM_INITC);	/* flush */
1272*4882a593Smuzhiyun 
1273*4882a593Smuzhiyun 		DPRINTK("snooze...\n");
1274*4882a593Smuzhiyun 		msleep(5000);
1275*4882a593Smuzhiyun 	}
1276*4882a593Smuzhiyun 
1277*4882a593Smuzhiyun 	tmp = readl(mmio + CARM_HMUC);
1278*4882a593Smuzhiyun 	if (tmp & CARM_CME) {
1279*4882a593Smuzhiyun 		DPRINTK("CME bit present, waiting\n");
1280*4882a593Smuzhiyun 		rc = carm_init_wait(mmio, CARM_CME, 1);
1281*4882a593Smuzhiyun 		if (rc) {
1282*4882a593Smuzhiyun 			DPRINTK("EXIT, carm_init_wait 1 failed\n");
1283*4882a593Smuzhiyun 			return rc;
1284*4882a593Smuzhiyun 		}
1285*4882a593Smuzhiyun 	}
1286*4882a593Smuzhiyun 	if (tmp & CARM_RME) {
1287*4882a593Smuzhiyun 		DPRINTK("RME bit present, waiting\n");
1288*4882a593Smuzhiyun 		rc = carm_init_wait(mmio, CARM_RME, 1);
1289*4882a593Smuzhiyun 		if (rc) {
1290*4882a593Smuzhiyun 			DPRINTK("EXIT, carm_init_wait 2 failed\n");
1291*4882a593Smuzhiyun 			return rc;
1292*4882a593Smuzhiyun 		}
1293*4882a593Smuzhiyun 	}
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 	tmp &= ~(CARM_RME | CARM_CME);
1296*4882a593Smuzhiyun 	writel(tmp, mmio + CARM_HMUC);
1297*4882a593Smuzhiyun 	readl(mmio + CARM_HMUC);	/* flush */
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
1300*4882a593Smuzhiyun 	if (rc) {
1301*4882a593Smuzhiyun 		DPRINTK("EXIT, carm_init_wait 3 failed\n");
1302*4882a593Smuzhiyun 		return rc;
1303*4882a593Smuzhiyun 	}
1304*4882a593Smuzhiyun 
1305*4882a593Smuzhiyun 	carm_init_buckets(mmio);
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
1308*4882a593Smuzhiyun 	writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
1309*4882a593Smuzhiyun 	writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	tmp = readl(mmio + CARM_HMUC);
1312*4882a593Smuzhiyun 	tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
1313*4882a593Smuzhiyun 	writel(tmp, mmio + CARM_HMUC);
1314*4882a593Smuzhiyun 	readl(mmio + CARM_HMUC);	/* flush */
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
1317*4882a593Smuzhiyun 	if (rc) {
1318*4882a593Smuzhiyun 		DPRINTK("EXIT, carm_init_wait 4 failed\n");
1319*4882a593Smuzhiyun 		return rc;
1320*4882a593Smuzhiyun 	}
1321*4882a593Smuzhiyun 
1322*4882a593Smuzhiyun 	writel(0, mmio + CARM_HMPHA);
1323*4882a593Smuzhiyun 	writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun 	carm_init_responses(host);
1326*4882a593Smuzhiyun 
1327*4882a593Smuzhiyun 	/* start initialization, probing state machine */
1328*4882a593Smuzhiyun 	spin_lock_irq(&host->lock);
1329*4882a593Smuzhiyun 	assert(host->state == HST_INVALID);
1330*4882a593Smuzhiyun 	host->state = HST_PROBE_START;
1331*4882a593Smuzhiyun 	spin_unlock_irq(&host->lock);
1332*4882a593Smuzhiyun 	schedule_work(&host->fsm_task);
1333*4882a593Smuzhiyun 
1334*4882a593Smuzhiyun 	DPRINTK("EXIT\n");
1335*4882a593Smuzhiyun 	return 0;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun static const struct blk_mq_ops carm_mq_ops = {
1339*4882a593Smuzhiyun 	.queue_rq	= carm_queue_rq,
1340*4882a593Smuzhiyun };
1341*4882a593Smuzhiyun 
carm_init_disk(struct carm_host * host,unsigned int port_no)1342*4882a593Smuzhiyun static int carm_init_disk(struct carm_host *host, unsigned int port_no)
1343*4882a593Smuzhiyun {
1344*4882a593Smuzhiyun 	struct carm_port *port = &host->port[port_no];
1345*4882a593Smuzhiyun 	struct gendisk *disk;
1346*4882a593Smuzhiyun 	struct request_queue *q;
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun 	port->host = host;
1349*4882a593Smuzhiyun 	port->port_no = port_no;
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun 	disk = alloc_disk(CARM_MINORS_PER_MAJOR);
1352*4882a593Smuzhiyun 	if (!disk)
1353*4882a593Smuzhiyun 		return -ENOMEM;
1354*4882a593Smuzhiyun 
1355*4882a593Smuzhiyun 	port->disk = disk;
1356*4882a593Smuzhiyun 	sprintf(disk->disk_name, DRV_NAME "/%u",
1357*4882a593Smuzhiyun 		(unsigned int)host->id * CARM_MAX_PORTS + port_no);
1358*4882a593Smuzhiyun 	disk->major = host->major;
1359*4882a593Smuzhiyun 	disk->first_minor = port_no * CARM_MINORS_PER_MAJOR;
1360*4882a593Smuzhiyun 	disk->fops = &carm_bd_ops;
1361*4882a593Smuzhiyun 	disk->private_data = port;
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	q = blk_mq_init_queue(&host->tag_set);
1364*4882a593Smuzhiyun 	if (IS_ERR(q))
1365*4882a593Smuzhiyun 		return PTR_ERR(q);
1366*4882a593Smuzhiyun 
1367*4882a593Smuzhiyun 	blk_queue_max_segments(q, CARM_MAX_REQ_SG);
1368*4882a593Smuzhiyun 	blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	q->queuedata = port;
1371*4882a593Smuzhiyun 	disk->queue = q;
1372*4882a593Smuzhiyun 	return 0;
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun 
carm_free_disk(struct carm_host * host,unsigned int port_no)1375*4882a593Smuzhiyun static void carm_free_disk(struct carm_host *host, unsigned int port_no)
1376*4882a593Smuzhiyun {
1377*4882a593Smuzhiyun 	struct carm_port *port = &host->port[port_no];
1378*4882a593Smuzhiyun 	struct gendisk *disk = port->disk;
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 	if (!disk)
1381*4882a593Smuzhiyun 		return;
1382*4882a593Smuzhiyun 
1383*4882a593Smuzhiyun 	if (disk->flags & GENHD_FL_UP)
1384*4882a593Smuzhiyun 		del_gendisk(disk);
1385*4882a593Smuzhiyun 	if (disk->queue)
1386*4882a593Smuzhiyun 		blk_cleanup_queue(disk->queue);
1387*4882a593Smuzhiyun 	put_disk(disk);
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun 
carm_init_shm(struct carm_host * host)1390*4882a593Smuzhiyun static int carm_init_shm(struct carm_host *host)
1391*4882a593Smuzhiyun {
1392*4882a593Smuzhiyun 	host->shm = dma_alloc_coherent(&host->pdev->dev, CARM_SHM_SIZE,
1393*4882a593Smuzhiyun 				       &host->shm_dma, GFP_KERNEL);
1394*4882a593Smuzhiyun 	if (!host->shm)
1395*4882a593Smuzhiyun 		return -ENOMEM;
1396*4882a593Smuzhiyun 
1397*4882a593Smuzhiyun 	host->msg_base = host->shm + RBUF_LEN;
1398*4882a593Smuzhiyun 	host->msg_dma = host->shm_dma + RBUF_LEN;
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun 	memset(host->shm, 0xff, RBUF_LEN);
1401*4882a593Smuzhiyun 	memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 	return 0;
1404*4882a593Smuzhiyun }
1405*4882a593Smuzhiyun 
carm_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1406*4882a593Smuzhiyun static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun 	struct carm_host *host;
1409*4882a593Smuzhiyun 	int rc;
1410*4882a593Smuzhiyun 	struct request_queue *q;
1411*4882a593Smuzhiyun 	unsigned int i;
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun 	printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	rc = pci_enable_device(pdev);
1416*4882a593Smuzhiyun 	if (rc)
1417*4882a593Smuzhiyun 		return rc;
1418*4882a593Smuzhiyun 
1419*4882a593Smuzhiyun 	rc = pci_request_regions(pdev, DRV_NAME);
1420*4882a593Smuzhiyun 	if (rc)
1421*4882a593Smuzhiyun 		goto err_out;
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1424*4882a593Smuzhiyun 	if (rc) {
1425*4882a593Smuzhiyun 		printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
1426*4882a593Smuzhiyun 			pci_name(pdev));
1427*4882a593Smuzhiyun 		goto err_out_regions;
1428*4882a593Smuzhiyun 	}
1429*4882a593Smuzhiyun 
1430*4882a593Smuzhiyun 	host = kzalloc(sizeof(*host), GFP_KERNEL);
1431*4882a593Smuzhiyun 	if (!host) {
1432*4882a593Smuzhiyun 		printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
1433*4882a593Smuzhiyun 		       pci_name(pdev));
1434*4882a593Smuzhiyun 		rc = -ENOMEM;
1435*4882a593Smuzhiyun 		goto err_out_regions;
1436*4882a593Smuzhiyun 	}
1437*4882a593Smuzhiyun 
1438*4882a593Smuzhiyun 	host->pdev = pdev;
1439*4882a593Smuzhiyun 	spin_lock_init(&host->lock);
1440*4882a593Smuzhiyun 	INIT_WORK(&host->fsm_task, carm_fsm_task);
1441*4882a593Smuzhiyun 	init_completion(&host->probe_comp);
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	host->mmio = ioremap(pci_resource_start(pdev, 0),
1444*4882a593Smuzhiyun 			     pci_resource_len(pdev, 0));
1445*4882a593Smuzhiyun 	if (!host->mmio) {
1446*4882a593Smuzhiyun 		printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
1447*4882a593Smuzhiyun 		       pci_name(pdev));
1448*4882a593Smuzhiyun 		rc = -ENOMEM;
1449*4882a593Smuzhiyun 		goto err_out_kfree;
1450*4882a593Smuzhiyun 	}
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun 	rc = carm_init_shm(host);
1453*4882a593Smuzhiyun 	if (rc) {
1454*4882a593Smuzhiyun 		printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
1455*4882a593Smuzhiyun 		       pci_name(pdev));
1456*4882a593Smuzhiyun 		goto err_out_iounmap;
1457*4882a593Smuzhiyun 	}
1458*4882a593Smuzhiyun 
1459*4882a593Smuzhiyun 	memset(&host->tag_set, 0, sizeof(host->tag_set));
1460*4882a593Smuzhiyun 	host->tag_set.ops = &carm_mq_ops;
1461*4882a593Smuzhiyun 	host->tag_set.cmd_size = sizeof(struct carm_request);
1462*4882a593Smuzhiyun 	host->tag_set.nr_hw_queues = 1;
1463*4882a593Smuzhiyun 	host->tag_set.nr_maps = 1;
1464*4882a593Smuzhiyun 	host->tag_set.queue_depth = max_queue;
1465*4882a593Smuzhiyun 	host->tag_set.numa_node = NUMA_NO_NODE;
1466*4882a593Smuzhiyun 	host->tag_set.flags = BLK_MQ_F_SHOULD_MERGE;
1467*4882a593Smuzhiyun 
1468*4882a593Smuzhiyun 	rc = blk_mq_alloc_tag_set(&host->tag_set);
1469*4882a593Smuzhiyun 	if (rc)
1470*4882a593Smuzhiyun 		goto err_out_dma_free;
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	q = blk_mq_init_queue(&host->tag_set);
1473*4882a593Smuzhiyun 	if (IS_ERR(q)) {
1474*4882a593Smuzhiyun 		rc = PTR_ERR(q);
1475*4882a593Smuzhiyun 		blk_mq_free_tag_set(&host->tag_set);
1476*4882a593Smuzhiyun 		goto err_out_dma_free;
1477*4882a593Smuzhiyun 	}
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	host->oob_q = q;
1480*4882a593Smuzhiyun 	q->queuedata = host;
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun 	/*
1483*4882a593Smuzhiyun 	 * Figure out which major to use: 160, 161, or dynamic
1484*4882a593Smuzhiyun 	 */
1485*4882a593Smuzhiyun 	if (!test_and_set_bit(0, &carm_major_alloc))
1486*4882a593Smuzhiyun 		host->major = 160;
1487*4882a593Smuzhiyun 	else if (!test_and_set_bit(1, &carm_major_alloc))
1488*4882a593Smuzhiyun 		host->major = 161;
1489*4882a593Smuzhiyun 	else
1490*4882a593Smuzhiyun 		host->flags |= FL_DYN_MAJOR;
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun 	host->id = carm_host_id;
1493*4882a593Smuzhiyun 	sprintf(host->name, DRV_NAME "%d", carm_host_id);
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	rc = register_blkdev(host->major, host->name);
1496*4882a593Smuzhiyun 	if (rc < 0)
1497*4882a593Smuzhiyun 		goto err_out_free_majors;
1498*4882a593Smuzhiyun 	if (host->flags & FL_DYN_MAJOR)
1499*4882a593Smuzhiyun 		host->major = rc;
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun 	for (i = 0; i < CARM_MAX_PORTS; i++) {
1502*4882a593Smuzhiyun 		rc = carm_init_disk(host, i);
1503*4882a593Smuzhiyun 		if (rc)
1504*4882a593Smuzhiyun 			goto err_out_blkdev_disks;
1505*4882a593Smuzhiyun 	}
1506*4882a593Smuzhiyun 
1507*4882a593Smuzhiyun 	pci_set_master(pdev);
1508*4882a593Smuzhiyun 
1509*4882a593Smuzhiyun 	rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host);
1510*4882a593Smuzhiyun 	if (rc) {
1511*4882a593Smuzhiyun 		printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
1512*4882a593Smuzhiyun 		       pci_name(pdev));
1513*4882a593Smuzhiyun 		goto err_out_blkdev_disks;
1514*4882a593Smuzhiyun 	}
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	rc = carm_init_host(host);
1517*4882a593Smuzhiyun 	if (rc)
1518*4882a593Smuzhiyun 		goto err_out_free_irq;
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	DPRINTK("waiting for probe_comp\n");
1521*4882a593Smuzhiyun 	wait_for_completion(&host->probe_comp);
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n",
1524*4882a593Smuzhiyun 	       host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
1525*4882a593Smuzhiyun 	       (unsigned long long)pci_resource_start(pdev, 0),
1526*4882a593Smuzhiyun 		   pdev->irq, host->major);
1527*4882a593Smuzhiyun 
1528*4882a593Smuzhiyun 	carm_host_id++;
1529*4882a593Smuzhiyun 	pci_set_drvdata(pdev, host);
1530*4882a593Smuzhiyun 	return 0;
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun err_out_free_irq:
1533*4882a593Smuzhiyun 	free_irq(pdev->irq, host);
1534*4882a593Smuzhiyun err_out_blkdev_disks:
1535*4882a593Smuzhiyun 	for (i = 0; i < CARM_MAX_PORTS; i++)
1536*4882a593Smuzhiyun 		carm_free_disk(host, i);
1537*4882a593Smuzhiyun 	unregister_blkdev(host->major, host->name);
1538*4882a593Smuzhiyun err_out_free_majors:
1539*4882a593Smuzhiyun 	if (host->major == 160)
1540*4882a593Smuzhiyun 		clear_bit(0, &carm_major_alloc);
1541*4882a593Smuzhiyun 	else if (host->major == 161)
1542*4882a593Smuzhiyun 		clear_bit(1, &carm_major_alloc);
1543*4882a593Smuzhiyun 	blk_cleanup_queue(host->oob_q);
1544*4882a593Smuzhiyun 	blk_mq_free_tag_set(&host->tag_set);
1545*4882a593Smuzhiyun err_out_dma_free:
1546*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1547*4882a593Smuzhiyun err_out_iounmap:
1548*4882a593Smuzhiyun 	iounmap(host->mmio);
1549*4882a593Smuzhiyun err_out_kfree:
1550*4882a593Smuzhiyun 	kfree(host);
1551*4882a593Smuzhiyun err_out_regions:
1552*4882a593Smuzhiyun 	pci_release_regions(pdev);
1553*4882a593Smuzhiyun err_out:
1554*4882a593Smuzhiyun 	pci_disable_device(pdev);
1555*4882a593Smuzhiyun 	return rc;
1556*4882a593Smuzhiyun }
1557*4882a593Smuzhiyun 
carm_remove_one(struct pci_dev * pdev)1558*4882a593Smuzhiyun static void carm_remove_one (struct pci_dev *pdev)
1559*4882a593Smuzhiyun {
1560*4882a593Smuzhiyun 	struct carm_host *host = pci_get_drvdata(pdev);
1561*4882a593Smuzhiyun 	unsigned int i;
1562*4882a593Smuzhiyun 
1563*4882a593Smuzhiyun 	if (!host) {
1564*4882a593Smuzhiyun 		printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
1565*4882a593Smuzhiyun 		       pci_name(pdev));
1566*4882a593Smuzhiyun 		return;
1567*4882a593Smuzhiyun 	}
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun 	free_irq(pdev->irq, host);
1570*4882a593Smuzhiyun 	for (i = 0; i < CARM_MAX_PORTS; i++)
1571*4882a593Smuzhiyun 		carm_free_disk(host, i);
1572*4882a593Smuzhiyun 	unregister_blkdev(host->major, host->name);
1573*4882a593Smuzhiyun 	if (host->major == 160)
1574*4882a593Smuzhiyun 		clear_bit(0, &carm_major_alloc);
1575*4882a593Smuzhiyun 	else if (host->major == 161)
1576*4882a593Smuzhiyun 		clear_bit(1, &carm_major_alloc);
1577*4882a593Smuzhiyun 	blk_cleanup_queue(host->oob_q);
1578*4882a593Smuzhiyun 	blk_mq_free_tag_set(&host->tag_set);
1579*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1580*4882a593Smuzhiyun 	iounmap(host->mmio);
1581*4882a593Smuzhiyun 	kfree(host);
1582*4882a593Smuzhiyun 	pci_release_regions(pdev);
1583*4882a593Smuzhiyun 	pci_disable_device(pdev);
1584*4882a593Smuzhiyun }
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun module_pci_driver(carm_driver);
1587