1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Filename: config.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
6*4882a593Smuzhiyun * Philip Kelleher <pjk1939@linux.vnet.ibm.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (C) Copyright 2013 IBM Corporation
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/crc32.h>
13*4882a593Smuzhiyun #include <linux/swab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "rsxx_priv.h"
16*4882a593Smuzhiyun #include "rsxx_cfg.h"
17*4882a593Smuzhiyun
initialize_config(struct rsxx_card_cfg * cfg)18*4882a593Smuzhiyun static void initialize_config(struct rsxx_card_cfg *cfg)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun cfg->hdr.version = RSXX_CFG_VERSION;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun cfg->data.block_size = RSXX_HW_BLK_SIZE;
23*4882a593Smuzhiyun cfg->data.stripe_size = RSXX_HW_BLK_SIZE;
24*4882a593Smuzhiyun cfg->data.vendor_id = RSXX_VENDOR_ID_IBM;
25*4882a593Smuzhiyun cfg->data.cache_order = (-1);
26*4882a593Smuzhiyun cfg->data.intr_coal.mode = RSXX_INTR_COAL_DISABLED;
27*4882a593Smuzhiyun cfg->data.intr_coal.count = 0;
28*4882a593Smuzhiyun cfg->data.intr_coal.latency = 0;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
config_data_crc32(struct rsxx_card_cfg * cfg)31*4882a593Smuzhiyun static u32 config_data_crc32(struct rsxx_card_cfg *cfg)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Return the compliment of the CRC to ensure compatibility
35*4882a593Smuzhiyun * (i.e. this is how early rsxx drivers did it.)
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return ~crc32(~0, &cfg->data, sizeof(cfg->data));
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*----------------- Config Byte Swap Functions -------------------*/
config_hdr_be_to_cpu(struct card_cfg_hdr * hdr)43*4882a593Smuzhiyun static void config_hdr_be_to_cpu(struct card_cfg_hdr *hdr)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun hdr->version = be32_to_cpu((__force __be32) hdr->version);
46*4882a593Smuzhiyun hdr->crc = be32_to_cpu((__force __be32) hdr->crc);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
config_hdr_cpu_to_be(struct card_cfg_hdr * hdr)49*4882a593Smuzhiyun static void config_hdr_cpu_to_be(struct card_cfg_hdr *hdr)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun hdr->version = (__force u32) cpu_to_be32(hdr->version);
52*4882a593Smuzhiyun hdr->crc = (__force u32) cpu_to_be32(hdr->crc);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
config_data_swab(struct rsxx_card_cfg * cfg)55*4882a593Smuzhiyun static void config_data_swab(struct rsxx_card_cfg *cfg)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun u32 *data = (u32 *) &cfg->data;
58*4882a593Smuzhiyun int i;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (i = 0; i < (sizeof(cfg->data) / 4); i++)
61*4882a593Smuzhiyun data[i] = swab32(data[i]);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
config_data_le_to_cpu(struct rsxx_card_cfg * cfg)64*4882a593Smuzhiyun static void config_data_le_to_cpu(struct rsxx_card_cfg *cfg)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun u32 *data = (u32 *) &cfg->data;
67*4882a593Smuzhiyun int i;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun for (i = 0; i < (sizeof(cfg->data) / 4); i++)
70*4882a593Smuzhiyun data[i] = le32_to_cpu((__force __le32) data[i]);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
config_data_cpu_to_le(struct rsxx_card_cfg * cfg)73*4882a593Smuzhiyun static void config_data_cpu_to_le(struct rsxx_card_cfg *cfg)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun u32 *data = (u32 *) &cfg->data;
76*4882a593Smuzhiyun int i;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun for (i = 0; i < (sizeof(cfg->data) / 4); i++)
79*4882a593Smuzhiyun data[i] = (__force u32) cpu_to_le32(data[i]);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /*----------------- Config Operations ------------------*/
rsxx_save_config(struct rsxx_cardinfo * card)84*4882a593Smuzhiyun static int rsxx_save_config(struct rsxx_cardinfo *card)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct rsxx_card_cfg cfg;
87*4882a593Smuzhiyun int st;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun memcpy(&cfg, &card->config, sizeof(cfg));
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (unlikely(cfg.hdr.version != RSXX_CFG_VERSION)) {
92*4882a593Smuzhiyun dev_err(CARD_TO_DEV(card),
93*4882a593Smuzhiyun "Cannot save config with invalid version %d\n",
94*4882a593Smuzhiyun cfg.hdr.version);
95*4882a593Smuzhiyun return -EINVAL;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Convert data to little endian for the CRC calculation. */
99*4882a593Smuzhiyun config_data_cpu_to_le(&cfg);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun cfg.hdr.crc = config_data_crc32(&cfg);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun * Swap the data from little endian to big endian so it can be
105*4882a593Smuzhiyun * stored.
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun config_data_swab(&cfg);
108*4882a593Smuzhiyun config_hdr_cpu_to_be(&cfg.hdr);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun st = rsxx_creg_write(card, CREG_ADD_CONFIG, sizeof(cfg), &cfg, 1);
111*4882a593Smuzhiyun if (st)
112*4882a593Smuzhiyun return st;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
rsxx_load_config(struct rsxx_cardinfo * card)117*4882a593Smuzhiyun int rsxx_load_config(struct rsxx_cardinfo *card)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int st;
120*4882a593Smuzhiyun u32 crc;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun st = rsxx_creg_read(card, CREG_ADD_CONFIG, sizeof(card->config),
123*4882a593Smuzhiyun &card->config, 1);
124*4882a593Smuzhiyun if (st) {
125*4882a593Smuzhiyun dev_err(CARD_TO_DEV(card),
126*4882a593Smuzhiyun "Failed reading card config.\n");
127*4882a593Smuzhiyun return st;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun config_hdr_be_to_cpu(&card->config.hdr);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (card->config.hdr.version == RSXX_CFG_VERSION) {
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * We calculate the CRC with the data in little endian, because
135*4882a593Smuzhiyun * early drivers did not take big endian CPUs into account.
136*4882a593Smuzhiyun * The data is always stored in big endian, so we need to byte
137*4882a593Smuzhiyun * swap it before calculating the CRC.
138*4882a593Smuzhiyun */
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun config_data_swab(&card->config);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Check the CRC */
143*4882a593Smuzhiyun crc = config_data_crc32(&card->config);
144*4882a593Smuzhiyun if (crc != card->config.hdr.crc) {
145*4882a593Smuzhiyun dev_err(CARD_TO_DEV(card),
146*4882a593Smuzhiyun "Config corruption detected!\n");
147*4882a593Smuzhiyun dev_info(CARD_TO_DEV(card),
148*4882a593Smuzhiyun "CRC (sb x%08x is x%08x)\n",
149*4882a593Smuzhiyun card->config.hdr.crc, crc);
150*4882a593Smuzhiyun return -EIO;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Convert the data to CPU byteorder */
154*4882a593Smuzhiyun config_data_le_to_cpu(&card->config);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun } else if (card->config.hdr.version != 0) {
157*4882a593Smuzhiyun dev_err(CARD_TO_DEV(card),
158*4882a593Smuzhiyun "Invalid config version %d.\n",
159*4882a593Smuzhiyun card->config.hdr.version);
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun * Config version changes require special handling from the
162*4882a593Smuzhiyun * user
163*4882a593Smuzhiyun */
164*4882a593Smuzhiyun return -EINVAL;
165*4882a593Smuzhiyun } else {
166*4882a593Smuzhiyun dev_info(CARD_TO_DEV(card),
167*4882a593Smuzhiyun "Initializing card configuration.\n");
168*4882a593Smuzhiyun initialize_config(&card->config);
169*4882a593Smuzhiyun st = rsxx_save_config(card);
170*4882a593Smuzhiyun if (st)
171*4882a593Smuzhiyun return st;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun card->config_valid = 1;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "version: x%08x\n",
177*4882a593Smuzhiyun card->config.hdr.version);
178*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "crc: x%08x\n",
179*4882a593Smuzhiyun card->config.hdr.crc);
180*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "block_size: x%08x\n",
181*4882a593Smuzhiyun card->config.data.block_size);
182*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "stripe_size: x%08x\n",
183*4882a593Smuzhiyun card->config.data.stripe_size);
184*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "vendor_id: x%08x\n",
185*4882a593Smuzhiyun card->config.data.vendor_id);
186*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "cache_order: x%08x\n",
187*4882a593Smuzhiyun card->config.data.cache_order);
188*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "mode: x%08x\n",
189*4882a593Smuzhiyun card->config.data.intr_coal.mode);
190*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "count: x%08x\n",
191*4882a593Smuzhiyun card->config.data.intr_coal.count);
192*4882a593Smuzhiyun dev_dbg(CARD_TO_DEV(card), "latency: x%08x\n",
193*4882a593Smuzhiyun card->config.data.intr_coal.latency);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198