1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Micron P320 SSD
4*4882a593Smuzhiyun * Copyright (C) 2011 Micron Technology, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Portions of this code were derived from works subjected to the
7*4882a593Smuzhiyun * following copyright:
8*4882a593Smuzhiyun * Copyright (C) 2009 Integrated Device Technology, Inc.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/ata.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/hdreg.h>
16*4882a593Smuzhiyun #include <linux/uaccess.h>
17*4882a593Smuzhiyun #include <linux/random.h>
18*4882a593Smuzhiyun #include <linux/smp.h>
19*4882a593Smuzhiyun #include <linux/compat.h>
20*4882a593Smuzhiyun #include <linux/fs.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/genhd.h>
23*4882a593Smuzhiyun #include <linux/blkdev.h>
24*4882a593Smuzhiyun #include <linux/blk-mq.h>
25*4882a593Smuzhiyun #include <linux/bio.h>
26*4882a593Smuzhiyun #include <linux/dma-mapping.h>
27*4882a593Smuzhiyun #include <linux/idr.h>
28*4882a593Smuzhiyun #include <linux/kthread.h>
29*4882a593Smuzhiyun #include <../drivers/ata/ahci.h>
30*4882a593Smuzhiyun #include <linux/export.h>
31*4882a593Smuzhiyun #include <linux/debugfs.h>
32*4882a593Smuzhiyun #include <linux/prefetch.h>
33*4882a593Smuzhiyun #include <linux/numa.h>
34*4882a593Smuzhiyun #include "mtip32xx.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define HW_CMD_SLOT_SZ (MTIP_MAX_COMMAND_SLOTS * 32)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* DMA region containing RX Fis, Identify, RLE10, and SMART buffers */
39*4882a593Smuzhiyun #define AHCI_RX_FIS_SZ 0x100
40*4882a593Smuzhiyun #define AHCI_RX_FIS_OFFSET 0x0
41*4882a593Smuzhiyun #define AHCI_IDFY_SZ ATA_SECT_SIZE
42*4882a593Smuzhiyun #define AHCI_IDFY_OFFSET 0x400
43*4882a593Smuzhiyun #define AHCI_SECTBUF_SZ ATA_SECT_SIZE
44*4882a593Smuzhiyun #define AHCI_SECTBUF_OFFSET 0x800
45*4882a593Smuzhiyun #define AHCI_SMARTBUF_SZ ATA_SECT_SIZE
46*4882a593Smuzhiyun #define AHCI_SMARTBUF_OFFSET 0xC00
47*4882a593Smuzhiyun /* 0x100 + 0x200 + 0x200 + 0x200 is smaller than 4k but we pad it out */
48*4882a593Smuzhiyun #define BLOCK_DMA_ALLOC_SZ 4096
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* DMA region containing command table (should be 8192 bytes) */
51*4882a593Smuzhiyun #define AHCI_CMD_SLOT_SZ sizeof(struct mtip_cmd_hdr)
52*4882a593Smuzhiyun #define AHCI_CMD_TBL_SZ (MTIP_MAX_COMMAND_SLOTS * AHCI_CMD_SLOT_SZ)
53*4882a593Smuzhiyun #define AHCI_CMD_TBL_OFFSET 0x0
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* DMA region per command (contains header and SGL) */
56*4882a593Smuzhiyun #define AHCI_CMD_TBL_HDR_SZ 0x80
57*4882a593Smuzhiyun #define AHCI_CMD_TBL_HDR_OFFSET 0x0
58*4882a593Smuzhiyun #define AHCI_CMD_TBL_SGL_SZ (MTIP_MAX_SG * sizeof(struct mtip_cmd_sg))
59*4882a593Smuzhiyun #define AHCI_CMD_TBL_SGL_OFFSET AHCI_CMD_TBL_HDR_SZ
60*4882a593Smuzhiyun #define CMD_DMA_ALLOC_SZ (AHCI_CMD_TBL_SGL_SZ + AHCI_CMD_TBL_HDR_SZ)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define HOST_CAP_NZDMA (1 << 19)
64*4882a593Smuzhiyun #define HOST_HSORG 0xFC
65*4882a593Smuzhiyun #define HSORG_DISABLE_SLOTGRP_INTR (1<<24)
66*4882a593Smuzhiyun #define HSORG_DISABLE_SLOTGRP_PXIS (1<<16)
67*4882a593Smuzhiyun #define HSORG_HWREV 0xFF00
68*4882a593Smuzhiyun #define HSORG_STYLE 0x8
69*4882a593Smuzhiyun #define HSORG_SLOTGROUPS 0x7
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define PORT_COMMAND_ISSUE 0x38
72*4882a593Smuzhiyun #define PORT_SDBV 0x7C
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define PORT_OFFSET 0x100
75*4882a593Smuzhiyun #define PORT_MEM_SIZE 0x80
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define PORT_IRQ_ERR \
78*4882a593Smuzhiyun (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | PORT_IRQ_CONNECT | \
79*4882a593Smuzhiyun PORT_IRQ_PHYRDY | PORT_IRQ_UNK_FIS | PORT_IRQ_BAD_PMP | \
80*4882a593Smuzhiyun PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_NONFATAL | \
81*4882a593Smuzhiyun PORT_IRQ_OVERFLOW)
82*4882a593Smuzhiyun #define PORT_IRQ_LEGACY \
83*4882a593Smuzhiyun (PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
84*4882a593Smuzhiyun #define PORT_IRQ_HANDLED \
85*4882a593Smuzhiyun (PORT_IRQ_SDB_FIS | PORT_IRQ_LEGACY | \
86*4882a593Smuzhiyun PORT_IRQ_TF_ERR | PORT_IRQ_IF_ERR | \
87*4882a593Smuzhiyun PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)
88*4882a593Smuzhiyun #define DEF_PORT_IRQ \
89*4882a593Smuzhiyun (PORT_IRQ_ERR | PORT_IRQ_LEGACY | PORT_IRQ_SDB_FIS)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* product numbers */
92*4882a593Smuzhiyun #define MTIP_PRODUCT_UNKNOWN 0x00
93*4882a593Smuzhiyun #define MTIP_PRODUCT_ASICFPGA 0x11
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Device instance number, incremented each time a device is probed. */
96*4882a593Smuzhiyun static int instance;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct list_head online_list;
99*4882a593Smuzhiyun static struct list_head removing_list;
100*4882a593Smuzhiyun static spinlock_t dev_lock;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * Global variable used to hold the major block device number
104*4882a593Smuzhiyun * allocated in mtip_init().
105*4882a593Smuzhiyun */
106*4882a593Smuzhiyun static int mtip_major;
107*4882a593Smuzhiyun static struct dentry *dfs_parent;
108*4882a593Smuzhiyun static struct dentry *dfs_device_status;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static u32 cpu_use[NR_CPUS];
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static DEFINE_IDA(rssd_index_ida);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static int mtip_block_initialize(struct driver_data *dd);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
117*4882a593Smuzhiyun struct mtip_compat_ide_task_request_s {
118*4882a593Smuzhiyun __u8 io_ports[8];
119*4882a593Smuzhiyun __u8 hob_ports[8];
120*4882a593Smuzhiyun ide_reg_valid_t out_flags;
121*4882a593Smuzhiyun ide_reg_valid_t in_flags;
122*4882a593Smuzhiyun int data_phase;
123*4882a593Smuzhiyun int req_cmd;
124*4882a593Smuzhiyun compat_ulong_t out_size;
125*4882a593Smuzhiyun compat_ulong_t in_size;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun #endif
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * This function check_for_surprise_removal is called
131*4882a593Smuzhiyun * while card is removed from the system and it will
132*4882a593Smuzhiyun * read the vendor id from the configuration space
133*4882a593Smuzhiyun *
134*4882a593Smuzhiyun * @pdev Pointer to the pci_dev structure.
135*4882a593Smuzhiyun *
136*4882a593Smuzhiyun * return value
137*4882a593Smuzhiyun * true if device removed, else false
138*4882a593Smuzhiyun */
mtip_check_surprise_removal(struct pci_dev * pdev)139*4882a593Smuzhiyun static bool mtip_check_surprise_removal(struct pci_dev *pdev)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun u16 vendor_id = 0;
142*4882a593Smuzhiyun struct driver_data *dd = pci_get_drvdata(pdev);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (dd->sr)
145*4882a593Smuzhiyun return true;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Read the vendorID from the configuration space */
148*4882a593Smuzhiyun pci_read_config_word(pdev, 0x00, &vendor_id);
149*4882a593Smuzhiyun if (vendor_id == 0xFFFF) {
150*4882a593Smuzhiyun dd->sr = true;
151*4882a593Smuzhiyun if (dd->queue)
152*4882a593Smuzhiyun blk_queue_flag_set(QUEUE_FLAG_DEAD, dd->queue);
153*4882a593Smuzhiyun else
154*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
155*4882a593Smuzhiyun "%s: dd->queue is NULL\n", __func__);
156*4882a593Smuzhiyun return true; /* device removed */
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return false; /* device present */
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
mtip_cmd_from_tag(struct driver_data * dd,unsigned int tag)162*4882a593Smuzhiyun static struct mtip_cmd *mtip_cmd_from_tag(struct driver_data *dd,
163*4882a593Smuzhiyun unsigned int tag)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct blk_mq_hw_ctx *hctx = dd->queue->queue_hw_ctx[0];
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return blk_mq_rq_to_pdu(blk_mq_tag_to_rq(hctx->tags, tag));
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun * Reset the HBA (without sleeping)
172*4882a593Smuzhiyun *
173*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
174*4882a593Smuzhiyun *
175*4882a593Smuzhiyun * return value
176*4882a593Smuzhiyun * 0 The reset was successful.
177*4882a593Smuzhiyun * -1 The HBA Reset bit did not clear.
178*4882a593Smuzhiyun */
mtip_hba_reset(struct driver_data * dd)179*4882a593Smuzhiyun static int mtip_hba_reset(struct driver_data *dd)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun unsigned long timeout;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* Set the reset bit */
184*4882a593Smuzhiyun writel(HOST_RESET, dd->mmio + HOST_CTL);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* Flush */
187*4882a593Smuzhiyun readl(dd->mmio + HOST_CTL);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /*
190*4882a593Smuzhiyun * Spin for up to 10 seconds waiting for reset acknowledgement. Spec
191*4882a593Smuzhiyun * is 1 sec but in LUN failure conditions, up to 10 secs are required
192*4882a593Smuzhiyun */
193*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(10000);
194*4882a593Smuzhiyun do {
195*4882a593Smuzhiyun mdelay(10);
196*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))
197*4882a593Smuzhiyun return -1;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun } while ((readl(dd->mmio + HOST_CTL) & HOST_RESET)
200*4882a593Smuzhiyun && time_before(jiffies, timeout));
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (readl(dd->mmio + HOST_CTL) & HOST_RESET)
203*4882a593Smuzhiyun return -1;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /*
209*4882a593Smuzhiyun * Issue a command to the hardware.
210*4882a593Smuzhiyun *
211*4882a593Smuzhiyun * Set the appropriate bit in the s_active and Command Issue hardware
212*4882a593Smuzhiyun * registers, causing hardware command processing to begin.
213*4882a593Smuzhiyun *
214*4882a593Smuzhiyun * @port Pointer to the port structure.
215*4882a593Smuzhiyun * @tag The tag of the command to be issued.
216*4882a593Smuzhiyun *
217*4882a593Smuzhiyun * return value
218*4882a593Smuzhiyun * None
219*4882a593Smuzhiyun */
mtip_issue_ncq_command(struct mtip_port * port,int tag)220*4882a593Smuzhiyun static inline void mtip_issue_ncq_command(struct mtip_port *port, int tag)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun int group = tag >> 5;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* guard SACT and CI registers */
225*4882a593Smuzhiyun spin_lock(&port->cmd_issue_lock[group]);
226*4882a593Smuzhiyun writel((1 << MTIP_TAG_BIT(tag)),
227*4882a593Smuzhiyun port->s_active[MTIP_TAG_INDEX(tag)]);
228*4882a593Smuzhiyun writel((1 << MTIP_TAG_BIT(tag)),
229*4882a593Smuzhiyun port->cmd_issue[MTIP_TAG_INDEX(tag)]);
230*4882a593Smuzhiyun spin_unlock(&port->cmd_issue_lock[group]);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /*
234*4882a593Smuzhiyun * Enable/disable the reception of FIS
235*4882a593Smuzhiyun *
236*4882a593Smuzhiyun * @port Pointer to the port data structure
237*4882a593Smuzhiyun * @enable 1 to enable, 0 to disable
238*4882a593Smuzhiyun *
239*4882a593Smuzhiyun * return value
240*4882a593Smuzhiyun * Previous state: 1 enabled, 0 disabled
241*4882a593Smuzhiyun */
mtip_enable_fis(struct mtip_port * port,int enable)242*4882a593Smuzhiyun static int mtip_enable_fis(struct mtip_port *port, int enable)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun u32 tmp;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* enable FIS reception */
247*4882a593Smuzhiyun tmp = readl(port->mmio + PORT_CMD);
248*4882a593Smuzhiyun if (enable)
249*4882a593Smuzhiyun writel(tmp | PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
250*4882a593Smuzhiyun else
251*4882a593Smuzhiyun writel(tmp & ~PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* Flush */
254*4882a593Smuzhiyun readl(port->mmio + PORT_CMD);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun return (((tmp & PORT_CMD_FIS_RX) == PORT_CMD_FIS_RX));
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /*
260*4882a593Smuzhiyun * Enable/disable the DMA engine
261*4882a593Smuzhiyun *
262*4882a593Smuzhiyun * @port Pointer to the port data structure
263*4882a593Smuzhiyun * @enable 1 to enable, 0 to disable
264*4882a593Smuzhiyun *
265*4882a593Smuzhiyun * return value
266*4882a593Smuzhiyun * Previous state: 1 enabled, 0 disabled.
267*4882a593Smuzhiyun */
mtip_enable_engine(struct mtip_port * port,int enable)268*4882a593Smuzhiyun static int mtip_enable_engine(struct mtip_port *port, int enable)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun u32 tmp;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* enable FIS reception */
273*4882a593Smuzhiyun tmp = readl(port->mmio + PORT_CMD);
274*4882a593Smuzhiyun if (enable)
275*4882a593Smuzhiyun writel(tmp | PORT_CMD_START, port->mmio + PORT_CMD);
276*4882a593Smuzhiyun else
277*4882a593Smuzhiyun writel(tmp & ~PORT_CMD_START, port->mmio + PORT_CMD);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun readl(port->mmio + PORT_CMD);
280*4882a593Smuzhiyun return (((tmp & PORT_CMD_START) == PORT_CMD_START));
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun /*
284*4882a593Smuzhiyun * Enables the port DMA engine and FIS reception.
285*4882a593Smuzhiyun *
286*4882a593Smuzhiyun * return value
287*4882a593Smuzhiyun * None
288*4882a593Smuzhiyun */
mtip_start_port(struct mtip_port * port)289*4882a593Smuzhiyun static inline void mtip_start_port(struct mtip_port *port)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun /* Enable FIS reception */
292*4882a593Smuzhiyun mtip_enable_fis(port, 1);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* Enable the DMA engine */
295*4882a593Smuzhiyun mtip_enable_engine(port, 1);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /*
299*4882a593Smuzhiyun * Deinitialize a port by disabling port interrupts, the DMA engine,
300*4882a593Smuzhiyun * and FIS reception.
301*4882a593Smuzhiyun *
302*4882a593Smuzhiyun * @port Pointer to the port structure
303*4882a593Smuzhiyun *
304*4882a593Smuzhiyun * return value
305*4882a593Smuzhiyun * None
306*4882a593Smuzhiyun */
mtip_deinit_port(struct mtip_port * port)307*4882a593Smuzhiyun static inline void mtip_deinit_port(struct mtip_port *port)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun /* Disable interrupts on this port */
310*4882a593Smuzhiyun writel(0, port->mmio + PORT_IRQ_MASK);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* Disable the DMA engine */
313*4882a593Smuzhiyun mtip_enable_engine(port, 0);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /* Disable FIS reception */
316*4882a593Smuzhiyun mtip_enable_fis(port, 0);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun /*
320*4882a593Smuzhiyun * Initialize a port.
321*4882a593Smuzhiyun *
322*4882a593Smuzhiyun * This function deinitializes the port by calling mtip_deinit_port() and
323*4882a593Smuzhiyun * then initializes it by setting the command header and RX FIS addresses,
324*4882a593Smuzhiyun * clearing the SError register and any pending port interrupts before
325*4882a593Smuzhiyun * re-enabling the default set of port interrupts.
326*4882a593Smuzhiyun *
327*4882a593Smuzhiyun * @port Pointer to the port structure.
328*4882a593Smuzhiyun *
329*4882a593Smuzhiyun * return value
330*4882a593Smuzhiyun * None
331*4882a593Smuzhiyun */
mtip_init_port(struct mtip_port * port)332*4882a593Smuzhiyun static void mtip_init_port(struct mtip_port *port)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun int i;
335*4882a593Smuzhiyun mtip_deinit_port(port);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* Program the command list base and FIS base addresses */
338*4882a593Smuzhiyun if (readl(port->dd->mmio + HOST_CAP) & HOST_CAP_64) {
339*4882a593Smuzhiyun writel((port->command_list_dma >> 16) >> 16,
340*4882a593Smuzhiyun port->mmio + PORT_LST_ADDR_HI);
341*4882a593Smuzhiyun writel((port->rxfis_dma >> 16) >> 16,
342*4882a593Smuzhiyun port->mmio + PORT_FIS_ADDR_HI);
343*4882a593Smuzhiyun set_bit(MTIP_PF_HOST_CAP_64, &port->flags);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun writel(port->command_list_dma & 0xFFFFFFFF,
347*4882a593Smuzhiyun port->mmio + PORT_LST_ADDR);
348*4882a593Smuzhiyun writel(port->rxfis_dma & 0xFFFFFFFF, port->mmio + PORT_FIS_ADDR);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun /* Clear SError */
351*4882a593Smuzhiyun writel(readl(port->mmio + PORT_SCR_ERR), port->mmio + PORT_SCR_ERR);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun /* reset the completed registers.*/
354*4882a593Smuzhiyun for (i = 0; i < port->dd->slot_groups; i++)
355*4882a593Smuzhiyun writel(0xFFFFFFFF, port->completed[i]);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun /* Clear any pending interrupts for this port */
358*4882a593Smuzhiyun writel(readl(port->mmio + PORT_IRQ_STAT), port->mmio + PORT_IRQ_STAT);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun /* Clear any pending interrupts on the HBA. */
361*4882a593Smuzhiyun writel(readl(port->dd->mmio + HOST_IRQ_STAT),
362*4882a593Smuzhiyun port->dd->mmio + HOST_IRQ_STAT);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun /* Enable port interrupts */
365*4882a593Smuzhiyun writel(DEF_PORT_IRQ, port->mmio + PORT_IRQ_MASK);
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun /*
369*4882a593Smuzhiyun * Restart a port
370*4882a593Smuzhiyun *
371*4882a593Smuzhiyun * @port Pointer to the port data structure.
372*4882a593Smuzhiyun *
373*4882a593Smuzhiyun * return value
374*4882a593Smuzhiyun * None
375*4882a593Smuzhiyun */
mtip_restart_port(struct mtip_port * port)376*4882a593Smuzhiyun static void mtip_restart_port(struct mtip_port *port)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun unsigned long timeout;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /* Disable the DMA engine */
381*4882a593Smuzhiyun mtip_enable_engine(port, 0);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* Chip quirk: wait up to 500ms for PxCMD.CR == 0 */
384*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(500);
385*4882a593Smuzhiyun while ((readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON)
386*4882a593Smuzhiyun && time_before(jiffies, timeout))
387*4882a593Smuzhiyun ;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
390*4882a593Smuzhiyun return;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /*
393*4882a593Smuzhiyun * Chip quirk: escalate to hba reset if
394*4882a593Smuzhiyun * PxCMD.CR not clear after 500 ms
395*4882a593Smuzhiyun */
396*4882a593Smuzhiyun if (readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON) {
397*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev,
398*4882a593Smuzhiyun "PxCMD.CR not clear, escalating reset\n");
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun if (mtip_hba_reset(port->dd))
401*4882a593Smuzhiyun dev_err(&port->dd->pdev->dev,
402*4882a593Smuzhiyun "HBA reset escalation failed.\n");
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* 30 ms delay before com reset to quiesce chip */
405*4882a593Smuzhiyun mdelay(30);
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev, "Issuing COM reset\n");
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* Set PxSCTL.DET */
411*4882a593Smuzhiyun writel(readl(port->mmio + PORT_SCR_CTL) |
412*4882a593Smuzhiyun 1, port->mmio + PORT_SCR_CTL);
413*4882a593Smuzhiyun readl(port->mmio + PORT_SCR_CTL);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun /* Wait 1 ms to quiesce chip function */
416*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(1);
417*4882a593Smuzhiyun while (time_before(jiffies, timeout))
418*4882a593Smuzhiyun ;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
421*4882a593Smuzhiyun return;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /* Clear PxSCTL.DET */
424*4882a593Smuzhiyun writel(readl(port->mmio + PORT_SCR_CTL) & ~1,
425*4882a593Smuzhiyun port->mmio + PORT_SCR_CTL);
426*4882a593Smuzhiyun readl(port->mmio + PORT_SCR_CTL);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /* Wait 500 ms for bit 0 of PORT_SCR_STS to be set */
429*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(500);
430*4882a593Smuzhiyun while (((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)
431*4882a593Smuzhiyun && time_before(jiffies, timeout))
432*4882a593Smuzhiyun ;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
435*4882a593Smuzhiyun return;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if ((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)
438*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev,
439*4882a593Smuzhiyun "COM reset failed\n");
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun mtip_init_port(port);
442*4882a593Smuzhiyun mtip_start_port(port);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
mtip_device_reset(struct driver_data * dd)446*4882a593Smuzhiyun static int mtip_device_reset(struct driver_data *dd)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun int rv = 0;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (mtip_check_surprise_removal(dd->pdev))
451*4882a593Smuzhiyun return 0;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (mtip_hba_reset(dd) < 0)
454*4882a593Smuzhiyun rv = -EFAULT;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun mdelay(1);
457*4882a593Smuzhiyun mtip_init_port(dd->port);
458*4882a593Smuzhiyun mtip_start_port(dd->port);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun /* Enable interrupts on the HBA. */
461*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
462*4882a593Smuzhiyun dd->mmio + HOST_CTL);
463*4882a593Smuzhiyun return rv;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun /*
467*4882a593Smuzhiyun * Helper function for tag logging
468*4882a593Smuzhiyun */
print_tags(struct driver_data * dd,char * msg,unsigned long * tagbits,int cnt)469*4882a593Smuzhiyun static void print_tags(struct driver_data *dd,
470*4882a593Smuzhiyun char *msg,
471*4882a593Smuzhiyun unsigned long *tagbits,
472*4882a593Smuzhiyun int cnt)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun unsigned char tagmap[128];
475*4882a593Smuzhiyun int group, tagmap_len = 0;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun memset(tagmap, 0, sizeof(tagmap));
478*4882a593Smuzhiyun for (group = SLOTBITS_IN_LONGS; group > 0; group--)
479*4882a593Smuzhiyun tagmap_len += sprintf(tagmap + tagmap_len, "%016lX ",
480*4882a593Smuzhiyun tagbits[group-1]);
481*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
482*4882a593Smuzhiyun "%d command(s) %s: tagmap [%s]", cnt, msg, tagmap);
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun static int mtip_read_log_page(struct mtip_port *port, u8 page, u16 *buffer,
486*4882a593Smuzhiyun dma_addr_t buffer_dma, unsigned int sectors);
487*4882a593Smuzhiyun static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
488*4882a593Smuzhiyun struct smart_attr *attrib);
489*4882a593Smuzhiyun
mtip_complete_command(struct mtip_cmd * cmd,blk_status_t status)490*4882a593Smuzhiyun static void mtip_complete_command(struct mtip_cmd *cmd, blk_status_t status)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun struct request *req = blk_mq_rq_from_pdu(cmd);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun cmd->status = status;
495*4882a593Smuzhiyun if (likely(!blk_should_fake_timeout(req->q)))
496*4882a593Smuzhiyun blk_mq_complete_request(req);
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun /*
500*4882a593Smuzhiyun * Handle an error.
501*4882a593Smuzhiyun *
502*4882a593Smuzhiyun * @dd Pointer to the DRIVER_DATA structure.
503*4882a593Smuzhiyun *
504*4882a593Smuzhiyun * return value
505*4882a593Smuzhiyun * None
506*4882a593Smuzhiyun */
mtip_handle_tfe(struct driver_data * dd)507*4882a593Smuzhiyun static void mtip_handle_tfe(struct driver_data *dd)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun int group, tag, bit, reissue, rv;
510*4882a593Smuzhiyun struct mtip_port *port;
511*4882a593Smuzhiyun struct mtip_cmd *cmd;
512*4882a593Smuzhiyun u32 completed;
513*4882a593Smuzhiyun struct host_to_dev_fis *fis;
514*4882a593Smuzhiyun unsigned long tagaccum[SLOTBITS_IN_LONGS];
515*4882a593Smuzhiyun unsigned int cmd_cnt = 0;
516*4882a593Smuzhiyun unsigned char *buf;
517*4882a593Smuzhiyun char *fail_reason = NULL;
518*4882a593Smuzhiyun int fail_all_ncq_write = 0, fail_all_ncq_cmds = 0;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun dev_warn(&dd->pdev->dev, "Taskfile error\n");
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun port = dd->port;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun if (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags)) {
525*4882a593Smuzhiyun cmd = mtip_cmd_from_tag(dd, MTIP_TAG_INTERNAL);
526*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME " TFE for the internal command\n");
527*4882a593Smuzhiyun mtip_complete_command(cmd, BLK_STS_IOERR);
528*4882a593Smuzhiyun return;
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /* clear the tag accumulator */
532*4882a593Smuzhiyun memset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* Loop through all the groups */
535*4882a593Smuzhiyun for (group = 0; group < dd->slot_groups; group++) {
536*4882a593Smuzhiyun completed = readl(port->completed[group]);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun dev_warn(&dd->pdev->dev, "g=%u, comp=%x\n", group, completed);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun /* clear completed status register in the hardware.*/
541*4882a593Smuzhiyun writel(completed, port->completed[group]);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /* Process successfully completed commands */
544*4882a593Smuzhiyun for (bit = 0; bit < 32 && completed; bit++) {
545*4882a593Smuzhiyun if (!(completed & (1<<bit)))
546*4882a593Smuzhiyun continue;
547*4882a593Smuzhiyun tag = (group << 5) + bit;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun /* Skip the internal command slot */
550*4882a593Smuzhiyun if (tag == MTIP_TAG_INTERNAL)
551*4882a593Smuzhiyun continue;
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun cmd = mtip_cmd_from_tag(dd, tag);
554*4882a593Smuzhiyun mtip_complete_command(cmd, 0);
555*4882a593Smuzhiyun set_bit(tag, tagaccum);
556*4882a593Smuzhiyun cmd_cnt++;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun print_tags(dd, "completed (TFE)", tagaccum, cmd_cnt);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun /* Restart the port */
563*4882a593Smuzhiyun mdelay(20);
564*4882a593Smuzhiyun mtip_restart_port(port);
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* Trying to determine the cause of the error */
567*4882a593Smuzhiyun rv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,
568*4882a593Smuzhiyun dd->port->log_buf,
569*4882a593Smuzhiyun dd->port->log_buf_dma, 1);
570*4882a593Smuzhiyun if (rv) {
571*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
572*4882a593Smuzhiyun "Error in READ LOG EXT (10h) command\n");
573*4882a593Smuzhiyun /* non-critical error, don't fail the load */
574*4882a593Smuzhiyun } else {
575*4882a593Smuzhiyun buf = (unsigned char *)dd->port->log_buf;
576*4882a593Smuzhiyun if (buf[259] & 0x1) {
577*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
578*4882a593Smuzhiyun "Write protect bit is set.\n");
579*4882a593Smuzhiyun set_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag);
580*4882a593Smuzhiyun fail_all_ncq_write = 1;
581*4882a593Smuzhiyun fail_reason = "write protect";
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun if (buf[288] == 0xF7) {
584*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
585*4882a593Smuzhiyun "Exceeded Tmax, drive in thermal shutdown.\n");
586*4882a593Smuzhiyun set_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag);
587*4882a593Smuzhiyun fail_all_ncq_cmds = 1;
588*4882a593Smuzhiyun fail_reason = "thermal shutdown";
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun if (buf[288] == 0xBF) {
591*4882a593Smuzhiyun set_bit(MTIP_DDF_REBUILD_FAILED_BIT, &dd->dd_flag);
592*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
593*4882a593Smuzhiyun "Drive indicates rebuild has failed. Secure erase required.\n");
594*4882a593Smuzhiyun fail_all_ncq_cmds = 1;
595*4882a593Smuzhiyun fail_reason = "rebuild failed";
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* clear the tag accumulator */
600*4882a593Smuzhiyun memset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun /* Loop through all the groups */
603*4882a593Smuzhiyun for (group = 0; group < dd->slot_groups; group++) {
604*4882a593Smuzhiyun for (bit = 0; bit < 32; bit++) {
605*4882a593Smuzhiyun reissue = 1;
606*4882a593Smuzhiyun tag = (group << 5) + bit;
607*4882a593Smuzhiyun cmd = mtip_cmd_from_tag(dd, tag);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun fis = (struct host_to_dev_fis *)cmd->command;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun /* Should re-issue? */
612*4882a593Smuzhiyun if (tag == MTIP_TAG_INTERNAL ||
613*4882a593Smuzhiyun fis->command == ATA_CMD_SET_FEATURES)
614*4882a593Smuzhiyun reissue = 0;
615*4882a593Smuzhiyun else {
616*4882a593Smuzhiyun if (fail_all_ncq_cmds ||
617*4882a593Smuzhiyun (fail_all_ncq_write &&
618*4882a593Smuzhiyun fis->command == ATA_CMD_FPDMA_WRITE)) {
619*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
620*4882a593Smuzhiyun " Fail: %s w/tag %d [%s].\n",
621*4882a593Smuzhiyun fis->command == ATA_CMD_FPDMA_WRITE ?
622*4882a593Smuzhiyun "write" : "read",
623*4882a593Smuzhiyun tag,
624*4882a593Smuzhiyun fail_reason != NULL ?
625*4882a593Smuzhiyun fail_reason : "unknown");
626*4882a593Smuzhiyun mtip_complete_command(cmd, BLK_STS_MEDIUM);
627*4882a593Smuzhiyun continue;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun /*
632*4882a593Smuzhiyun * First check if this command has
633*4882a593Smuzhiyun * exceeded its retries.
634*4882a593Smuzhiyun */
635*4882a593Smuzhiyun if (reissue && (cmd->retries-- > 0)) {
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun set_bit(tag, tagaccum);
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun /* Re-issue the command. */
640*4882a593Smuzhiyun mtip_issue_ncq_command(port, tag);
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun continue;
643*4882a593Smuzhiyun }
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun /* Retire a command that will not be reissued */
646*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev,
647*4882a593Smuzhiyun "retiring tag %d\n", tag);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun mtip_complete_command(cmd, BLK_STS_IOERR);
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun print_tags(dd, "reissued (TFE)", tagaccum, cmd_cnt);
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun /*
656*4882a593Smuzhiyun * Handle a set device bits interrupt
657*4882a593Smuzhiyun */
mtip_workq_sdbfx(struct mtip_port * port,int group,u32 completed)658*4882a593Smuzhiyun static inline void mtip_workq_sdbfx(struct mtip_port *port, int group,
659*4882a593Smuzhiyun u32 completed)
660*4882a593Smuzhiyun {
661*4882a593Smuzhiyun struct driver_data *dd = port->dd;
662*4882a593Smuzhiyun int tag, bit;
663*4882a593Smuzhiyun struct mtip_cmd *command;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (!completed) {
666*4882a593Smuzhiyun WARN_ON_ONCE(!completed);
667*4882a593Smuzhiyun return;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun /* clear completed status register in the hardware.*/
670*4882a593Smuzhiyun writel(completed, port->completed[group]);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun /* Process completed commands. */
673*4882a593Smuzhiyun for (bit = 0; (bit < 32) && completed; bit++) {
674*4882a593Smuzhiyun if (completed & 0x01) {
675*4882a593Smuzhiyun tag = (group << 5) | bit;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun /* skip internal command slot. */
678*4882a593Smuzhiyun if (unlikely(tag == MTIP_TAG_INTERNAL))
679*4882a593Smuzhiyun continue;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun command = mtip_cmd_from_tag(dd, tag);
682*4882a593Smuzhiyun mtip_complete_command(command, 0);
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun completed >>= 1;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /* If last, re-enable interrupts */
688*4882a593Smuzhiyun if (atomic_dec_return(&dd->irq_workers_active) == 0)
689*4882a593Smuzhiyun writel(0xffffffff, dd->mmio + HOST_IRQ_STAT);
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun /*
693*4882a593Smuzhiyun * Process legacy pio and d2h interrupts
694*4882a593Smuzhiyun */
mtip_process_legacy(struct driver_data * dd,u32 port_stat)695*4882a593Smuzhiyun static inline void mtip_process_legacy(struct driver_data *dd, u32 port_stat)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun struct mtip_port *port = dd->port;
698*4882a593Smuzhiyun struct mtip_cmd *cmd = mtip_cmd_from_tag(dd, MTIP_TAG_INTERNAL);
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun if (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags) && cmd) {
701*4882a593Smuzhiyun int group = MTIP_TAG_INDEX(MTIP_TAG_INTERNAL);
702*4882a593Smuzhiyun int status = readl(port->cmd_issue[group]);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun if (!(status & (1 << MTIP_TAG_BIT(MTIP_TAG_INTERNAL))))
705*4882a593Smuzhiyun mtip_complete_command(cmd, 0);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun /*
710*4882a593Smuzhiyun * Demux and handle errors
711*4882a593Smuzhiyun */
mtip_process_errors(struct driver_data * dd,u32 port_stat)712*4882a593Smuzhiyun static inline void mtip_process_errors(struct driver_data *dd, u32 port_stat)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun if (unlikely(port_stat & PORT_IRQ_CONNECT)) {
715*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
716*4882a593Smuzhiyun "Clearing PxSERR.DIAG.x\n");
717*4882a593Smuzhiyun writel((1 << 26), dd->port->mmio + PORT_SCR_ERR);
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun if (unlikely(port_stat & PORT_IRQ_PHYRDY)) {
721*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
722*4882a593Smuzhiyun "Clearing PxSERR.DIAG.n\n");
723*4882a593Smuzhiyun writel((1 << 16), dd->port->mmio + PORT_SCR_ERR);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun if (unlikely(port_stat & ~PORT_IRQ_HANDLED)) {
727*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
728*4882a593Smuzhiyun "Port stat errors %x unhandled\n",
729*4882a593Smuzhiyun (port_stat & ~PORT_IRQ_HANDLED));
730*4882a593Smuzhiyun if (mtip_check_surprise_removal(dd->pdev))
731*4882a593Smuzhiyun return;
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun if (likely(port_stat & (PORT_IRQ_TF_ERR | PORT_IRQ_IF_ERR))) {
734*4882a593Smuzhiyun set_bit(MTIP_PF_EH_ACTIVE_BIT, &dd->port->flags);
735*4882a593Smuzhiyun wake_up_interruptible(&dd->port->svc_wait);
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
mtip_handle_irq(struct driver_data * data)739*4882a593Smuzhiyun static inline irqreturn_t mtip_handle_irq(struct driver_data *data)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun struct driver_data *dd = (struct driver_data *) data;
742*4882a593Smuzhiyun struct mtip_port *port = dd->port;
743*4882a593Smuzhiyun u32 hba_stat, port_stat;
744*4882a593Smuzhiyun int rv = IRQ_NONE;
745*4882a593Smuzhiyun int do_irq_enable = 1, i, workers;
746*4882a593Smuzhiyun struct mtip_work *twork;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun hba_stat = readl(dd->mmio + HOST_IRQ_STAT);
749*4882a593Smuzhiyun if (hba_stat) {
750*4882a593Smuzhiyun rv = IRQ_HANDLED;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun /* Acknowledge the interrupt status on the port.*/
753*4882a593Smuzhiyun port_stat = readl(port->mmio + PORT_IRQ_STAT);
754*4882a593Smuzhiyun if (unlikely(port_stat == 0xFFFFFFFF)) {
755*4882a593Smuzhiyun mtip_check_surprise_removal(dd->pdev);
756*4882a593Smuzhiyun return IRQ_HANDLED;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun writel(port_stat, port->mmio + PORT_IRQ_STAT);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun /* Demux port status */
761*4882a593Smuzhiyun if (likely(port_stat & PORT_IRQ_SDB_FIS)) {
762*4882a593Smuzhiyun do_irq_enable = 0;
763*4882a593Smuzhiyun WARN_ON_ONCE(atomic_read(&dd->irq_workers_active) != 0);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun /* Start at 1: group zero is always local? */
766*4882a593Smuzhiyun for (i = 0, workers = 0; i < MTIP_MAX_SLOT_GROUPS;
767*4882a593Smuzhiyun i++) {
768*4882a593Smuzhiyun twork = &dd->work[i];
769*4882a593Smuzhiyun twork->completed = readl(port->completed[i]);
770*4882a593Smuzhiyun if (twork->completed)
771*4882a593Smuzhiyun workers++;
772*4882a593Smuzhiyun }
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun atomic_set(&dd->irq_workers_active, workers);
775*4882a593Smuzhiyun if (workers) {
776*4882a593Smuzhiyun for (i = 1; i < MTIP_MAX_SLOT_GROUPS; i++) {
777*4882a593Smuzhiyun twork = &dd->work[i];
778*4882a593Smuzhiyun if (twork->completed)
779*4882a593Smuzhiyun queue_work_on(
780*4882a593Smuzhiyun twork->cpu_binding,
781*4882a593Smuzhiyun dd->isr_workq,
782*4882a593Smuzhiyun &twork->work);
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun if (likely(dd->work[0].completed))
786*4882a593Smuzhiyun mtip_workq_sdbfx(port, 0,
787*4882a593Smuzhiyun dd->work[0].completed);
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun } else {
790*4882a593Smuzhiyun /*
791*4882a593Smuzhiyun * Chip quirk: SDB interrupt but nothing
792*4882a593Smuzhiyun * to complete
793*4882a593Smuzhiyun */
794*4882a593Smuzhiyun do_irq_enable = 1;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun if (unlikely(port_stat & PORT_IRQ_ERR)) {
799*4882a593Smuzhiyun if (unlikely(mtip_check_surprise_removal(dd->pdev))) {
800*4882a593Smuzhiyun /* don't proceed further */
801*4882a593Smuzhiyun return IRQ_HANDLED;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
804*4882a593Smuzhiyun &dd->dd_flag))
805*4882a593Smuzhiyun return rv;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun mtip_process_errors(dd, port_stat & PORT_IRQ_ERR);
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun if (unlikely(port_stat & PORT_IRQ_LEGACY))
811*4882a593Smuzhiyun mtip_process_legacy(dd, port_stat & PORT_IRQ_LEGACY);
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun /* acknowledge interrupt */
815*4882a593Smuzhiyun if (unlikely(do_irq_enable))
816*4882a593Smuzhiyun writel(hba_stat, dd->mmio + HOST_IRQ_STAT);
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun return rv;
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun /*
822*4882a593Smuzhiyun * HBA interrupt subroutine.
823*4882a593Smuzhiyun *
824*4882a593Smuzhiyun * @irq IRQ number.
825*4882a593Smuzhiyun * @instance Pointer to the driver data structure.
826*4882a593Smuzhiyun *
827*4882a593Smuzhiyun * return value
828*4882a593Smuzhiyun * IRQ_HANDLED A HBA interrupt was pending and handled.
829*4882a593Smuzhiyun * IRQ_NONE This interrupt was not for the HBA.
830*4882a593Smuzhiyun */
mtip_irq_handler(int irq,void * instance)831*4882a593Smuzhiyun static irqreturn_t mtip_irq_handler(int irq, void *instance)
832*4882a593Smuzhiyun {
833*4882a593Smuzhiyun struct driver_data *dd = instance;
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun return mtip_handle_irq(dd);
836*4882a593Smuzhiyun }
837*4882a593Smuzhiyun
mtip_issue_non_ncq_command(struct mtip_port * port,int tag)838*4882a593Smuzhiyun static void mtip_issue_non_ncq_command(struct mtip_port *port, int tag)
839*4882a593Smuzhiyun {
840*4882a593Smuzhiyun writel(1 << MTIP_TAG_BIT(tag), port->cmd_issue[MTIP_TAG_INDEX(tag)]);
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun
mtip_pause_ncq(struct mtip_port * port,struct host_to_dev_fis * fis)843*4882a593Smuzhiyun static bool mtip_pause_ncq(struct mtip_port *port,
844*4882a593Smuzhiyun struct host_to_dev_fis *fis)
845*4882a593Smuzhiyun {
846*4882a593Smuzhiyun unsigned long task_file_data;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun task_file_data = readl(port->mmio+PORT_TFDATA);
849*4882a593Smuzhiyun if ((task_file_data & 1))
850*4882a593Smuzhiyun return false;
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun if (fis->command == ATA_CMD_SEC_ERASE_PREP) {
853*4882a593Smuzhiyun port->ic_pause_timer = jiffies;
854*4882a593Smuzhiyun return true;
855*4882a593Smuzhiyun } else if ((fis->command == ATA_CMD_DOWNLOAD_MICRO) &&
856*4882a593Smuzhiyun (fis->features == 0x03)) {
857*4882a593Smuzhiyun set_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
858*4882a593Smuzhiyun port->ic_pause_timer = jiffies;
859*4882a593Smuzhiyun return true;
860*4882a593Smuzhiyun } else if ((fis->command == ATA_CMD_SEC_ERASE_UNIT) ||
861*4882a593Smuzhiyun ((fis->command == 0xFC) &&
862*4882a593Smuzhiyun (fis->features == 0x27 || fis->features == 0x72 ||
863*4882a593Smuzhiyun fis->features == 0x62 || fis->features == 0x26))) {
864*4882a593Smuzhiyun clear_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
865*4882a593Smuzhiyun clear_bit(MTIP_DDF_REBUILD_FAILED_BIT, &port->dd->dd_flag);
866*4882a593Smuzhiyun /* Com reset after secure erase or lowlevel format */
867*4882a593Smuzhiyun mtip_restart_port(port);
868*4882a593Smuzhiyun clear_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
869*4882a593Smuzhiyun return false;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun return false;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun
mtip_commands_active(struct mtip_port * port)875*4882a593Smuzhiyun static bool mtip_commands_active(struct mtip_port *port)
876*4882a593Smuzhiyun {
877*4882a593Smuzhiyun unsigned int active;
878*4882a593Smuzhiyun unsigned int n;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun /*
881*4882a593Smuzhiyun * Ignore s_active bit 0 of array element 0.
882*4882a593Smuzhiyun * This bit will always be set
883*4882a593Smuzhiyun */
884*4882a593Smuzhiyun active = readl(port->s_active[0]) & 0xFFFFFFFE;
885*4882a593Smuzhiyun for (n = 1; n < port->dd->slot_groups; n++)
886*4882a593Smuzhiyun active |= readl(port->s_active[n]);
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun return active != 0;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun /*
892*4882a593Smuzhiyun * Wait for port to quiesce
893*4882a593Smuzhiyun *
894*4882a593Smuzhiyun * @port Pointer to port data structure
895*4882a593Smuzhiyun * @timeout Max duration to wait (ms)
896*4882a593Smuzhiyun *
897*4882a593Smuzhiyun * return value
898*4882a593Smuzhiyun * 0 Success
899*4882a593Smuzhiyun * -EBUSY Commands still active
900*4882a593Smuzhiyun */
mtip_quiesce_io(struct mtip_port * port,unsigned long timeout)901*4882a593Smuzhiyun static int mtip_quiesce_io(struct mtip_port *port, unsigned long timeout)
902*4882a593Smuzhiyun {
903*4882a593Smuzhiyun unsigned long to;
904*4882a593Smuzhiyun bool active = true;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun blk_mq_quiesce_queue(port->dd->queue);
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun to = jiffies + msecs_to_jiffies(timeout);
909*4882a593Smuzhiyun do {
910*4882a593Smuzhiyun if (test_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags) &&
911*4882a593Smuzhiyun test_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags)) {
912*4882a593Smuzhiyun msleep(20);
913*4882a593Smuzhiyun continue; /* svc thd is actively issuing commands */
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun msleep(100);
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun if (mtip_check_surprise_removal(port->dd->pdev))
919*4882a593Smuzhiyun goto err_fault;
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun active = mtip_commands_active(port);
922*4882a593Smuzhiyun if (!active)
923*4882a593Smuzhiyun break;
924*4882a593Smuzhiyun } while (time_before(jiffies, to));
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun blk_mq_unquiesce_queue(port->dd->queue);
927*4882a593Smuzhiyun return active ? -EBUSY : 0;
928*4882a593Smuzhiyun err_fault:
929*4882a593Smuzhiyun blk_mq_unquiesce_queue(port->dd->queue);
930*4882a593Smuzhiyun return -EFAULT;
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun struct mtip_int_cmd {
934*4882a593Smuzhiyun int fis_len;
935*4882a593Smuzhiyun dma_addr_t buffer;
936*4882a593Smuzhiyun int buf_len;
937*4882a593Smuzhiyun u32 opts;
938*4882a593Smuzhiyun };
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun /*
941*4882a593Smuzhiyun * Execute an internal command and wait for the completion.
942*4882a593Smuzhiyun *
943*4882a593Smuzhiyun * @port Pointer to the port data structure.
944*4882a593Smuzhiyun * @fis Pointer to the FIS that describes the command.
945*4882a593Smuzhiyun * @fis_len Length in WORDS of the FIS.
946*4882a593Smuzhiyun * @buffer DMA accessible for command data.
947*4882a593Smuzhiyun * @buf_len Length, in bytes, of the data buffer.
948*4882a593Smuzhiyun * @opts Command header options, excluding the FIS length
949*4882a593Smuzhiyun * and the number of PRD entries.
950*4882a593Smuzhiyun * @timeout Time in ms to wait for the command to complete.
951*4882a593Smuzhiyun *
952*4882a593Smuzhiyun * return value
953*4882a593Smuzhiyun * 0 Command completed successfully.
954*4882a593Smuzhiyun * -EFAULT The buffer address is not correctly aligned.
955*4882a593Smuzhiyun * -EBUSY Internal command or other IO in progress.
956*4882a593Smuzhiyun * -EAGAIN Time out waiting for command to complete.
957*4882a593Smuzhiyun */
mtip_exec_internal_command(struct mtip_port * port,struct host_to_dev_fis * fis,int fis_len,dma_addr_t buffer,int buf_len,u32 opts,unsigned long timeout)958*4882a593Smuzhiyun static int mtip_exec_internal_command(struct mtip_port *port,
959*4882a593Smuzhiyun struct host_to_dev_fis *fis,
960*4882a593Smuzhiyun int fis_len,
961*4882a593Smuzhiyun dma_addr_t buffer,
962*4882a593Smuzhiyun int buf_len,
963*4882a593Smuzhiyun u32 opts,
964*4882a593Smuzhiyun unsigned long timeout)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun struct mtip_cmd *int_cmd;
967*4882a593Smuzhiyun struct driver_data *dd = port->dd;
968*4882a593Smuzhiyun struct request *rq;
969*4882a593Smuzhiyun struct mtip_int_cmd icmd = {
970*4882a593Smuzhiyun .fis_len = fis_len,
971*4882a593Smuzhiyun .buffer = buffer,
972*4882a593Smuzhiyun .buf_len = buf_len,
973*4882a593Smuzhiyun .opts = opts
974*4882a593Smuzhiyun };
975*4882a593Smuzhiyun int rv = 0;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun /* Make sure the buffer is 8 byte aligned. This is asic specific. */
978*4882a593Smuzhiyun if (buffer & 0x00000007) {
979*4882a593Smuzhiyun dev_err(&dd->pdev->dev, "SG buffer is not 8 byte aligned\n");
980*4882a593Smuzhiyun return -EFAULT;
981*4882a593Smuzhiyun }
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (mtip_check_surprise_removal(dd->pdev))
984*4882a593Smuzhiyun return -EFAULT;
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun rq = blk_mq_alloc_request(dd->queue, REQ_OP_DRV_IN, BLK_MQ_REQ_RESERVED);
987*4882a593Smuzhiyun if (IS_ERR(rq)) {
988*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME "Unable to allocate tag for PIO cmd\n");
989*4882a593Smuzhiyun return -EFAULT;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun set_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun if (fis->command == ATA_CMD_SEC_ERASE_PREP)
995*4882a593Smuzhiyun set_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun clear_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun if (fis->command != ATA_CMD_STANDBYNOW1) {
1000*4882a593Smuzhiyun /* wait for io to complete if non atomic */
1001*4882a593Smuzhiyun if (mtip_quiesce_io(port, MTIP_QUIESCE_IO_TIMEOUT_MS) < 0) {
1002*4882a593Smuzhiyun dev_warn(&dd->pdev->dev, "Failed to quiesce IO\n");
1003*4882a593Smuzhiyun blk_mq_free_request(rq);
1004*4882a593Smuzhiyun clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1005*4882a593Smuzhiyun wake_up_interruptible(&port->svc_wait);
1006*4882a593Smuzhiyun return -EBUSY;
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun }
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun /* Copy the command to the command table */
1011*4882a593Smuzhiyun int_cmd = blk_mq_rq_to_pdu(rq);
1012*4882a593Smuzhiyun int_cmd->icmd = &icmd;
1013*4882a593Smuzhiyun memcpy(int_cmd->command, fis, fis_len*4);
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun rq->timeout = timeout;
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun /* insert request and run queue */
1018*4882a593Smuzhiyun blk_execute_rq(rq->q, NULL, rq, true);
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun if (int_cmd->status) {
1021*4882a593Smuzhiyun dev_err(&dd->pdev->dev, "Internal command [%02X] failed %d\n",
1022*4882a593Smuzhiyun fis->command, int_cmd->status);
1023*4882a593Smuzhiyun rv = -EIO;
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun if (mtip_check_surprise_removal(dd->pdev) ||
1026*4882a593Smuzhiyun test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
1027*4882a593Smuzhiyun &dd->dd_flag)) {
1028*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
1029*4882a593Smuzhiyun "Internal command [%02X] wait returned due to SR\n",
1030*4882a593Smuzhiyun fis->command);
1031*4882a593Smuzhiyun rv = -ENXIO;
1032*4882a593Smuzhiyun goto exec_ic_exit;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun mtip_device_reset(dd); /* recover from timeout issue */
1035*4882a593Smuzhiyun rv = -EAGAIN;
1036*4882a593Smuzhiyun goto exec_ic_exit;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (readl(port->cmd_issue[MTIP_TAG_INDEX(MTIP_TAG_INTERNAL)])
1040*4882a593Smuzhiyun & (1 << MTIP_TAG_BIT(MTIP_TAG_INTERNAL))) {
1041*4882a593Smuzhiyun rv = -ENXIO;
1042*4882a593Smuzhiyun if (!test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)) {
1043*4882a593Smuzhiyun mtip_device_reset(dd);
1044*4882a593Smuzhiyun rv = -EAGAIN;
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun exec_ic_exit:
1048*4882a593Smuzhiyun /* Clear the allocated and active bits for the internal command. */
1049*4882a593Smuzhiyun blk_mq_free_request(rq);
1050*4882a593Smuzhiyun clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1051*4882a593Smuzhiyun if (rv >= 0 && mtip_pause_ncq(port, fis)) {
1052*4882a593Smuzhiyun /* NCQ paused */
1053*4882a593Smuzhiyun return rv;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun wake_up_interruptible(&port->svc_wait);
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun return rv;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun /*
1061*4882a593Smuzhiyun * Byte-swap ATA ID strings.
1062*4882a593Smuzhiyun *
1063*4882a593Smuzhiyun * ATA identify data contains strings in byte-swapped 16-bit words.
1064*4882a593Smuzhiyun * They must be swapped (on all architectures) to be usable as C strings.
1065*4882a593Smuzhiyun * This function swaps bytes in-place.
1066*4882a593Smuzhiyun *
1067*4882a593Smuzhiyun * @buf The buffer location of the string
1068*4882a593Smuzhiyun * @len The number of bytes to swap
1069*4882a593Smuzhiyun *
1070*4882a593Smuzhiyun * return value
1071*4882a593Smuzhiyun * None
1072*4882a593Smuzhiyun */
ata_swap_string(u16 * buf,unsigned int len)1073*4882a593Smuzhiyun static inline void ata_swap_string(u16 *buf, unsigned int len)
1074*4882a593Smuzhiyun {
1075*4882a593Smuzhiyun int i;
1076*4882a593Smuzhiyun for (i = 0; i < (len/2); i++)
1077*4882a593Smuzhiyun be16_to_cpus(&buf[i]);
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun
mtip_set_timeout(struct driver_data * dd,struct host_to_dev_fis * fis,unsigned int * timeout,u8 erasemode)1080*4882a593Smuzhiyun static void mtip_set_timeout(struct driver_data *dd,
1081*4882a593Smuzhiyun struct host_to_dev_fis *fis,
1082*4882a593Smuzhiyun unsigned int *timeout, u8 erasemode)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun switch (fis->command) {
1085*4882a593Smuzhiyun case ATA_CMD_DOWNLOAD_MICRO:
1086*4882a593Smuzhiyun *timeout = 120000; /* 2 minutes */
1087*4882a593Smuzhiyun break;
1088*4882a593Smuzhiyun case ATA_CMD_SEC_ERASE_UNIT:
1089*4882a593Smuzhiyun case 0xFC:
1090*4882a593Smuzhiyun if (erasemode)
1091*4882a593Smuzhiyun *timeout = ((*(dd->port->identify + 90) * 2) * 60000);
1092*4882a593Smuzhiyun else
1093*4882a593Smuzhiyun *timeout = ((*(dd->port->identify + 89) * 2) * 60000);
1094*4882a593Smuzhiyun break;
1095*4882a593Smuzhiyun case ATA_CMD_STANDBYNOW1:
1096*4882a593Smuzhiyun *timeout = 120000; /* 2 minutes */
1097*4882a593Smuzhiyun break;
1098*4882a593Smuzhiyun case 0xF7:
1099*4882a593Smuzhiyun case 0xFA:
1100*4882a593Smuzhiyun *timeout = 60000; /* 60 seconds */
1101*4882a593Smuzhiyun break;
1102*4882a593Smuzhiyun case ATA_CMD_SMART:
1103*4882a593Smuzhiyun *timeout = 15000; /* 15 seconds */
1104*4882a593Smuzhiyun break;
1105*4882a593Smuzhiyun default:
1106*4882a593Smuzhiyun *timeout = MTIP_IOCTL_CMD_TIMEOUT_MS;
1107*4882a593Smuzhiyun break;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun /*
1112*4882a593Smuzhiyun * Request the device identity information.
1113*4882a593Smuzhiyun *
1114*4882a593Smuzhiyun * If a user space buffer is not specified, i.e. is NULL, the
1115*4882a593Smuzhiyun * identify information is still read from the drive and placed
1116*4882a593Smuzhiyun * into the identify data buffer (@e port->identify) in the
1117*4882a593Smuzhiyun * port data structure.
1118*4882a593Smuzhiyun * When the identify buffer contains valid identify information @e
1119*4882a593Smuzhiyun * port->identify_valid is non-zero.
1120*4882a593Smuzhiyun *
1121*4882a593Smuzhiyun * @port Pointer to the port structure.
1122*4882a593Smuzhiyun * @user_buffer A user space buffer where the identify data should be
1123*4882a593Smuzhiyun * copied.
1124*4882a593Smuzhiyun *
1125*4882a593Smuzhiyun * return value
1126*4882a593Smuzhiyun * 0 Command completed successfully.
1127*4882a593Smuzhiyun * -EFAULT An error occurred while coping data to the user buffer.
1128*4882a593Smuzhiyun * -1 Command failed.
1129*4882a593Smuzhiyun */
mtip_get_identify(struct mtip_port * port,void __user * user_buffer)1130*4882a593Smuzhiyun static int mtip_get_identify(struct mtip_port *port, void __user *user_buffer)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun int rv = 0;
1133*4882a593Smuzhiyun struct host_to_dev_fis fis;
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
1136*4882a593Smuzhiyun return -EFAULT;
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun /* Build the FIS. */
1139*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1140*4882a593Smuzhiyun fis.type = 0x27;
1141*4882a593Smuzhiyun fis.opts = 1 << 7;
1142*4882a593Smuzhiyun fis.command = ATA_CMD_ID_ATA;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun /* Set the identify information as invalid. */
1145*4882a593Smuzhiyun port->identify_valid = 0;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun /* Clear the identify information. */
1148*4882a593Smuzhiyun memset(port->identify, 0, sizeof(u16) * ATA_ID_WORDS);
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun /* Execute the command. */
1151*4882a593Smuzhiyun if (mtip_exec_internal_command(port,
1152*4882a593Smuzhiyun &fis,
1153*4882a593Smuzhiyun 5,
1154*4882a593Smuzhiyun port->identify_dma,
1155*4882a593Smuzhiyun sizeof(u16) * ATA_ID_WORDS,
1156*4882a593Smuzhiyun 0,
1157*4882a593Smuzhiyun MTIP_INT_CMD_TIMEOUT_MS)
1158*4882a593Smuzhiyun < 0) {
1159*4882a593Smuzhiyun rv = -1;
1160*4882a593Smuzhiyun goto out;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun /*
1164*4882a593Smuzhiyun * Perform any necessary byte-swapping. Yes, the kernel does in fact
1165*4882a593Smuzhiyun * perform field-sensitive swapping on the string fields.
1166*4882a593Smuzhiyun * See the kernel use of ata_id_string() for proof of this.
1167*4882a593Smuzhiyun */
1168*4882a593Smuzhiyun #ifdef __LITTLE_ENDIAN
1169*4882a593Smuzhiyun ata_swap_string(port->identify + 27, 40); /* model string*/
1170*4882a593Smuzhiyun ata_swap_string(port->identify + 23, 8); /* firmware string*/
1171*4882a593Smuzhiyun ata_swap_string(port->identify + 10, 20); /* serial# string*/
1172*4882a593Smuzhiyun #else
1173*4882a593Smuzhiyun {
1174*4882a593Smuzhiyun int i;
1175*4882a593Smuzhiyun for (i = 0; i < ATA_ID_WORDS; i++)
1176*4882a593Smuzhiyun port->identify[i] = le16_to_cpu(port->identify[i]);
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun #endif
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun /* Check security locked state */
1181*4882a593Smuzhiyun if (port->identify[128] & 0x4)
1182*4882a593Smuzhiyun set_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
1183*4882a593Smuzhiyun else
1184*4882a593Smuzhiyun clear_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun /* Set the identify buffer as valid. */
1187*4882a593Smuzhiyun port->identify_valid = 1;
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun if (user_buffer) {
1190*4882a593Smuzhiyun if (copy_to_user(
1191*4882a593Smuzhiyun user_buffer,
1192*4882a593Smuzhiyun port->identify,
1193*4882a593Smuzhiyun ATA_ID_WORDS * sizeof(u16))) {
1194*4882a593Smuzhiyun rv = -EFAULT;
1195*4882a593Smuzhiyun goto out;
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun out:
1200*4882a593Smuzhiyun return rv;
1201*4882a593Smuzhiyun }
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun /*
1204*4882a593Smuzhiyun * Issue a standby immediate command to the device.
1205*4882a593Smuzhiyun *
1206*4882a593Smuzhiyun * @port Pointer to the port structure.
1207*4882a593Smuzhiyun *
1208*4882a593Smuzhiyun * return value
1209*4882a593Smuzhiyun * 0 Command was executed successfully.
1210*4882a593Smuzhiyun * -1 An error occurred while executing the command.
1211*4882a593Smuzhiyun */
mtip_standby_immediate(struct mtip_port * port)1212*4882a593Smuzhiyun static int mtip_standby_immediate(struct mtip_port *port)
1213*4882a593Smuzhiyun {
1214*4882a593Smuzhiyun int rv;
1215*4882a593Smuzhiyun struct host_to_dev_fis fis;
1216*4882a593Smuzhiyun unsigned long start;
1217*4882a593Smuzhiyun unsigned int timeout;
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun /* Build the FIS. */
1220*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1221*4882a593Smuzhiyun fis.type = 0x27;
1222*4882a593Smuzhiyun fis.opts = 1 << 7;
1223*4882a593Smuzhiyun fis.command = ATA_CMD_STANDBYNOW1;
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun mtip_set_timeout(port->dd, &fis, &timeout, 0);
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun start = jiffies;
1228*4882a593Smuzhiyun rv = mtip_exec_internal_command(port,
1229*4882a593Smuzhiyun &fis,
1230*4882a593Smuzhiyun 5,
1231*4882a593Smuzhiyun 0,
1232*4882a593Smuzhiyun 0,
1233*4882a593Smuzhiyun 0,
1234*4882a593Smuzhiyun timeout);
1235*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME "Time taken to complete standby cmd: %d ms\n",
1236*4882a593Smuzhiyun jiffies_to_msecs(jiffies - start));
1237*4882a593Smuzhiyun if (rv)
1238*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev,
1239*4882a593Smuzhiyun "STANDBY IMMEDIATE command failed.\n");
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun return rv;
1242*4882a593Smuzhiyun }
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun /*
1245*4882a593Smuzhiyun * Issue a READ LOG EXT command to the device.
1246*4882a593Smuzhiyun *
1247*4882a593Smuzhiyun * @port pointer to the port structure.
1248*4882a593Smuzhiyun * @page page number to fetch
1249*4882a593Smuzhiyun * @buffer pointer to buffer
1250*4882a593Smuzhiyun * @buffer_dma dma address corresponding to @buffer
1251*4882a593Smuzhiyun * @sectors page length to fetch, in sectors
1252*4882a593Smuzhiyun *
1253*4882a593Smuzhiyun * return value
1254*4882a593Smuzhiyun * @rv return value from mtip_exec_internal_command()
1255*4882a593Smuzhiyun */
mtip_read_log_page(struct mtip_port * port,u8 page,u16 * buffer,dma_addr_t buffer_dma,unsigned int sectors)1256*4882a593Smuzhiyun static int mtip_read_log_page(struct mtip_port *port, u8 page, u16 *buffer,
1257*4882a593Smuzhiyun dma_addr_t buffer_dma, unsigned int sectors)
1258*4882a593Smuzhiyun {
1259*4882a593Smuzhiyun struct host_to_dev_fis fis;
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1262*4882a593Smuzhiyun fis.type = 0x27;
1263*4882a593Smuzhiyun fis.opts = 1 << 7;
1264*4882a593Smuzhiyun fis.command = ATA_CMD_READ_LOG_EXT;
1265*4882a593Smuzhiyun fis.sect_count = sectors & 0xFF;
1266*4882a593Smuzhiyun fis.sect_cnt_ex = (sectors >> 8) & 0xFF;
1267*4882a593Smuzhiyun fis.lba_low = page;
1268*4882a593Smuzhiyun fis.lba_mid = 0;
1269*4882a593Smuzhiyun fis.device = ATA_DEVICE_OBS;
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun memset(buffer, 0, sectors * ATA_SECT_SIZE);
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun return mtip_exec_internal_command(port,
1274*4882a593Smuzhiyun &fis,
1275*4882a593Smuzhiyun 5,
1276*4882a593Smuzhiyun buffer_dma,
1277*4882a593Smuzhiyun sectors * ATA_SECT_SIZE,
1278*4882a593Smuzhiyun 0,
1279*4882a593Smuzhiyun MTIP_INT_CMD_TIMEOUT_MS);
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun /*
1283*4882a593Smuzhiyun * Issue a SMART READ DATA command to the device.
1284*4882a593Smuzhiyun *
1285*4882a593Smuzhiyun * @port pointer to the port structure.
1286*4882a593Smuzhiyun * @buffer pointer to buffer
1287*4882a593Smuzhiyun * @buffer_dma dma address corresponding to @buffer
1288*4882a593Smuzhiyun *
1289*4882a593Smuzhiyun * return value
1290*4882a593Smuzhiyun * @rv return value from mtip_exec_internal_command()
1291*4882a593Smuzhiyun */
mtip_get_smart_data(struct mtip_port * port,u8 * buffer,dma_addr_t buffer_dma)1292*4882a593Smuzhiyun static int mtip_get_smart_data(struct mtip_port *port, u8 *buffer,
1293*4882a593Smuzhiyun dma_addr_t buffer_dma)
1294*4882a593Smuzhiyun {
1295*4882a593Smuzhiyun struct host_to_dev_fis fis;
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1298*4882a593Smuzhiyun fis.type = 0x27;
1299*4882a593Smuzhiyun fis.opts = 1 << 7;
1300*4882a593Smuzhiyun fis.command = ATA_CMD_SMART;
1301*4882a593Smuzhiyun fis.features = 0xD0;
1302*4882a593Smuzhiyun fis.sect_count = 1;
1303*4882a593Smuzhiyun fis.lba_mid = 0x4F;
1304*4882a593Smuzhiyun fis.lba_hi = 0xC2;
1305*4882a593Smuzhiyun fis.device = ATA_DEVICE_OBS;
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun return mtip_exec_internal_command(port,
1308*4882a593Smuzhiyun &fis,
1309*4882a593Smuzhiyun 5,
1310*4882a593Smuzhiyun buffer_dma,
1311*4882a593Smuzhiyun ATA_SECT_SIZE,
1312*4882a593Smuzhiyun 0,
1313*4882a593Smuzhiyun 15000);
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun /*
1317*4882a593Smuzhiyun * Get the value of a smart attribute
1318*4882a593Smuzhiyun *
1319*4882a593Smuzhiyun * @port pointer to the port structure
1320*4882a593Smuzhiyun * @id attribute number
1321*4882a593Smuzhiyun * @attrib pointer to return attrib information corresponding to @id
1322*4882a593Smuzhiyun *
1323*4882a593Smuzhiyun * return value
1324*4882a593Smuzhiyun * -EINVAL NULL buffer passed or unsupported attribute @id.
1325*4882a593Smuzhiyun * -EPERM Identify data not valid, SMART not supported or not enabled
1326*4882a593Smuzhiyun */
mtip_get_smart_attr(struct mtip_port * port,unsigned int id,struct smart_attr * attrib)1327*4882a593Smuzhiyun static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
1328*4882a593Smuzhiyun struct smart_attr *attrib)
1329*4882a593Smuzhiyun {
1330*4882a593Smuzhiyun int rv, i;
1331*4882a593Smuzhiyun struct smart_attr *pattr;
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun if (!attrib)
1334*4882a593Smuzhiyun return -EINVAL;
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun if (!port->identify_valid) {
1337*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev, "IDENTIFY DATA not valid\n");
1338*4882a593Smuzhiyun return -EPERM;
1339*4882a593Smuzhiyun }
1340*4882a593Smuzhiyun if (!(port->identify[82] & 0x1)) {
1341*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev, "SMART not supported\n");
1342*4882a593Smuzhiyun return -EPERM;
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun if (!(port->identify[85] & 0x1)) {
1345*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev, "SMART not enabled\n");
1346*4882a593Smuzhiyun return -EPERM;
1347*4882a593Smuzhiyun }
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun memset(port->smart_buf, 0, ATA_SECT_SIZE);
1350*4882a593Smuzhiyun rv = mtip_get_smart_data(port, port->smart_buf, port->smart_buf_dma);
1351*4882a593Smuzhiyun if (rv) {
1352*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev, "Failed to ge SMART data\n");
1353*4882a593Smuzhiyun return rv;
1354*4882a593Smuzhiyun }
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun pattr = (struct smart_attr *)(port->smart_buf + 2);
1357*4882a593Smuzhiyun for (i = 0; i < 29; i++, pattr++)
1358*4882a593Smuzhiyun if (pattr->attr_id == id) {
1359*4882a593Smuzhiyun memcpy(attrib, pattr, sizeof(struct smart_attr));
1360*4882a593Smuzhiyun break;
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun if (i == 29) {
1364*4882a593Smuzhiyun dev_warn(&port->dd->pdev->dev,
1365*4882a593Smuzhiyun "Query for invalid SMART attribute ID\n");
1366*4882a593Smuzhiyun rv = -EINVAL;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun return rv;
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun /*
1373*4882a593Smuzhiyun * Get the drive capacity.
1374*4882a593Smuzhiyun *
1375*4882a593Smuzhiyun * @dd Pointer to the device data structure.
1376*4882a593Smuzhiyun * @sectors Pointer to the variable that will receive the sector count.
1377*4882a593Smuzhiyun *
1378*4882a593Smuzhiyun * return value
1379*4882a593Smuzhiyun * 1 Capacity was returned successfully.
1380*4882a593Smuzhiyun * 0 The identify information is invalid.
1381*4882a593Smuzhiyun */
mtip_hw_get_capacity(struct driver_data * dd,sector_t * sectors)1382*4882a593Smuzhiyun static bool mtip_hw_get_capacity(struct driver_data *dd, sector_t *sectors)
1383*4882a593Smuzhiyun {
1384*4882a593Smuzhiyun struct mtip_port *port = dd->port;
1385*4882a593Smuzhiyun u64 total, raw0, raw1, raw2, raw3;
1386*4882a593Smuzhiyun raw0 = port->identify[100];
1387*4882a593Smuzhiyun raw1 = port->identify[101];
1388*4882a593Smuzhiyun raw2 = port->identify[102];
1389*4882a593Smuzhiyun raw3 = port->identify[103];
1390*4882a593Smuzhiyun total = raw0 | raw1<<16 | raw2<<32 | raw3<<48;
1391*4882a593Smuzhiyun *sectors = total;
1392*4882a593Smuzhiyun return (bool) !!port->identify_valid;
1393*4882a593Smuzhiyun }
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun /*
1396*4882a593Smuzhiyun * Display the identify command data.
1397*4882a593Smuzhiyun *
1398*4882a593Smuzhiyun * @port Pointer to the port data structure.
1399*4882a593Smuzhiyun *
1400*4882a593Smuzhiyun * return value
1401*4882a593Smuzhiyun * None
1402*4882a593Smuzhiyun */
mtip_dump_identify(struct mtip_port * port)1403*4882a593Smuzhiyun static void mtip_dump_identify(struct mtip_port *port)
1404*4882a593Smuzhiyun {
1405*4882a593Smuzhiyun sector_t sectors;
1406*4882a593Smuzhiyun unsigned short revid;
1407*4882a593Smuzhiyun char cbuf[42];
1408*4882a593Smuzhiyun
1409*4882a593Smuzhiyun if (!port->identify_valid)
1410*4882a593Smuzhiyun return;
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun strlcpy(cbuf, (char *)(port->identify+10), 21);
1413*4882a593Smuzhiyun dev_info(&port->dd->pdev->dev,
1414*4882a593Smuzhiyun "Serial No.: %s\n", cbuf);
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun strlcpy(cbuf, (char *)(port->identify+23), 9);
1417*4882a593Smuzhiyun dev_info(&port->dd->pdev->dev,
1418*4882a593Smuzhiyun "Firmware Ver.: %s\n", cbuf);
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun strlcpy(cbuf, (char *)(port->identify+27), 41);
1421*4882a593Smuzhiyun dev_info(&port->dd->pdev->dev, "Model: %s\n", cbuf);
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun dev_info(&port->dd->pdev->dev, "Security: %04x %s\n",
1424*4882a593Smuzhiyun port->identify[128],
1425*4882a593Smuzhiyun port->identify[128] & 0x4 ? "(LOCKED)" : "");
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun if (mtip_hw_get_capacity(port->dd, §ors))
1428*4882a593Smuzhiyun dev_info(&port->dd->pdev->dev,
1429*4882a593Smuzhiyun "Capacity: %llu sectors (%llu MB)\n",
1430*4882a593Smuzhiyun (u64)sectors,
1431*4882a593Smuzhiyun ((u64)sectors) * ATA_SECT_SIZE >> 20);
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun pci_read_config_word(port->dd->pdev, PCI_REVISION_ID, &revid);
1434*4882a593Smuzhiyun switch (revid & 0xFF) {
1435*4882a593Smuzhiyun case 0x1:
1436*4882a593Smuzhiyun strlcpy(cbuf, "A0", 3);
1437*4882a593Smuzhiyun break;
1438*4882a593Smuzhiyun case 0x3:
1439*4882a593Smuzhiyun strlcpy(cbuf, "A2", 3);
1440*4882a593Smuzhiyun break;
1441*4882a593Smuzhiyun default:
1442*4882a593Smuzhiyun strlcpy(cbuf, "?", 2);
1443*4882a593Smuzhiyun break;
1444*4882a593Smuzhiyun }
1445*4882a593Smuzhiyun dev_info(&port->dd->pdev->dev,
1446*4882a593Smuzhiyun "Card Type: %s\n", cbuf);
1447*4882a593Smuzhiyun }
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun /*
1450*4882a593Smuzhiyun * Map the commands scatter list into the command table.
1451*4882a593Smuzhiyun *
1452*4882a593Smuzhiyun * @command Pointer to the command.
1453*4882a593Smuzhiyun * @nents Number of scatter list entries.
1454*4882a593Smuzhiyun *
1455*4882a593Smuzhiyun * return value
1456*4882a593Smuzhiyun * None
1457*4882a593Smuzhiyun */
fill_command_sg(struct driver_data * dd,struct mtip_cmd * command,int nents)1458*4882a593Smuzhiyun static inline void fill_command_sg(struct driver_data *dd,
1459*4882a593Smuzhiyun struct mtip_cmd *command,
1460*4882a593Smuzhiyun int nents)
1461*4882a593Smuzhiyun {
1462*4882a593Smuzhiyun int n;
1463*4882a593Smuzhiyun unsigned int dma_len;
1464*4882a593Smuzhiyun struct mtip_cmd_sg *command_sg;
1465*4882a593Smuzhiyun struct scatterlist *sg;
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun command_sg = command->command + AHCI_CMD_TBL_HDR_SZ;
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun for_each_sg(command->sg, sg, nents, n) {
1470*4882a593Smuzhiyun dma_len = sg_dma_len(sg);
1471*4882a593Smuzhiyun if (dma_len > 0x400000)
1472*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
1473*4882a593Smuzhiyun "DMA segment length truncated\n");
1474*4882a593Smuzhiyun command_sg->info = cpu_to_le32((dma_len-1) & 0x3FFFFF);
1475*4882a593Smuzhiyun command_sg->dba = cpu_to_le32(sg_dma_address(sg));
1476*4882a593Smuzhiyun command_sg->dba_upper =
1477*4882a593Smuzhiyun cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
1478*4882a593Smuzhiyun command_sg++;
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun }
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun /*
1483*4882a593Smuzhiyun * @brief Execute a drive command.
1484*4882a593Smuzhiyun *
1485*4882a593Smuzhiyun * return value 0 The command completed successfully.
1486*4882a593Smuzhiyun * return value -1 An error occurred while executing the command.
1487*4882a593Smuzhiyun */
exec_drive_task(struct mtip_port * port,u8 * command)1488*4882a593Smuzhiyun static int exec_drive_task(struct mtip_port *port, u8 *command)
1489*4882a593Smuzhiyun {
1490*4882a593Smuzhiyun struct host_to_dev_fis fis;
1491*4882a593Smuzhiyun struct host_to_dev_fis *reply = (port->rxfis + RX_FIS_D2H_REG);
1492*4882a593Smuzhiyun unsigned int to;
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun /* Build the FIS. */
1495*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1496*4882a593Smuzhiyun fis.type = 0x27;
1497*4882a593Smuzhiyun fis.opts = 1 << 7;
1498*4882a593Smuzhiyun fis.command = command[0];
1499*4882a593Smuzhiyun fis.features = command[1];
1500*4882a593Smuzhiyun fis.sect_count = command[2];
1501*4882a593Smuzhiyun fis.sector = command[3];
1502*4882a593Smuzhiyun fis.cyl_low = command[4];
1503*4882a593Smuzhiyun fis.cyl_hi = command[5];
1504*4882a593Smuzhiyun fis.device = command[6] & ~0x10; /* Clear the dev bit*/
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun mtip_set_timeout(port->dd, &fis, &to, 0);
1507*4882a593Smuzhiyun
1508*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME " %s: User Command: cmd %x, feat %x, nsect %x, sect %x, lcyl %x, hcyl %x, sel %x\n",
1509*4882a593Smuzhiyun __func__,
1510*4882a593Smuzhiyun command[0],
1511*4882a593Smuzhiyun command[1],
1512*4882a593Smuzhiyun command[2],
1513*4882a593Smuzhiyun command[3],
1514*4882a593Smuzhiyun command[4],
1515*4882a593Smuzhiyun command[5],
1516*4882a593Smuzhiyun command[6]);
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun /* Execute the command. */
1519*4882a593Smuzhiyun if (mtip_exec_internal_command(port,
1520*4882a593Smuzhiyun &fis,
1521*4882a593Smuzhiyun 5,
1522*4882a593Smuzhiyun 0,
1523*4882a593Smuzhiyun 0,
1524*4882a593Smuzhiyun 0,
1525*4882a593Smuzhiyun to) < 0) {
1526*4882a593Smuzhiyun return -1;
1527*4882a593Smuzhiyun }
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun command[0] = reply->command; /* Status*/
1530*4882a593Smuzhiyun command[1] = reply->features; /* Error*/
1531*4882a593Smuzhiyun command[4] = reply->cyl_low;
1532*4882a593Smuzhiyun command[5] = reply->cyl_hi;
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME " %s: Completion Status: stat %x, err %x , cyl_lo %x cyl_hi %x\n",
1535*4882a593Smuzhiyun __func__,
1536*4882a593Smuzhiyun command[0],
1537*4882a593Smuzhiyun command[1],
1538*4882a593Smuzhiyun command[4],
1539*4882a593Smuzhiyun command[5]);
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun return 0;
1542*4882a593Smuzhiyun }
1543*4882a593Smuzhiyun
1544*4882a593Smuzhiyun /*
1545*4882a593Smuzhiyun * @brief Execute a drive command.
1546*4882a593Smuzhiyun *
1547*4882a593Smuzhiyun * @param port Pointer to the port data structure.
1548*4882a593Smuzhiyun * @param command Pointer to the user specified command parameters.
1549*4882a593Smuzhiyun * @param user_buffer Pointer to the user space buffer where read sector
1550*4882a593Smuzhiyun * data should be copied.
1551*4882a593Smuzhiyun *
1552*4882a593Smuzhiyun * return value 0 The command completed successfully.
1553*4882a593Smuzhiyun * return value -EFAULT An error occurred while copying the completion
1554*4882a593Smuzhiyun * data to the user space buffer.
1555*4882a593Smuzhiyun * return value -1 An error occurred while executing the command.
1556*4882a593Smuzhiyun */
exec_drive_command(struct mtip_port * port,u8 * command,void __user * user_buffer)1557*4882a593Smuzhiyun static int exec_drive_command(struct mtip_port *port, u8 *command,
1558*4882a593Smuzhiyun void __user *user_buffer)
1559*4882a593Smuzhiyun {
1560*4882a593Smuzhiyun struct host_to_dev_fis fis;
1561*4882a593Smuzhiyun struct host_to_dev_fis *reply;
1562*4882a593Smuzhiyun u8 *buf = NULL;
1563*4882a593Smuzhiyun dma_addr_t dma_addr = 0;
1564*4882a593Smuzhiyun int rv = 0, xfer_sz = command[3];
1565*4882a593Smuzhiyun unsigned int to;
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun if (xfer_sz) {
1568*4882a593Smuzhiyun if (!user_buffer)
1569*4882a593Smuzhiyun return -EFAULT;
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun buf = dma_alloc_coherent(&port->dd->pdev->dev,
1572*4882a593Smuzhiyun ATA_SECT_SIZE * xfer_sz,
1573*4882a593Smuzhiyun &dma_addr,
1574*4882a593Smuzhiyun GFP_KERNEL);
1575*4882a593Smuzhiyun if (!buf) {
1576*4882a593Smuzhiyun dev_err(&port->dd->pdev->dev,
1577*4882a593Smuzhiyun "Memory allocation failed (%d bytes)\n",
1578*4882a593Smuzhiyun ATA_SECT_SIZE * xfer_sz);
1579*4882a593Smuzhiyun return -ENOMEM;
1580*4882a593Smuzhiyun }
1581*4882a593Smuzhiyun }
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun /* Build the FIS. */
1584*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1585*4882a593Smuzhiyun fis.type = 0x27;
1586*4882a593Smuzhiyun fis.opts = 1 << 7;
1587*4882a593Smuzhiyun fis.command = command[0];
1588*4882a593Smuzhiyun fis.features = command[2];
1589*4882a593Smuzhiyun fis.sect_count = command[3];
1590*4882a593Smuzhiyun if (fis.command == ATA_CMD_SMART) {
1591*4882a593Smuzhiyun fis.sector = command[1];
1592*4882a593Smuzhiyun fis.cyl_low = 0x4F;
1593*4882a593Smuzhiyun fis.cyl_hi = 0xC2;
1594*4882a593Smuzhiyun }
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun mtip_set_timeout(port->dd, &fis, &to, 0);
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun if (xfer_sz)
1599*4882a593Smuzhiyun reply = (port->rxfis + RX_FIS_PIO_SETUP);
1600*4882a593Smuzhiyun else
1601*4882a593Smuzhiyun reply = (port->rxfis + RX_FIS_D2H_REG);
1602*4882a593Smuzhiyun
1603*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME
1604*4882a593Smuzhiyun " %s: User Command: cmd %x, sect %x, "
1605*4882a593Smuzhiyun "feat %x, sectcnt %x\n",
1606*4882a593Smuzhiyun __func__,
1607*4882a593Smuzhiyun command[0],
1608*4882a593Smuzhiyun command[1],
1609*4882a593Smuzhiyun command[2],
1610*4882a593Smuzhiyun command[3]);
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun /* Execute the command. */
1613*4882a593Smuzhiyun if (mtip_exec_internal_command(port,
1614*4882a593Smuzhiyun &fis,
1615*4882a593Smuzhiyun 5,
1616*4882a593Smuzhiyun (xfer_sz ? dma_addr : 0),
1617*4882a593Smuzhiyun (xfer_sz ? ATA_SECT_SIZE * xfer_sz : 0),
1618*4882a593Smuzhiyun 0,
1619*4882a593Smuzhiyun to)
1620*4882a593Smuzhiyun < 0) {
1621*4882a593Smuzhiyun rv = -EFAULT;
1622*4882a593Smuzhiyun goto exit_drive_command;
1623*4882a593Smuzhiyun }
1624*4882a593Smuzhiyun
1625*4882a593Smuzhiyun /* Collect the completion status. */
1626*4882a593Smuzhiyun command[0] = reply->command; /* Status*/
1627*4882a593Smuzhiyun command[1] = reply->features; /* Error*/
1628*4882a593Smuzhiyun command[2] = reply->sect_count;
1629*4882a593Smuzhiyun
1630*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME
1631*4882a593Smuzhiyun " %s: Completion Status: stat %x, "
1632*4882a593Smuzhiyun "err %x, nsect %x\n",
1633*4882a593Smuzhiyun __func__,
1634*4882a593Smuzhiyun command[0],
1635*4882a593Smuzhiyun command[1],
1636*4882a593Smuzhiyun command[2]);
1637*4882a593Smuzhiyun
1638*4882a593Smuzhiyun if (xfer_sz) {
1639*4882a593Smuzhiyun if (copy_to_user(user_buffer,
1640*4882a593Smuzhiyun buf,
1641*4882a593Smuzhiyun ATA_SECT_SIZE * command[3])) {
1642*4882a593Smuzhiyun rv = -EFAULT;
1643*4882a593Smuzhiyun goto exit_drive_command;
1644*4882a593Smuzhiyun }
1645*4882a593Smuzhiyun }
1646*4882a593Smuzhiyun exit_drive_command:
1647*4882a593Smuzhiyun if (buf)
1648*4882a593Smuzhiyun dma_free_coherent(&port->dd->pdev->dev,
1649*4882a593Smuzhiyun ATA_SECT_SIZE * xfer_sz, buf, dma_addr);
1650*4882a593Smuzhiyun return rv;
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun
1653*4882a593Smuzhiyun /*
1654*4882a593Smuzhiyun * Indicates whether a command has a single sector payload.
1655*4882a593Smuzhiyun *
1656*4882a593Smuzhiyun * @command passed to the device to perform the certain event.
1657*4882a593Smuzhiyun * @features passed to the device to perform the certain event.
1658*4882a593Smuzhiyun *
1659*4882a593Smuzhiyun * return value
1660*4882a593Smuzhiyun * 1 command is one that always has a single sector payload,
1661*4882a593Smuzhiyun * regardless of the value in the Sector Count field.
1662*4882a593Smuzhiyun * 0 otherwise
1663*4882a593Smuzhiyun *
1664*4882a593Smuzhiyun */
implicit_sector(unsigned char command,unsigned char features)1665*4882a593Smuzhiyun static unsigned int implicit_sector(unsigned char command,
1666*4882a593Smuzhiyun unsigned char features)
1667*4882a593Smuzhiyun {
1668*4882a593Smuzhiyun unsigned int rv = 0;
1669*4882a593Smuzhiyun
1670*4882a593Smuzhiyun /* list of commands that have an implicit sector count of 1 */
1671*4882a593Smuzhiyun switch (command) {
1672*4882a593Smuzhiyun case ATA_CMD_SEC_SET_PASS:
1673*4882a593Smuzhiyun case ATA_CMD_SEC_UNLOCK:
1674*4882a593Smuzhiyun case ATA_CMD_SEC_ERASE_PREP:
1675*4882a593Smuzhiyun case ATA_CMD_SEC_ERASE_UNIT:
1676*4882a593Smuzhiyun case ATA_CMD_SEC_FREEZE_LOCK:
1677*4882a593Smuzhiyun case ATA_CMD_SEC_DISABLE_PASS:
1678*4882a593Smuzhiyun case ATA_CMD_PMP_READ:
1679*4882a593Smuzhiyun case ATA_CMD_PMP_WRITE:
1680*4882a593Smuzhiyun rv = 1;
1681*4882a593Smuzhiyun break;
1682*4882a593Smuzhiyun case ATA_CMD_SET_MAX:
1683*4882a593Smuzhiyun if (features == ATA_SET_MAX_UNLOCK)
1684*4882a593Smuzhiyun rv = 1;
1685*4882a593Smuzhiyun break;
1686*4882a593Smuzhiyun case ATA_CMD_SMART:
1687*4882a593Smuzhiyun if ((features == ATA_SMART_READ_VALUES) ||
1688*4882a593Smuzhiyun (features == ATA_SMART_READ_THRESHOLDS))
1689*4882a593Smuzhiyun rv = 1;
1690*4882a593Smuzhiyun break;
1691*4882a593Smuzhiyun case ATA_CMD_CONF_OVERLAY:
1692*4882a593Smuzhiyun if ((features == ATA_DCO_IDENTIFY) ||
1693*4882a593Smuzhiyun (features == ATA_DCO_SET))
1694*4882a593Smuzhiyun rv = 1;
1695*4882a593Smuzhiyun break;
1696*4882a593Smuzhiyun }
1697*4882a593Smuzhiyun return rv;
1698*4882a593Smuzhiyun }
1699*4882a593Smuzhiyun
1700*4882a593Smuzhiyun /*
1701*4882a593Smuzhiyun * Executes a taskfile
1702*4882a593Smuzhiyun * See ide_taskfile_ioctl() for derivation
1703*4882a593Smuzhiyun */
exec_drive_taskfile(struct driver_data * dd,void __user * buf,ide_task_request_t * req_task,int outtotal)1704*4882a593Smuzhiyun static int exec_drive_taskfile(struct driver_data *dd,
1705*4882a593Smuzhiyun void __user *buf,
1706*4882a593Smuzhiyun ide_task_request_t *req_task,
1707*4882a593Smuzhiyun int outtotal)
1708*4882a593Smuzhiyun {
1709*4882a593Smuzhiyun struct host_to_dev_fis fis;
1710*4882a593Smuzhiyun struct host_to_dev_fis *reply;
1711*4882a593Smuzhiyun u8 *outbuf = NULL;
1712*4882a593Smuzhiyun u8 *inbuf = NULL;
1713*4882a593Smuzhiyun dma_addr_t outbuf_dma = 0;
1714*4882a593Smuzhiyun dma_addr_t inbuf_dma = 0;
1715*4882a593Smuzhiyun dma_addr_t dma_buffer = 0;
1716*4882a593Smuzhiyun int err = 0;
1717*4882a593Smuzhiyun unsigned int taskin = 0;
1718*4882a593Smuzhiyun unsigned int taskout = 0;
1719*4882a593Smuzhiyun u8 nsect = 0;
1720*4882a593Smuzhiyun unsigned int timeout;
1721*4882a593Smuzhiyun unsigned int force_single_sector;
1722*4882a593Smuzhiyun unsigned int transfer_size;
1723*4882a593Smuzhiyun unsigned long task_file_data;
1724*4882a593Smuzhiyun int intotal = outtotal + req_task->out_size;
1725*4882a593Smuzhiyun int erasemode = 0;
1726*4882a593Smuzhiyun
1727*4882a593Smuzhiyun taskout = req_task->out_size;
1728*4882a593Smuzhiyun taskin = req_task->in_size;
1729*4882a593Smuzhiyun /* 130560 = 512 * 0xFF*/
1730*4882a593Smuzhiyun if (taskin > 130560 || taskout > 130560)
1731*4882a593Smuzhiyun return -EINVAL;
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun if (taskout) {
1734*4882a593Smuzhiyun outbuf = memdup_user(buf + outtotal, taskout);
1735*4882a593Smuzhiyun if (IS_ERR(outbuf))
1736*4882a593Smuzhiyun return PTR_ERR(outbuf);
1737*4882a593Smuzhiyun
1738*4882a593Smuzhiyun outbuf_dma = dma_map_single(&dd->pdev->dev, outbuf,
1739*4882a593Smuzhiyun taskout, DMA_TO_DEVICE);
1740*4882a593Smuzhiyun if (dma_mapping_error(&dd->pdev->dev, outbuf_dma)) {
1741*4882a593Smuzhiyun err = -ENOMEM;
1742*4882a593Smuzhiyun goto abort;
1743*4882a593Smuzhiyun }
1744*4882a593Smuzhiyun dma_buffer = outbuf_dma;
1745*4882a593Smuzhiyun }
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun if (taskin) {
1748*4882a593Smuzhiyun inbuf = memdup_user(buf + intotal, taskin);
1749*4882a593Smuzhiyun if (IS_ERR(inbuf)) {
1750*4882a593Smuzhiyun err = PTR_ERR(inbuf);
1751*4882a593Smuzhiyun inbuf = NULL;
1752*4882a593Smuzhiyun goto abort;
1753*4882a593Smuzhiyun }
1754*4882a593Smuzhiyun inbuf_dma = dma_map_single(&dd->pdev->dev, inbuf,
1755*4882a593Smuzhiyun taskin, DMA_FROM_DEVICE);
1756*4882a593Smuzhiyun if (dma_mapping_error(&dd->pdev->dev, inbuf_dma)) {
1757*4882a593Smuzhiyun err = -ENOMEM;
1758*4882a593Smuzhiyun goto abort;
1759*4882a593Smuzhiyun }
1760*4882a593Smuzhiyun dma_buffer = inbuf_dma;
1761*4882a593Smuzhiyun }
1762*4882a593Smuzhiyun
1763*4882a593Smuzhiyun /* only supports PIO and non-data commands from this ioctl. */
1764*4882a593Smuzhiyun switch (req_task->data_phase) {
1765*4882a593Smuzhiyun case TASKFILE_OUT:
1766*4882a593Smuzhiyun nsect = taskout / ATA_SECT_SIZE;
1767*4882a593Smuzhiyun reply = (dd->port->rxfis + RX_FIS_PIO_SETUP);
1768*4882a593Smuzhiyun break;
1769*4882a593Smuzhiyun case TASKFILE_IN:
1770*4882a593Smuzhiyun reply = (dd->port->rxfis + RX_FIS_PIO_SETUP);
1771*4882a593Smuzhiyun break;
1772*4882a593Smuzhiyun case TASKFILE_NO_DATA:
1773*4882a593Smuzhiyun reply = (dd->port->rxfis + RX_FIS_D2H_REG);
1774*4882a593Smuzhiyun break;
1775*4882a593Smuzhiyun default:
1776*4882a593Smuzhiyun err = -EINVAL;
1777*4882a593Smuzhiyun goto abort;
1778*4882a593Smuzhiyun }
1779*4882a593Smuzhiyun
1780*4882a593Smuzhiyun /* Build the FIS. */
1781*4882a593Smuzhiyun memset(&fis, 0, sizeof(struct host_to_dev_fis));
1782*4882a593Smuzhiyun
1783*4882a593Smuzhiyun fis.type = 0x27;
1784*4882a593Smuzhiyun fis.opts = 1 << 7;
1785*4882a593Smuzhiyun fis.command = req_task->io_ports[7];
1786*4882a593Smuzhiyun fis.features = req_task->io_ports[1];
1787*4882a593Smuzhiyun fis.sect_count = req_task->io_ports[2];
1788*4882a593Smuzhiyun fis.lba_low = req_task->io_ports[3];
1789*4882a593Smuzhiyun fis.lba_mid = req_task->io_ports[4];
1790*4882a593Smuzhiyun fis.lba_hi = req_task->io_ports[5];
1791*4882a593Smuzhiyun /* Clear the dev bit*/
1792*4882a593Smuzhiyun fis.device = req_task->io_ports[6] & ~0x10;
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun if ((req_task->in_flags.all == 0) && (req_task->out_flags.all & 1)) {
1795*4882a593Smuzhiyun req_task->in_flags.all =
1796*4882a593Smuzhiyun IDE_TASKFILE_STD_IN_FLAGS |
1797*4882a593Smuzhiyun (IDE_HOB_STD_IN_FLAGS << 8);
1798*4882a593Smuzhiyun fis.lba_low_ex = req_task->hob_ports[3];
1799*4882a593Smuzhiyun fis.lba_mid_ex = req_task->hob_ports[4];
1800*4882a593Smuzhiyun fis.lba_hi_ex = req_task->hob_ports[5];
1801*4882a593Smuzhiyun fis.features_ex = req_task->hob_ports[1];
1802*4882a593Smuzhiyun fis.sect_cnt_ex = req_task->hob_ports[2];
1803*4882a593Smuzhiyun
1804*4882a593Smuzhiyun } else {
1805*4882a593Smuzhiyun req_task->in_flags.all = IDE_TASKFILE_STD_IN_FLAGS;
1806*4882a593Smuzhiyun }
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun force_single_sector = implicit_sector(fis.command, fis.features);
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun if ((taskin || taskout) && (!fis.sect_count)) {
1811*4882a593Smuzhiyun if (nsect)
1812*4882a593Smuzhiyun fis.sect_count = nsect;
1813*4882a593Smuzhiyun else {
1814*4882a593Smuzhiyun if (!force_single_sector) {
1815*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
1816*4882a593Smuzhiyun "data movement but "
1817*4882a593Smuzhiyun "sect_count is 0\n");
1818*4882a593Smuzhiyun err = -EINVAL;
1819*4882a593Smuzhiyun goto abort;
1820*4882a593Smuzhiyun }
1821*4882a593Smuzhiyun }
1822*4882a593Smuzhiyun }
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME
1825*4882a593Smuzhiyun " %s: cmd %x, feat %x, nsect %x,"
1826*4882a593Smuzhiyun " sect/lbal %x, lcyl/lbam %x, hcyl/lbah %x,"
1827*4882a593Smuzhiyun " head/dev %x\n",
1828*4882a593Smuzhiyun __func__,
1829*4882a593Smuzhiyun fis.command,
1830*4882a593Smuzhiyun fis.features,
1831*4882a593Smuzhiyun fis.sect_count,
1832*4882a593Smuzhiyun fis.lba_low,
1833*4882a593Smuzhiyun fis.lba_mid,
1834*4882a593Smuzhiyun fis.lba_hi,
1835*4882a593Smuzhiyun fis.device);
1836*4882a593Smuzhiyun
1837*4882a593Smuzhiyun /* check for erase mode support during secure erase.*/
1838*4882a593Smuzhiyun if ((fis.command == ATA_CMD_SEC_ERASE_UNIT) && outbuf &&
1839*4882a593Smuzhiyun (outbuf[0] & MTIP_SEC_ERASE_MODE)) {
1840*4882a593Smuzhiyun erasemode = 1;
1841*4882a593Smuzhiyun }
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun mtip_set_timeout(dd, &fis, &timeout, erasemode);
1844*4882a593Smuzhiyun
1845*4882a593Smuzhiyun /* Determine the correct transfer size.*/
1846*4882a593Smuzhiyun if (force_single_sector)
1847*4882a593Smuzhiyun transfer_size = ATA_SECT_SIZE;
1848*4882a593Smuzhiyun else
1849*4882a593Smuzhiyun transfer_size = ATA_SECT_SIZE * fis.sect_count;
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun /* Execute the command.*/
1852*4882a593Smuzhiyun if (mtip_exec_internal_command(dd->port,
1853*4882a593Smuzhiyun &fis,
1854*4882a593Smuzhiyun 5,
1855*4882a593Smuzhiyun dma_buffer,
1856*4882a593Smuzhiyun transfer_size,
1857*4882a593Smuzhiyun 0,
1858*4882a593Smuzhiyun timeout) < 0) {
1859*4882a593Smuzhiyun err = -EIO;
1860*4882a593Smuzhiyun goto abort;
1861*4882a593Smuzhiyun }
1862*4882a593Smuzhiyun
1863*4882a593Smuzhiyun task_file_data = readl(dd->port->mmio+PORT_TFDATA);
1864*4882a593Smuzhiyun
1865*4882a593Smuzhiyun if ((req_task->data_phase == TASKFILE_IN) && !(task_file_data & 1)) {
1866*4882a593Smuzhiyun reply = dd->port->rxfis + RX_FIS_PIO_SETUP;
1867*4882a593Smuzhiyun req_task->io_ports[7] = reply->control;
1868*4882a593Smuzhiyun } else {
1869*4882a593Smuzhiyun reply = dd->port->rxfis + RX_FIS_D2H_REG;
1870*4882a593Smuzhiyun req_task->io_ports[7] = reply->command;
1871*4882a593Smuzhiyun }
1872*4882a593Smuzhiyun
1873*4882a593Smuzhiyun /* reclaim the DMA buffers.*/
1874*4882a593Smuzhiyun if (inbuf_dma)
1875*4882a593Smuzhiyun dma_unmap_single(&dd->pdev->dev, inbuf_dma, taskin,
1876*4882a593Smuzhiyun DMA_FROM_DEVICE);
1877*4882a593Smuzhiyun if (outbuf_dma)
1878*4882a593Smuzhiyun dma_unmap_single(&dd->pdev->dev, outbuf_dma, taskout,
1879*4882a593Smuzhiyun DMA_TO_DEVICE);
1880*4882a593Smuzhiyun inbuf_dma = 0;
1881*4882a593Smuzhiyun outbuf_dma = 0;
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun /* return the ATA registers to the caller.*/
1884*4882a593Smuzhiyun req_task->io_ports[1] = reply->features;
1885*4882a593Smuzhiyun req_task->io_ports[2] = reply->sect_count;
1886*4882a593Smuzhiyun req_task->io_ports[3] = reply->lba_low;
1887*4882a593Smuzhiyun req_task->io_ports[4] = reply->lba_mid;
1888*4882a593Smuzhiyun req_task->io_ports[5] = reply->lba_hi;
1889*4882a593Smuzhiyun req_task->io_ports[6] = reply->device;
1890*4882a593Smuzhiyun
1891*4882a593Smuzhiyun if (req_task->out_flags.all & 1) {
1892*4882a593Smuzhiyun
1893*4882a593Smuzhiyun req_task->hob_ports[3] = reply->lba_low_ex;
1894*4882a593Smuzhiyun req_task->hob_ports[4] = reply->lba_mid_ex;
1895*4882a593Smuzhiyun req_task->hob_ports[5] = reply->lba_hi_ex;
1896*4882a593Smuzhiyun req_task->hob_ports[1] = reply->features_ex;
1897*4882a593Smuzhiyun req_task->hob_ports[2] = reply->sect_cnt_ex;
1898*4882a593Smuzhiyun }
1899*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME
1900*4882a593Smuzhiyun " %s: Completion: stat %x,"
1901*4882a593Smuzhiyun "err %x, sect_cnt %x, lbalo %x,"
1902*4882a593Smuzhiyun "lbamid %x, lbahi %x, dev %x\n",
1903*4882a593Smuzhiyun __func__,
1904*4882a593Smuzhiyun req_task->io_ports[7],
1905*4882a593Smuzhiyun req_task->io_ports[1],
1906*4882a593Smuzhiyun req_task->io_ports[2],
1907*4882a593Smuzhiyun req_task->io_ports[3],
1908*4882a593Smuzhiyun req_task->io_ports[4],
1909*4882a593Smuzhiyun req_task->io_ports[5],
1910*4882a593Smuzhiyun req_task->io_ports[6]);
1911*4882a593Smuzhiyun
1912*4882a593Smuzhiyun if (taskout) {
1913*4882a593Smuzhiyun if (copy_to_user(buf + outtotal, outbuf, taskout)) {
1914*4882a593Smuzhiyun err = -EFAULT;
1915*4882a593Smuzhiyun goto abort;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun }
1918*4882a593Smuzhiyun if (taskin) {
1919*4882a593Smuzhiyun if (copy_to_user(buf + intotal, inbuf, taskin)) {
1920*4882a593Smuzhiyun err = -EFAULT;
1921*4882a593Smuzhiyun goto abort;
1922*4882a593Smuzhiyun }
1923*4882a593Smuzhiyun }
1924*4882a593Smuzhiyun abort:
1925*4882a593Smuzhiyun if (inbuf_dma)
1926*4882a593Smuzhiyun dma_unmap_single(&dd->pdev->dev, inbuf_dma, taskin,
1927*4882a593Smuzhiyun DMA_FROM_DEVICE);
1928*4882a593Smuzhiyun if (outbuf_dma)
1929*4882a593Smuzhiyun dma_unmap_single(&dd->pdev->dev, outbuf_dma, taskout,
1930*4882a593Smuzhiyun DMA_TO_DEVICE);
1931*4882a593Smuzhiyun kfree(outbuf);
1932*4882a593Smuzhiyun kfree(inbuf);
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun return err;
1935*4882a593Smuzhiyun }
1936*4882a593Smuzhiyun
1937*4882a593Smuzhiyun /*
1938*4882a593Smuzhiyun * Handle IOCTL calls from the Block Layer.
1939*4882a593Smuzhiyun *
1940*4882a593Smuzhiyun * This function is called by the Block Layer when it receives an IOCTL
1941*4882a593Smuzhiyun * command that it does not understand. If the IOCTL command is not supported
1942*4882a593Smuzhiyun * this function returns -ENOTTY.
1943*4882a593Smuzhiyun *
1944*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
1945*4882a593Smuzhiyun * @cmd IOCTL command passed from the Block Layer.
1946*4882a593Smuzhiyun * @arg IOCTL argument passed from the Block Layer.
1947*4882a593Smuzhiyun *
1948*4882a593Smuzhiyun * return value
1949*4882a593Smuzhiyun * 0 The IOCTL completed successfully.
1950*4882a593Smuzhiyun * -ENOTTY The specified command is not supported.
1951*4882a593Smuzhiyun * -EFAULT An error occurred copying data to a user space buffer.
1952*4882a593Smuzhiyun * -EIO An error occurred while executing the command.
1953*4882a593Smuzhiyun */
mtip_hw_ioctl(struct driver_data * dd,unsigned int cmd,unsigned long arg)1954*4882a593Smuzhiyun static int mtip_hw_ioctl(struct driver_data *dd, unsigned int cmd,
1955*4882a593Smuzhiyun unsigned long arg)
1956*4882a593Smuzhiyun {
1957*4882a593Smuzhiyun switch (cmd) {
1958*4882a593Smuzhiyun case HDIO_GET_IDENTITY:
1959*4882a593Smuzhiyun {
1960*4882a593Smuzhiyun if (copy_to_user((void __user *)arg, dd->port->identify,
1961*4882a593Smuzhiyun sizeof(u16) * ATA_ID_WORDS))
1962*4882a593Smuzhiyun return -EFAULT;
1963*4882a593Smuzhiyun break;
1964*4882a593Smuzhiyun }
1965*4882a593Smuzhiyun case HDIO_DRIVE_CMD:
1966*4882a593Smuzhiyun {
1967*4882a593Smuzhiyun u8 drive_command[4];
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun /* Copy the user command info to our buffer. */
1970*4882a593Smuzhiyun if (copy_from_user(drive_command,
1971*4882a593Smuzhiyun (void __user *) arg,
1972*4882a593Smuzhiyun sizeof(drive_command)))
1973*4882a593Smuzhiyun return -EFAULT;
1974*4882a593Smuzhiyun
1975*4882a593Smuzhiyun /* Execute the drive command. */
1976*4882a593Smuzhiyun if (exec_drive_command(dd->port,
1977*4882a593Smuzhiyun drive_command,
1978*4882a593Smuzhiyun (void __user *) (arg+4)))
1979*4882a593Smuzhiyun return -EIO;
1980*4882a593Smuzhiyun
1981*4882a593Smuzhiyun /* Copy the status back to the users buffer. */
1982*4882a593Smuzhiyun if (copy_to_user((void __user *) arg,
1983*4882a593Smuzhiyun drive_command,
1984*4882a593Smuzhiyun sizeof(drive_command)))
1985*4882a593Smuzhiyun return -EFAULT;
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun break;
1988*4882a593Smuzhiyun }
1989*4882a593Smuzhiyun case HDIO_DRIVE_TASK:
1990*4882a593Smuzhiyun {
1991*4882a593Smuzhiyun u8 drive_command[7];
1992*4882a593Smuzhiyun
1993*4882a593Smuzhiyun /* Copy the user command info to our buffer. */
1994*4882a593Smuzhiyun if (copy_from_user(drive_command,
1995*4882a593Smuzhiyun (void __user *) arg,
1996*4882a593Smuzhiyun sizeof(drive_command)))
1997*4882a593Smuzhiyun return -EFAULT;
1998*4882a593Smuzhiyun
1999*4882a593Smuzhiyun /* Execute the drive command. */
2000*4882a593Smuzhiyun if (exec_drive_task(dd->port, drive_command))
2001*4882a593Smuzhiyun return -EIO;
2002*4882a593Smuzhiyun
2003*4882a593Smuzhiyun /* Copy the status back to the users buffer. */
2004*4882a593Smuzhiyun if (copy_to_user((void __user *) arg,
2005*4882a593Smuzhiyun drive_command,
2006*4882a593Smuzhiyun sizeof(drive_command)))
2007*4882a593Smuzhiyun return -EFAULT;
2008*4882a593Smuzhiyun
2009*4882a593Smuzhiyun break;
2010*4882a593Smuzhiyun }
2011*4882a593Smuzhiyun case HDIO_DRIVE_TASKFILE: {
2012*4882a593Smuzhiyun ide_task_request_t req_task;
2013*4882a593Smuzhiyun int ret, outtotal;
2014*4882a593Smuzhiyun
2015*4882a593Smuzhiyun if (copy_from_user(&req_task, (void __user *) arg,
2016*4882a593Smuzhiyun sizeof(req_task)))
2017*4882a593Smuzhiyun return -EFAULT;
2018*4882a593Smuzhiyun
2019*4882a593Smuzhiyun outtotal = sizeof(req_task);
2020*4882a593Smuzhiyun
2021*4882a593Smuzhiyun ret = exec_drive_taskfile(dd, (void __user *) arg,
2022*4882a593Smuzhiyun &req_task, outtotal);
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun if (copy_to_user((void __user *) arg, &req_task,
2025*4882a593Smuzhiyun sizeof(req_task)))
2026*4882a593Smuzhiyun return -EFAULT;
2027*4882a593Smuzhiyun
2028*4882a593Smuzhiyun return ret;
2029*4882a593Smuzhiyun }
2030*4882a593Smuzhiyun
2031*4882a593Smuzhiyun default:
2032*4882a593Smuzhiyun return -EINVAL;
2033*4882a593Smuzhiyun }
2034*4882a593Smuzhiyun return 0;
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun
2037*4882a593Smuzhiyun /*
2038*4882a593Smuzhiyun * Submit an IO to the hw
2039*4882a593Smuzhiyun *
2040*4882a593Smuzhiyun * This function is called by the block layer to issue an io
2041*4882a593Smuzhiyun * to the device. Upon completion, the callback function will
2042*4882a593Smuzhiyun * be called with the data parameter passed as the callback data.
2043*4882a593Smuzhiyun *
2044*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
2045*4882a593Smuzhiyun * @start First sector to read.
2046*4882a593Smuzhiyun * @nsect Number of sectors to read.
2047*4882a593Smuzhiyun * @tag The tag of this read command.
2048*4882a593Smuzhiyun * @callback Pointer to the function that should be called
2049*4882a593Smuzhiyun * when the read completes.
2050*4882a593Smuzhiyun * @data Callback data passed to the callback function
2051*4882a593Smuzhiyun * when the read completes.
2052*4882a593Smuzhiyun * @dir Direction (read or write)
2053*4882a593Smuzhiyun *
2054*4882a593Smuzhiyun * return value
2055*4882a593Smuzhiyun * None
2056*4882a593Smuzhiyun */
mtip_hw_submit_io(struct driver_data * dd,struct request * rq,struct mtip_cmd * command,struct blk_mq_hw_ctx * hctx)2057*4882a593Smuzhiyun static void mtip_hw_submit_io(struct driver_data *dd, struct request *rq,
2058*4882a593Smuzhiyun struct mtip_cmd *command,
2059*4882a593Smuzhiyun struct blk_mq_hw_ctx *hctx)
2060*4882a593Smuzhiyun {
2061*4882a593Smuzhiyun struct mtip_cmd_hdr *hdr =
2062*4882a593Smuzhiyun dd->port->command_list + sizeof(struct mtip_cmd_hdr) * rq->tag;
2063*4882a593Smuzhiyun struct host_to_dev_fis *fis;
2064*4882a593Smuzhiyun struct mtip_port *port = dd->port;
2065*4882a593Smuzhiyun int dma_dir = rq_data_dir(rq) == READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2066*4882a593Smuzhiyun u64 start = blk_rq_pos(rq);
2067*4882a593Smuzhiyun unsigned int nsect = blk_rq_sectors(rq);
2068*4882a593Smuzhiyun unsigned int nents;
2069*4882a593Smuzhiyun
2070*4882a593Smuzhiyun /* Map the scatter list for DMA access */
2071*4882a593Smuzhiyun nents = blk_rq_map_sg(hctx->queue, rq, command->sg);
2072*4882a593Smuzhiyun nents = dma_map_sg(&dd->pdev->dev, command->sg, nents, dma_dir);
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun prefetch(&port->flags);
2075*4882a593Smuzhiyun
2076*4882a593Smuzhiyun command->scatter_ents = nents;
2077*4882a593Smuzhiyun
2078*4882a593Smuzhiyun /*
2079*4882a593Smuzhiyun * The number of retries for this command before it is
2080*4882a593Smuzhiyun * reported as a failure to the upper layers.
2081*4882a593Smuzhiyun */
2082*4882a593Smuzhiyun command->retries = MTIP_MAX_RETRIES;
2083*4882a593Smuzhiyun
2084*4882a593Smuzhiyun /* Fill out fis */
2085*4882a593Smuzhiyun fis = command->command;
2086*4882a593Smuzhiyun fis->type = 0x27;
2087*4882a593Smuzhiyun fis->opts = 1 << 7;
2088*4882a593Smuzhiyun if (dma_dir == DMA_FROM_DEVICE)
2089*4882a593Smuzhiyun fis->command = ATA_CMD_FPDMA_READ;
2090*4882a593Smuzhiyun else
2091*4882a593Smuzhiyun fis->command = ATA_CMD_FPDMA_WRITE;
2092*4882a593Smuzhiyun fis->lba_low = start & 0xFF;
2093*4882a593Smuzhiyun fis->lba_mid = (start >> 8) & 0xFF;
2094*4882a593Smuzhiyun fis->lba_hi = (start >> 16) & 0xFF;
2095*4882a593Smuzhiyun fis->lba_low_ex = (start >> 24) & 0xFF;
2096*4882a593Smuzhiyun fis->lba_mid_ex = (start >> 32) & 0xFF;
2097*4882a593Smuzhiyun fis->lba_hi_ex = (start >> 40) & 0xFF;
2098*4882a593Smuzhiyun fis->device = 1 << 6;
2099*4882a593Smuzhiyun fis->features = nsect & 0xFF;
2100*4882a593Smuzhiyun fis->features_ex = (nsect >> 8) & 0xFF;
2101*4882a593Smuzhiyun fis->sect_count = ((rq->tag << 3) | (rq->tag >> 5));
2102*4882a593Smuzhiyun fis->sect_cnt_ex = 0;
2103*4882a593Smuzhiyun fis->control = 0;
2104*4882a593Smuzhiyun fis->res2 = 0;
2105*4882a593Smuzhiyun fis->res3 = 0;
2106*4882a593Smuzhiyun fill_command_sg(dd, command, nents);
2107*4882a593Smuzhiyun
2108*4882a593Smuzhiyun if (unlikely(command->unaligned))
2109*4882a593Smuzhiyun fis->device |= 1 << 7;
2110*4882a593Smuzhiyun
2111*4882a593Smuzhiyun /* Populate the command header */
2112*4882a593Smuzhiyun hdr->ctba = cpu_to_le32(command->command_dma & 0xFFFFFFFF);
2113*4882a593Smuzhiyun if (test_bit(MTIP_PF_HOST_CAP_64, &dd->port->flags))
2114*4882a593Smuzhiyun hdr->ctbau = cpu_to_le32((command->command_dma >> 16) >> 16);
2115*4882a593Smuzhiyun hdr->opts = cpu_to_le32((nents << 16) | 5 | AHCI_CMD_PREFETCH);
2116*4882a593Smuzhiyun hdr->byte_count = 0;
2117*4882a593Smuzhiyun
2118*4882a593Smuzhiyun command->direction = dma_dir;
2119*4882a593Smuzhiyun
2120*4882a593Smuzhiyun /*
2121*4882a593Smuzhiyun * To prevent this command from being issued
2122*4882a593Smuzhiyun * if an internal command is in progress or error handling is active.
2123*4882a593Smuzhiyun */
2124*4882a593Smuzhiyun if (unlikely(port->flags & MTIP_PF_PAUSE_IO)) {
2125*4882a593Smuzhiyun set_bit(rq->tag, port->cmds_to_issue);
2126*4882a593Smuzhiyun set_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags);
2127*4882a593Smuzhiyun return;
2128*4882a593Smuzhiyun }
2129*4882a593Smuzhiyun
2130*4882a593Smuzhiyun /* Issue the command to the hardware */
2131*4882a593Smuzhiyun mtip_issue_ncq_command(port, rq->tag);
2132*4882a593Smuzhiyun }
2133*4882a593Smuzhiyun
2134*4882a593Smuzhiyun /*
2135*4882a593Smuzhiyun * Sysfs status dump.
2136*4882a593Smuzhiyun *
2137*4882a593Smuzhiyun * @dev Pointer to the device structure, passed by the kernrel.
2138*4882a593Smuzhiyun * @attr Pointer to the device_attribute structure passed by the kernel.
2139*4882a593Smuzhiyun * @buf Pointer to the char buffer that will receive the stats info.
2140*4882a593Smuzhiyun *
2141*4882a593Smuzhiyun * return value
2142*4882a593Smuzhiyun * The size, in bytes, of the data copied into buf.
2143*4882a593Smuzhiyun */
mtip_hw_show_status(struct device * dev,struct device_attribute * attr,char * buf)2144*4882a593Smuzhiyun static ssize_t mtip_hw_show_status(struct device *dev,
2145*4882a593Smuzhiyun struct device_attribute *attr,
2146*4882a593Smuzhiyun char *buf)
2147*4882a593Smuzhiyun {
2148*4882a593Smuzhiyun struct driver_data *dd = dev_to_disk(dev)->private_data;
2149*4882a593Smuzhiyun int size = 0;
2150*4882a593Smuzhiyun
2151*4882a593Smuzhiyun if (test_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag))
2152*4882a593Smuzhiyun size += sprintf(buf, "%s", "thermal_shutdown\n");
2153*4882a593Smuzhiyun else if (test_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag))
2154*4882a593Smuzhiyun size += sprintf(buf, "%s", "write_protect\n");
2155*4882a593Smuzhiyun else
2156*4882a593Smuzhiyun size += sprintf(buf, "%s", "online\n");
2157*4882a593Smuzhiyun
2158*4882a593Smuzhiyun return size;
2159*4882a593Smuzhiyun }
2160*4882a593Smuzhiyun
2161*4882a593Smuzhiyun static DEVICE_ATTR(status, 0444, mtip_hw_show_status, NULL);
2162*4882a593Smuzhiyun
2163*4882a593Smuzhiyun /* debugsfs entries */
2164*4882a593Smuzhiyun
show_device_status(struct device_driver * drv,char * buf)2165*4882a593Smuzhiyun static ssize_t show_device_status(struct device_driver *drv, char *buf)
2166*4882a593Smuzhiyun {
2167*4882a593Smuzhiyun int size = 0;
2168*4882a593Smuzhiyun struct driver_data *dd, *tmp;
2169*4882a593Smuzhiyun unsigned long flags;
2170*4882a593Smuzhiyun char id_buf[42];
2171*4882a593Smuzhiyun u16 status = 0;
2172*4882a593Smuzhiyun
2173*4882a593Smuzhiyun spin_lock_irqsave(&dev_lock, flags);
2174*4882a593Smuzhiyun size += sprintf(&buf[size], "Devices Present:\n");
2175*4882a593Smuzhiyun list_for_each_entry_safe(dd, tmp, &online_list, online_list) {
2176*4882a593Smuzhiyun if (dd->pdev) {
2177*4882a593Smuzhiyun if (dd->port &&
2178*4882a593Smuzhiyun dd->port->identify &&
2179*4882a593Smuzhiyun dd->port->identify_valid) {
2180*4882a593Smuzhiyun strlcpy(id_buf,
2181*4882a593Smuzhiyun (char *) (dd->port->identify + 10), 21);
2182*4882a593Smuzhiyun status = *(dd->port->identify + 141);
2183*4882a593Smuzhiyun } else {
2184*4882a593Smuzhiyun memset(id_buf, 0, 42);
2185*4882a593Smuzhiyun status = 0;
2186*4882a593Smuzhiyun }
2187*4882a593Smuzhiyun
2188*4882a593Smuzhiyun if (dd->port &&
2189*4882a593Smuzhiyun test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags)) {
2190*4882a593Smuzhiyun size += sprintf(&buf[size],
2191*4882a593Smuzhiyun " device %s %s (ftl rebuild %d %%)\n",
2192*4882a593Smuzhiyun dev_name(&dd->pdev->dev),
2193*4882a593Smuzhiyun id_buf,
2194*4882a593Smuzhiyun status);
2195*4882a593Smuzhiyun } else {
2196*4882a593Smuzhiyun size += sprintf(&buf[size],
2197*4882a593Smuzhiyun " device %s %s\n",
2198*4882a593Smuzhiyun dev_name(&dd->pdev->dev),
2199*4882a593Smuzhiyun id_buf);
2200*4882a593Smuzhiyun }
2201*4882a593Smuzhiyun }
2202*4882a593Smuzhiyun }
2203*4882a593Smuzhiyun
2204*4882a593Smuzhiyun size += sprintf(&buf[size], "Devices Being Removed:\n");
2205*4882a593Smuzhiyun list_for_each_entry_safe(dd, tmp, &removing_list, remove_list) {
2206*4882a593Smuzhiyun if (dd->pdev) {
2207*4882a593Smuzhiyun if (dd->port &&
2208*4882a593Smuzhiyun dd->port->identify &&
2209*4882a593Smuzhiyun dd->port->identify_valid) {
2210*4882a593Smuzhiyun strlcpy(id_buf,
2211*4882a593Smuzhiyun (char *) (dd->port->identify+10), 21);
2212*4882a593Smuzhiyun status = *(dd->port->identify + 141);
2213*4882a593Smuzhiyun } else {
2214*4882a593Smuzhiyun memset(id_buf, 0, 42);
2215*4882a593Smuzhiyun status = 0;
2216*4882a593Smuzhiyun }
2217*4882a593Smuzhiyun
2218*4882a593Smuzhiyun if (dd->port &&
2219*4882a593Smuzhiyun test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags)) {
2220*4882a593Smuzhiyun size += sprintf(&buf[size],
2221*4882a593Smuzhiyun " device %s %s (ftl rebuild %d %%)\n",
2222*4882a593Smuzhiyun dev_name(&dd->pdev->dev),
2223*4882a593Smuzhiyun id_buf,
2224*4882a593Smuzhiyun status);
2225*4882a593Smuzhiyun } else {
2226*4882a593Smuzhiyun size += sprintf(&buf[size],
2227*4882a593Smuzhiyun " device %s %s\n",
2228*4882a593Smuzhiyun dev_name(&dd->pdev->dev),
2229*4882a593Smuzhiyun id_buf);
2230*4882a593Smuzhiyun }
2231*4882a593Smuzhiyun }
2232*4882a593Smuzhiyun }
2233*4882a593Smuzhiyun spin_unlock_irqrestore(&dev_lock, flags);
2234*4882a593Smuzhiyun
2235*4882a593Smuzhiyun return size;
2236*4882a593Smuzhiyun }
2237*4882a593Smuzhiyun
mtip_hw_read_device_status(struct file * f,char __user * ubuf,size_t len,loff_t * offset)2238*4882a593Smuzhiyun static ssize_t mtip_hw_read_device_status(struct file *f, char __user *ubuf,
2239*4882a593Smuzhiyun size_t len, loff_t *offset)
2240*4882a593Smuzhiyun {
2241*4882a593Smuzhiyun struct driver_data *dd = (struct driver_data *)f->private_data;
2242*4882a593Smuzhiyun int size = *offset;
2243*4882a593Smuzhiyun char *buf;
2244*4882a593Smuzhiyun int rv = 0;
2245*4882a593Smuzhiyun
2246*4882a593Smuzhiyun if (!len || *offset)
2247*4882a593Smuzhiyun return 0;
2248*4882a593Smuzhiyun
2249*4882a593Smuzhiyun buf = kzalloc(MTIP_DFS_MAX_BUF_SIZE, GFP_KERNEL);
2250*4882a593Smuzhiyun if (!buf) {
2251*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2252*4882a593Smuzhiyun "Memory allocation: status buffer\n");
2253*4882a593Smuzhiyun return -ENOMEM;
2254*4882a593Smuzhiyun }
2255*4882a593Smuzhiyun
2256*4882a593Smuzhiyun size += show_device_status(NULL, buf);
2257*4882a593Smuzhiyun
2258*4882a593Smuzhiyun *offset = size <= len ? size : len;
2259*4882a593Smuzhiyun size = copy_to_user(ubuf, buf, *offset);
2260*4882a593Smuzhiyun if (size)
2261*4882a593Smuzhiyun rv = -EFAULT;
2262*4882a593Smuzhiyun
2263*4882a593Smuzhiyun kfree(buf);
2264*4882a593Smuzhiyun return rv ? rv : *offset;
2265*4882a593Smuzhiyun }
2266*4882a593Smuzhiyun
mtip_hw_read_registers(struct file * f,char __user * ubuf,size_t len,loff_t * offset)2267*4882a593Smuzhiyun static ssize_t mtip_hw_read_registers(struct file *f, char __user *ubuf,
2268*4882a593Smuzhiyun size_t len, loff_t *offset)
2269*4882a593Smuzhiyun {
2270*4882a593Smuzhiyun struct driver_data *dd = (struct driver_data *)f->private_data;
2271*4882a593Smuzhiyun char *buf;
2272*4882a593Smuzhiyun u32 group_allocated;
2273*4882a593Smuzhiyun int size = *offset;
2274*4882a593Smuzhiyun int n, rv = 0;
2275*4882a593Smuzhiyun
2276*4882a593Smuzhiyun if (!len || size)
2277*4882a593Smuzhiyun return 0;
2278*4882a593Smuzhiyun
2279*4882a593Smuzhiyun buf = kzalloc(MTIP_DFS_MAX_BUF_SIZE, GFP_KERNEL);
2280*4882a593Smuzhiyun if (!buf) {
2281*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2282*4882a593Smuzhiyun "Memory allocation: register buffer\n");
2283*4882a593Smuzhiyun return -ENOMEM;
2284*4882a593Smuzhiyun }
2285*4882a593Smuzhiyun
2286*4882a593Smuzhiyun size += sprintf(&buf[size], "H/ S ACTive : [ 0x");
2287*4882a593Smuzhiyun
2288*4882a593Smuzhiyun for (n = dd->slot_groups-1; n >= 0; n--)
2289*4882a593Smuzhiyun size += sprintf(&buf[size], "%08X ",
2290*4882a593Smuzhiyun readl(dd->port->s_active[n]));
2291*4882a593Smuzhiyun
2292*4882a593Smuzhiyun size += sprintf(&buf[size], "]\n");
2293*4882a593Smuzhiyun size += sprintf(&buf[size], "H/ Command Issue : [ 0x");
2294*4882a593Smuzhiyun
2295*4882a593Smuzhiyun for (n = dd->slot_groups-1; n >= 0; n--)
2296*4882a593Smuzhiyun size += sprintf(&buf[size], "%08X ",
2297*4882a593Smuzhiyun readl(dd->port->cmd_issue[n]));
2298*4882a593Smuzhiyun
2299*4882a593Smuzhiyun size += sprintf(&buf[size], "]\n");
2300*4882a593Smuzhiyun size += sprintf(&buf[size], "H/ Completed : [ 0x");
2301*4882a593Smuzhiyun
2302*4882a593Smuzhiyun for (n = dd->slot_groups-1; n >= 0; n--)
2303*4882a593Smuzhiyun size += sprintf(&buf[size], "%08X ",
2304*4882a593Smuzhiyun readl(dd->port->completed[n]));
2305*4882a593Smuzhiyun
2306*4882a593Smuzhiyun size += sprintf(&buf[size], "]\n");
2307*4882a593Smuzhiyun size += sprintf(&buf[size], "H/ PORT IRQ STAT : [ 0x%08X ]\n",
2308*4882a593Smuzhiyun readl(dd->port->mmio + PORT_IRQ_STAT));
2309*4882a593Smuzhiyun size += sprintf(&buf[size], "H/ HOST IRQ STAT : [ 0x%08X ]\n",
2310*4882a593Smuzhiyun readl(dd->mmio + HOST_IRQ_STAT));
2311*4882a593Smuzhiyun size += sprintf(&buf[size], "\n");
2312*4882a593Smuzhiyun
2313*4882a593Smuzhiyun size += sprintf(&buf[size], "L/ Commands in Q : [ 0x");
2314*4882a593Smuzhiyun
2315*4882a593Smuzhiyun for (n = dd->slot_groups-1; n >= 0; n--) {
2316*4882a593Smuzhiyun if (sizeof(long) > sizeof(u32))
2317*4882a593Smuzhiyun group_allocated =
2318*4882a593Smuzhiyun dd->port->cmds_to_issue[n/2] >> (32*(n&1));
2319*4882a593Smuzhiyun else
2320*4882a593Smuzhiyun group_allocated = dd->port->cmds_to_issue[n];
2321*4882a593Smuzhiyun size += sprintf(&buf[size], "%08X ", group_allocated);
2322*4882a593Smuzhiyun }
2323*4882a593Smuzhiyun size += sprintf(&buf[size], "]\n");
2324*4882a593Smuzhiyun
2325*4882a593Smuzhiyun *offset = size <= len ? size : len;
2326*4882a593Smuzhiyun size = copy_to_user(ubuf, buf, *offset);
2327*4882a593Smuzhiyun if (size)
2328*4882a593Smuzhiyun rv = -EFAULT;
2329*4882a593Smuzhiyun
2330*4882a593Smuzhiyun kfree(buf);
2331*4882a593Smuzhiyun return rv ? rv : *offset;
2332*4882a593Smuzhiyun }
2333*4882a593Smuzhiyun
mtip_hw_read_flags(struct file * f,char __user * ubuf,size_t len,loff_t * offset)2334*4882a593Smuzhiyun static ssize_t mtip_hw_read_flags(struct file *f, char __user *ubuf,
2335*4882a593Smuzhiyun size_t len, loff_t *offset)
2336*4882a593Smuzhiyun {
2337*4882a593Smuzhiyun struct driver_data *dd = (struct driver_data *)f->private_data;
2338*4882a593Smuzhiyun char *buf;
2339*4882a593Smuzhiyun int size = *offset;
2340*4882a593Smuzhiyun int rv = 0;
2341*4882a593Smuzhiyun
2342*4882a593Smuzhiyun if (!len || size)
2343*4882a593Smuzhiyun return 0;
2344*4882a593Smuzhiyun
2345*4882a593Smuzhiyun buf = kzalloc(MTIP_DFS_MAX_BUF_SIZE, GFP_KERNEL);
2346*4882a593Smuzhiyun if (!buf) {
2347*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2348*4882a593Smuzhiyun "Memory allocation: flag buffer\n");
2349*4882a593Smuzhiyun return -ENOMEM;
2350*4882a593Smuzhiyun }
2351*4882a593Smuzhiyun
2352*4882a593Smuzhiyun size += sprintf(&buf[size], "Flag-port : [ %08lX ]\n",
2353*4882a593Smuzhiyun dd->port->flags);
2354*4882a593Smuzhiyun size += sprintf(&buf[size], "Flag-dd : [ %08lX ]\n",
2355*4882a593Smuzhiyun dd->dd_flag);
2356*4882a593Smuzhiyun
2357*4882a593Smuzhiyun *offset = size <= len ? size : len;
2358*4882a593Smuzhiyun size = copy_to_user(ubuf, buf, *offset);
2359*4882a593Smuzhiyun if (size)
2360*4882a593Smuzhiyun rv = -EFAULT;
2361*4882a593Smuzhiyun
2362*4882a593Smuzhiyun kfree(buf);
2363*4882a593Smuzhiyun return rv ? rv : *offset;
2364*4882a593Smuzhiyun }
2365*4882a593Smuzhiyun
2366*4882a593Smuzhiyun static const struct file_operations mtip_device_status_fops = {
2367*4882a593Smuzhiyun .owner = THIS_MODULE,
2368*4882a593Smuzhiyun .open = simple_open,
2369*4882a593Smuzhiyun .read = mtip_hw_read_device_status,
2370*4882a593Smuzhiyun .llseek = no_llseek,
2371*4882a593Smuzhiyun };
2372*4882a593Smuzhiyun
2373*4882a593Smuzhiyun static const struct file_operations mtip_regs_fops = {
2374*4882a593Smuzhiyun .owner = THIS_MODULE,
2375*4882a593Smuzhiyun .open = simple_open,
2376*4882a593Smuzhiyun .read = mtip_hw_read_registers,
2377*4882a593Smuzhiyun .llseek = no_llseek,
2378*4882a593Smuzhiyun };
2379*4882a593Smuzhiyun
2380*4882a593Smuzhiyun static const struct file_operations mtip_flags_fops = {
2381*4882a593Smuzhiyun .owner = THIS_MODULE,
2382*4882a593Smuzhiyun .open = simple_open,
2383*4882a593Smuzhiyun .read = mtip_hw_read_flags,
2384*4882a593Smuzhiyun .llseek = no_llseek,
2385*4882a593Smuzhiyun };
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun /*
2388*4882a593Smuzhiyun * Create the sysfs related attributes.
2389*4882a593Smuzhiyun *
2390*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
2391*4882a593Smuzhiyun * @kobj Pointer to the kobj for the block device.
2392*4882a593Smuzhiyun *
2393*4882a593Smuzhiyun * return value
2394*4882a593Smuzhiyun * 0 Operation completed successfully.
2395*4882a593Smuzhiyun * -EINVAL Invalid parameter.
2396*4882a593Smuzhiyun */
mtip_hw_sysfs_init(struct driver_data * dd,struct kobject * kobj)2397*4882a593Smuzhiyun static int mtip_hw_sysfs_init(struct driver_data *dd, struct kobject *kobj)
2398*4882a593Smuzhiyun {
2399*4882a593Smuzhiyun if (!kobj || !dd)
2400*4882a593Smuzhiyun return -EINVAL;
2401*4882a593Smuzhiyun
2402*4882a593Smuzhiyun if (sysfs_create_file(kobj, &dev_attr_status.attr))
2403*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2404*4882a593Smuzhiyun "Error creating 'status' sysfs entry\n");
2405*4882a593Smuzhiyun return 0;
2406*4882a593Smuzhiyun }
2407*4882a593Smuzhiyun
2408*4882a593Smuzhiyun /*
2409*4882a593Smuzhiyun * Remove the sysfs related attributes.
2410*4882a593Smuzhiyun *
2411*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
2412*4882a593Smuzhiyun * @kobj Pointer to the kobj for the block device.
2413*4882a593Smuzhiyun *
2414*4882a593Smuzhiyun * return value
2415*4882a593Smuzhiyun * 0 Operation completed successfully.
2416*4882a593Smuzhiyun * -EINVAL Invalid parameter.
2417*4882a593Smuzhiyun */
mtip_hw_sysfs_exit(struct driver_data * dd,struct kobject * kobj)2418*4882a593Smuzhiyun static int mtip_hw_sysfs_exit(struct driver_data *dd, struct kobject *kobj)
2419*4882a593Smuzhiyun {
2420*4882a593Smuzhiyun if (!kobj || !dd)
2421*4882a593Smuzhiyun return -EINVAL;
2422*4882a593Smuzhiyun
2423*4882a593Smuzhiyun sysfs_remove_file(kobj, &dev_attr_status.attr);
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun return 0;
2426*4882a593Smuzhiyun }
2427*4882a593Smuzhiyun
mtip_hw_debugfs_init(struct driver_data * dd)2428*4882a593Smuzhiyun static int mtip_hw_debugfs_init(struct driver_data *dd)
2429*4882a593Smuzhiyun {
2430*4882a593Smuzhiyun if (!dfs_parent)
2431*4882a593Smuzhiyun return -1;
2432*4882a593Smuzhiyun
2433*4882a593Smuzhiyun dd->dfs_node = debugfs_create_dir(dd->disk->disk_name, dfs_parent);
2434*4882a593Smuzhiyun if (IS_ERR_OR_NULL(dd->dfs_node)) {
2435*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2436*4882a593Smuzhiyun "Error creating node %s under debugfs\n",
2437*4882a593Smuzhiyun dd->disk->disk_name);
2438*4882a593Smuzhiyun dd->dfs_node = NULL;
2439*4882a593Smuzhiyun return -1;
2440*4882a593Smuzhiyun }
2441*4882a593Smuzhiyun
2442*4882a593Smuzhiyun debugfs_create_file("flags", 0444, dd->dfs_node, dd, &mtip_flags_fops);
2443*4882a593Smuzhiyun debugfs_create_file("registers", 0444, dd->dfs_node, dd,
2444*4882a593Smuzhiyun &mtip_regs_fops);
2445*4882a593Smuzhiyun
2446*4882a593Smuzhiyun return 0;
2447*4882a593Smuzhiyun }
2448*4882a593Smuzhiyun
mtip_hw_debugfs_exit(struct driver_data * dd)2449*4882a593Smuzhiyun static void mtip_hw_debugfs_exit(struct driver_data *dd)
2450*4882a593Smuzhiyun {
2451*4882a593Smuzhiyun debugfs_remove_recursive(dd->dfs_node);
2452*4882a593Smuzhiyun }
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun /*
2455*4882a593Smuzhiyun * Perform any init/resume time hardware setup
2456*4882a593Smuzhiyun *
2457*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
2458*4882a593Smuzhiyun *
2459*4882a593Smuzhiyun * return value
2460*4882a593Smuzhiyun * None
2461*4882a593Smuzhiyun */
hba_setup(struct driver_data * dd)2462*4882a593Smuzhiyun static inline void hba_setup(struct driver_data *dd)
2463*4882a593Smuzhiyun {
2464*4882a593Smuzhiyun u32 hwdata;
2465*4882a593Smuzhiyun hwdata = readl(dd->mmio + HOST_HSORG);
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun /* interrupt bug workaround: use only 1 IS bit.*/
2468*4882a593Smuzhiyun writel(hwdata |
2469*4882a593Smuzhiyun HSORG_DISABLE_SLOTGRP_INTR |
2470*4882a593Smuzhiyun HSORG_DISABLE_SLOTGRP_PXIS,
2471*4882a593Smuzhiyun dd->mmio + HOST_HSORG);
2472*4882a593Smuzhiyun }
2473*4882a593Smuzhiyun
mtip_device_unaligned_constrained(struct driver_data * dd)2474*4882a593Smuzhiyun static int mtip_device_unaligned_constrained(struct driver_data *dd)
2475*4882a593Smuzhiyun {
2476*4882a593Smuzhiyun return (dd->pdev->device == P420M_DEVICE_ID ? 1 : 0);
2477*4882a593Smuzhiyun }
2478*4882a593Smuzhiyun
2479*4882a593Smuzhiyun /*
2480*4882a593Smuzhiyun * Detect the details of the product, and store anything needed
2481*4882a593Smuzhiyun * into the driver data structure. This includes product type and
2482*4882a593Smuzhiyun * version and number of slot groups.
2483*4882a593Smuzhiyun *
2484*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
2485*4882a593Smuzhiyun *
2486*4882a593Smuzhiyun * return value
2487*4882a593Smuzhiyun * None
2488*4882a593Smuzhiyun */
mtip_detect_product(struct driver_data * dd)2489*4882a593Smuzhiyun static void mtip_detect_product(struct driver_data *dd)
2490*4882a593Smuzhiyun {
2491*4882a593Smuzhiyun u32 hwdata;
2492*4882a593Smuzhiyun unsigned int rev, slotgroups;
2493*4882a593Smuzhiyun
2494*4882a593Smuzhiyun /*
2495*4882a593Smuzhiyun * HBA base + 0xFC [15:0] - vendor-specific hardware interface
2496*4882a593Smuzhiyun * info register:
2497*4882a593Smuzhiyun * [15:8] hardware/software interface rev#
2498*4882a593Smuzhiyun * [ 3] asic-style interface
2499*4882a593Smuzhiyun * [ 2:0] number of slot groups, minus 1 (only valid for asic-style).
2500*4882a593Smuzhiyun */
2501*4882a593Smuzhiyun hwdata = readl(dd->mmio + HOST_HSORG);
2502*4882a593Smuzhiyun
2503*4882a593Smuzhiyun dd->product_type = MTIP_PRODUCT_UNKNOWN;
2504*4882a593Smuzhiyun dd->slot_groups = 1;
2505*4882a593Smuzhiyun
2506*4882a593Smuzhiyun if (hwdata & 0x8) {
2507*4882a593Smuzhiyun dd->product_type = MTIP_PRODUCT_ASICFPGA;
2508*4882a593Smuzhiyun rev = (hwdata & HSORG_HWREV) >> 8;
2509*4882a593Smuzhiyun slotgroups = (hwdata & HSORG_SLOTGROUPS) + 1;
2510*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
2511*4882a593Smuzhiyun "ASIC-FPGA design, HS rev 0x%x, "
2512*4882a593Smuzhiyun "%i slot groups [%i slots]\n",
2513*4882a593Smuzhiyun rev,
2514*4882a593Smuzhiyun slotgroups,
2515*4882a593Smuzhiyun slotgroups * 32);
2516*4882a593Smuzhiyun
2517*4882a593Smuzhiyun if (slotgroups > MTIP_MAX_SLOT_GROUPS) {
2518*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2519*4882a593Smuzhiyun "Warning: driver only supports "
2520*4882a593Smuzhiyun "%i slot groups.\n", MTIP_MAX_SLOT_GROUPS);
2521*4882a593Smuzhiyun slotgroups = MTIP_MAX_SLOT_GROUPS;
2522*4882a593Smuzhiyun }
2523*4882a593Smuzhiyun dd->slot_groups = slotgroups;
2524*4882a593Smuzhiyun return;
2525*4882a593Smuzhiyun }
2526*4882a593Smuzhiyun
2527*4882a593Smuzhiyun dev_warn(&dd->pdev->dev, "Unrecognized product id\n");
2528*4882a593Smuzhiyun }
2529*4882a593Smuzhiyun
2530*4882a593Smuzhiyun /*
2531*4882a593Smuzhiyun * Blocking wait for FTL rebuild to complete
2532*4882a593Smuzhiyun *
2533*4882a593Smuzhiyun * @dd Pointer to the DRIVER_DATA structure.
2534*4882a593Smuzhiyun *
2535*4882a593Smuzhiyun * return value
2536*4882a593Smuzhiyun * 0 FTL rebuild completed successfully
2537*4882a593Smuzhiyun * -EFAULT FTL rebuild error/timeout/interruption
2538*4882a593Smuzhiyun */
mtip_ftl_rebuild_poll(struct driver_data * dd)2539*4882a593Smuzhiyun static int mtip_ftl_rebuild_poll(struct driver_data *dd)
2540*4882a593Smuzhiyun {
2541*4882a593Smuzhiyun unsigned long timeout, cnt = 0, start;
2542*4882a593Smuzhiyun
2543*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2544*4882a593Smuzhiyun "FTL rebuild in progress. Polling for completion.\n");
2545*4882a593Smuzhiyun
2546*4882a593Smuzhiyun start = jiffies;
2547*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(MTIP_FTL_REBUILD_TIMEOUT_MS);
2548*4882a593Smuzhiyun
2549*4882a593Smuzhiyun do {
2550*4882a593Smuzhiyun if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
2551*4882a593Smuzhiyun &dd->dd_flag)))
2552*4882a593Smuzhiyun return -EFAULT;
2553*4882a593Smuzhiyun if (mtip_check_surprise_removal(dd->pdev))
2554*4882a593Smuzhiyun return -EFAULT;
2555*4882a593Smuzhiyun
2556*4882a593Smuzhiyun if (mtip_get_identify(dd->port, NULL) < 0)
2557*4882a593Smuzhiyun return -EFAULT;
2558*4882a593Smuzhiyun
2559*4882a593Smuzhiyun if (*(dd->port->identify + MTIP_FTL_REBUILD_OFFSET) ==
2560*4882a593Smuzhiyun MTIP_FTL_REBUILD_MAGIC) {
2561*4882a593Smuzhiyun ssleep(1);
2562*4882a593Smuzhiyun /* Print message every 3 minutes */
2563*4882a593Smuzhiyun if (cnt++ >= 180) {
2564*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2565*4882a593Smuzhiyun "FTL rebuild in progress (%d secs).\n",
2566*4882a593Smuzhiyun jiffies_to_msecs(jiffies - start) / 1000);
2567*4882a593Smuzhiyun cnt = 0;
2568*4882a593Smuzhiyun }
2569*4882a593Smuzhiyun } else {
2570*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2571*4882a593Smuzhiyun "FTL rebuild complete (%d secs).\n",
2572*4882a593Smuzhiyun jiffies_to_msecs(jiffies - start) / 1000);
2573*4882a593Smuzhiyun mtip_block_initialize(dd);
2574*4882a593Smuzhiyun return 0;
2575*4882a593Smuzhiyun }
2576*4882a593Smuzhiyun } while (time_before(jiffies, timeout));
2577*4882a593Smuzhiyun
2578*4882a593Smuzhiyun /* Check for timeout */
2579*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2580*4882a593Smuzhiyun "Timed out waiting for FTL rebuild to complete (%d secs).\n",
2581*4882a593Smuzhiyun jiffies_to_msecs(jiffies - start) / 1000);
2582*4882a593Smuzhiyun return -EFAULT;
2583*4882a593Smuzhiyun }
2584*4882a593Smuzhiyun
mtip_softirq_done_fn(struct request * rq)2585*4882a593Smuzhiyun static void mtip_softirq_done_fn(struct request *rq)
2586*4882a593Smuzhiyun {
2587*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
2588*4882a593Smuzhiyun struct driver_data *dd = rq->q->queuedata;
2589*4882a593Smuzhiyun
2590*4882a593Smuzhiyun /* Unmap the DMA scatter list entries */
2591*4882a593Smuzhiyun dma_unmap_sg(&dd->pdev->dev, cmd->sg, cmd->scatter_ents,
2592*4882a593Smuzhiyun cmd->direction);
2593*4882a593Smuzhiyun
2594*4882a593Smuzhiyun if (unlikely(cmd->unaligned))
2595*4882a593Smuzhiyun atomic_inc(&dd->port->cmd_slot_unal);
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun blk_mq_end_request(rq, cmd->status);
2598*4882a593Smuzhiyun }
2599*4882a593Smuzhiyun
mtip_abort_cmd(struct request * req,void * data,bool reserved)2600*4882a593Smuzhiyun static bool mtip_abort_cmd(struct request *req, void *data, bool reserved)
2601*4882a593Smuzhiyun {
2602*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(req);
2603*4882a593Smuzhiyun struct driver_data *dd = data;
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun dbg_printk(MTIP_DRV_NAME " Aborting request, tag = %d\n", req->tag);
2606*4882a593Smuzhiyun
2607*4882a593Smuzhiyun clear_bit(req->tag, dd->port->cmds_to_issue);
2608*4882a593Smuzhiyun cmd->status = BLK_STS_IOERR;
2609*4882a593Smuzhiyun mtip_softirq_done_fn(req);
2610*4882a593Smuzhiyun return true;
2611*4882a593Smuzhiyun }
2612*4882a593Smuzhiyun
mtip_queue_cmd(struct request * req,void * data,bool reserved)2613*4882a593Smuzhiyun static bool mtip_queue_cmd(struct request *req, void *data, bool reserved)
2614*4882a593Smuzhiyun {
2615*4882a593Smuzhiyun struct driver_data *dd = data;
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun set_bit(req->tag, dd->port->cmds_to_issue);
2618*4882a593Smuzhiyun blk_abort_request(req);
2619*4882a593Smuzhiyun return true;
2620*4882a593Smuzhiyun }
2621*4882a593Smuzhiyun
2622*4882a593Smuzhiyun /*
2623*4882a593Smuzhiyun * service thread to issue queued commands
2624*4882a593Smuzhiyun *
2625*4882a593Smuzhiyun * @data Pointer to the driver data structure.
2626*4882a593Smuzhiyun *
2627*4882a593Smuzhiyun * return value
2628*4882a593Smuzhiyun * 0
2629*4882a593Smuzhiyun */
2630*4882a593Smuzhiyun
mtip_service_thread(void * data)2631*4882a593Smuzhiyun static int mtip_service_thread(void *data)
2632*4882a593Smuzhiyun {
2633*4882a593Smuzhiyun struct driver_data *dd = (struct driver_data *)data;
2634*4882a593Smuzhiyun unsigned long slot, slot_start, slot_wrap, to;
2635*4882a593Smuzhiyun unsigned int num_cmd_slots = dd->slot_groups * 32;
2636*4882a593Smuzhiyun struct mtip_port *port = dd->port;
2637*4882a593Smuzhiyun
2638*4882a593Smuzhiyun while (1) {
2639*4882a593Smuzhiyun if (kthread_should_stop() ||
2640*4882a593Smuzhiyun test_bit(MTIP_PF_SVC_THD_STOP_BIT, &port->flags))
2641*4882a593Smuzhiyun goto st_out;
2642*4882a593Smuzhiyun clear_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags);
2643*4882a593Smuzhiyun
2644*4882a593Smuzhiyun /*
2645*4882a593Smuzhiyun * the condition is to check neither an internal command is
2646*4882a593Smuzhiyun * is in progress nor error handling is active
2647*4882a593Smuzhiyun */
2648*4882a593Smuzhiyun wait_event_interruptible(port->svc_wait, (port->flags) &&
2649*4882a593Smuzhiyun (port->flags & MTIP_PF_SVC_THD_WORK));
2650*4882a593Smuzhiyun
2651*4882a593Smuzhiyun if (kthread_should_stop() ||
2652*4882a593Smuzhiyun test_bit(MTIP_PF_SVC_THD_STOP_BIT, &port->flags))
2653*4882a593Smuzhiyun goto st_out;
2654*4882a593Smuzhiyun
2655*4882a593Smuzhiyun if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
2656*4882a593Smuzhiyun &dd->dd_flag)))
2657*4882a593Smuzhiyun goto st_out;
2658*4882a593Smuzhiyun
2659*4882a593Smuzhiyun set_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags);
2660*4882a593Smuzhiyun
2661*4882a593Smuzhiyun restart_eh:
2662*4882a593Smuzhiyun /* Demux bits: start with error handling */
2663*4882a593Smuzhiyun if (test_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags)) {
2664*4882a593Smuzhiyun mtip_handle_tfe(dd);
2665*4882a593Smuzhiyun clear_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
2666*4882a593Smuzhiyun }
2667*4882a593Smuzhiyun
2668*4882a593Smuzhiyun if (test_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags))
2669*4882a593Smuzhiyun goto restart_eh;
2670*4882a593Smuzhiyun
2671*4882a593Smuzhiyun if (test_bit(MTIP_PF_TO_ACTIVE_BIT, &port->flags)) {
2672*4882a593Smuzhiyun to = jiffies + msecs_to_jiffies(5000);
2673*4882a593Smuzhiyun
2674*4882a593Smuzhiyun do {
2675*4882a593Smuzhiyun mdelay(100);
2676*4882a593Smuzhiyun } while (atomic_read(&dd->irq_workers_active) != 0 &&
2677*4882a593Smuzhiyun time_before(jiffies, to));
2678*4882a593Smuzhiyun
2679*4882a593Smuzhiyun if (atomic_read(&dd->irq_workers_active) != 0)
2680*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2681*4882a593Smuzhiyun "Completion workers still active!");
2682*4882a593Smuzhiyun
2683*4882a593Smuzhiyun blk_mq_quiesce_queue(dd->queue);
2684*4882a593Smuzhiyun
2685*4882a593Smuzhiyun blk_mq_tagset_busy_iter(&dd->tags, mtip_queue_cmd, dd);
2686*4882a593Smuzhiyun
2687*4882a593Smuzhiyun set_bit(MTIP_PF_ISSUE_CMDS_BIT, &dd->port->flags);
2688*4882a593Smuzhiyun
2689*4882a593Smuzhiyun if (mtip_device_reset(dd))
2690*4882a593Smuzhiyun blk_mq_tagset_busy_iter(&dd->tags,
2691*4882a593Smuzhiyun mtip_abort_cmd, dd);
2692*4882a593Smuzhiyun
2693*4882a593Smuzhiyun clear_bit(MTIP_PF_TO_ACTIVE_BIT, &dd->port->flags);
2694*4882a593Smuzhiyun
2695*4882a593Smuzhiyun blk_mq_unquiesce_queue(dd->queue);
2696*4882a593Smuzhiyun }
2697*4882a593Smuzhiyun
2698*4882a593Smuzhiyun if (test_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags)) {
2699*4882a593Smuzhiyun slot = 1;
2700*4882a593Smuzhiyun /* used to restrict the loop to one iteration */
2701*4882a593Smuzhiyun slot_start = num_cmd_slots;
2702*4882a593Smuzhiyun slot_wrap = 0;
2703*4882a593Smuzhiyun while (1) {
2704*4882a593Smuzhiyun slot = find_next_bit(port->cmds_to_issue,
2705*4882a593Smuzhiyun num_cmd_slots, slot);
2706*4882a593Smuzhiyun if (slot_wrap == 1) {
2707*4882a593Smuzhiyun if ((slot_start >= slot) ||
2708*4882a593Smuzhiyun (slot >= num_cmd_slots))
2709*4882a593Smuzhiyun break;
2710*4882a593Smuzhiyun }
2711*4882a593Smuzhiyun if (unlikely(slot_start == num_cmd_slots))
2712*4882a593Smuzhiyun slot_start = slot;
2713*4882a593Smuzhiyun
2714*4882a593Smuzhiyun if (unlikely(slot == num_cmd_slots)) {
2715*4882a593Smuzhiyun slot = 1;
2716*4882a593Smuzhiyun slot_wrap = 1;
2717*4882a593Smuzhiyun continue;
2718*4882a593Smuzhiyun }
2719*4882a593Smuzhiyun
2720*4882a593Smuzhiyun /* Issue the command to the hardware */
2721*4882a593Smuzhiyun mtip_issue_ncq_command(port, slot);
2722*4882a593Smuzhiyun
2723*4882a593Smuzhiyun clear_bit(slot, port->cmds_to_issue);
2724*4882a593Smuzhiyun }
2725*4882a593Smuzhiyun
2726*4882a593Smuzhiyun clear_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags);
2727*4882a593Smuzhiyun }
2728*4882a593Smuzhiyun
2729*4882a593Smuzhiyun if (test_bit(MTIP_PF_REBUILD_BIT, &port->flags)) {
2730*4882a593Smuzhiyun if (mtip_ftl_rebuild_poll(dd) == 0)
2731*4882a593Smuzhiyun clear_bit(MTIP_PF_REBUILD_BIT, &port->flags);
2732*4882a593Smuzhiyun }
2733*4882a593Smuzhiyun }
2734*4882a593Smuzhiyun
2735*4882a593Smuzhiyun st_out:
2736*4882a593Smuzhiyun return 0;
2737*4882a593Smuzhiyun }
2738*4882a593Smuzhiyun
2739*4882a593Smuzhiyun /*
2740*4882a593Smuzhiyun * DMA region teardown
2741*4882a593Smuzhiyun *
2742*4882a593Smuzhiyun * @dd Pointer to driver_data structure
2743*4882a593Smuzhiyun *
2744*4882a593Smuzhiyun * return value
2745*4882a593Smuzhiyun * None
2746*4882a593Smuzhiyun */
mtip_dma_free(struct driver_data * dd)2747*4882a593Smuzhiyun static void mtip_dma_free(struct driver_data *dd)
2748*4882a593Smuzhiyun {
2749*4882a593Smuzhiyun struct mtip_port *port = dd->port;
2750*4882a593Smuzhiyun
2751*4882a593Smuzhiyun if (port->block1)
2752*4882a593Smuzhiyun dma_free_coherent(&dd->pdev->dev, BLOCK_DMA_ALLOC_SZ,
2753*4882a593Smuzhiyun port->block1, port->block1_dma);
2754*4882a593Smuzhiyun
2755*4882a593Smuzhiyun if (port->command_list) {
2756*4882a593Smuzhiyun dma_free_coherent(&dd->pdev->dev, AHCI_CMD_TBL_SZ,
2757*4882a593Smuzhiyun port->command_list, port->command_list_dma);
2758*4882a593Smuzhiyun }
2759*4882a593Smuzhiyun }
2760*4882a593Smuzhiyun
2761*4882a593Smuzhiyun /*
2762*4882a593Smuzhiyun * DMA region setup
2763*4882a593Smuzhiyun *
2764*4882a593Smuzhiyun * @dd Pointer to driver_data structure
2765*4882a593Smuzhiyun *
2766*4882a593Smuzhiyun * return value
2767*4882a593Smuzhiyun * -ENOMEM Not enough free DMA region space to initialize driver
2768*4882a593Smuzhiyun */
mtip_dma_alloc(struct driver_data * dd)2769*4882a593Smuzhiyun static int mtip_dma_alloc(struct driver_data *dd)
2770*4882a593Smuzhiyun {
2771*4882a593Smuzhiyun struct mtip_port *port = dd->port;
2772*4882a593Smuzhiyun
2773*4882a593Smuzhiyun /* Allocate dma memory for RX Fis, Identify, and Sector Bufffer */
2774*4882a593Smuzhiyun port->block1 =
2775*4882a593Smuzhiyun dma_alloc_coherent(&dd->pdev->dev, BLOCK_DMA_ALLOC_SZ,
2776*4882a593Smuzhiyun &port->block1_dma, GFP_KERNEL);
2777*4882a593Smuzhiyun if (!port->block1)
2778*4882a593Smuzhiyun return -ENOMEM;
2779*4882a593Smuzhiyun
2780*4882a593Smuzhiyun /* Allocate dma memory for command list */
2781*4882a593Smuzhiyun port->command_list =
2782*4882a593Smuzhiyun dma_alloc_coherent(&dd->pdev->dev, AHCI_CMD_TBL_SZ,
2783*4882a593Smuzhiyun &port->command_list_dma, GFP_KERNEL);
2784*4882a593Smuzhiyun if (!port->command_list) {
2785*4882a593Smuzhiyun dma_free_coherent(&dd->pdev->dev, BLOCK_DMA_ALLOC_SZ,
2786*4882a593Smuzhiyun port->block1, port->block1_dma);
2787*4882a593Smuzhiyun port->block1 = NULL;
2788*4882a593Smuzhiyun port->block1_dma = 0;
2789*4882a593Smuzhiyun return -ENOMEM;
2790*4882a593Smuzhiyun }
2791*4882a593Smuzhiyun
2792*4882a593Smuzhiyun /* Setup all pointers into first DMA region */
2793*4882a593Smuzhiyun port->rxfis = port->block1 + AHCI_RX_FIS_OFFSET;
2794*4882a593Smuzhiyun port->rxfis_dma = port->block1_dma + AHCI_RX_FIS_OFFSET;
2795*4882a593Smuzhiyun port->identify = port->block1 + AHCI_IDFY_OFFSET;
2796*4882a593Smuzhiyun port->identify_dma = port->block1_dma + AHCI_IDFY_OFFSET;
2797*4882a593Smuzhiyun port->log_buf = port->block1 + AHCI_SECTBUF_OFFSET;
2798*4882a593Smuzhiyun port->log_buf_dma = port->block1_dma + AHCI_SECTBUF_OFFSET;
2799*4882a593Smuzhiyun port->smart_buf = port->block1 + AHCI_SMARTBUF_OFFSET;
2800*4882a593Smuzhiyun port->smart_buf_dma = port->block1_dma + AHCI_SMARTBUF_OFFSET;
2801*4882a593Smuzhiyun
2802*4882a593Smuzhiyun return 0;
2803*4882a593Smuzhiyun }
2804*4882a593Smuzhiyun
mtip_hw_get_identify(struct driver_data * dd)2805*4882a593Smuzhiyun static int mtip_hw_get_identify(struct driver_data *dd)
2806*4882a593Smuzhiyun {
2807*4882a593Smuzhiyun struct smart_attr attr242;
2808*4882a593Smuzhiyun unsigned char *buf;
2809*4882a593Smuzhiyun int rv;
2810*4882a593Smuzhiyun
2811*4882a593Smuzhiyun if (mtip_get_identify(dd->port, NULL) < 0)
2812*4882a593Smuzhiyun return -EFAULT;
2813*4882a593Smuzhiyun
2814*4882a593Smuzhiyun if (*(dd->port->identify + MTIP_FTL_REBUILD_OFFSET) ==
2815*4882a593Smuzhiyun MTIP_FTL_REBUILD_MAGIC) {
2816*4882a593Smuzhiyun set_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags);
2817*4882a593Smuzhiyun return MTIP_FTL_REBUILD_MAGIC;
2818*4882a593Smuzhiyun }
2819*4882a593Smuzhiyun mtip_dump_identify(dd->port);
2820*4882a593Smuzhiyun
2821*4882a593Smuzhiyun /* check write protect, over temp and rebuild statuses */
2822*4882a593Smuzhiyun rv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,
2823*4882a593Smuzhiyun dd->port->log_buf,
2824*4882a593Smuzhiyun dd->port->log_buf_dma, 1);
2825*4882a593Smuzhiyun if (rv) {
2826*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2827*4882a593Smuzhiyun "Error in READ LOG EXT (10h) command\n");
2828*4882a593Smuzhiyun /* non-critical error, don't fail the load */
2829*4882a593Smuzhiyun } else {
2830*4882a593Smuzhiyun buf = (unsigned char *)dd->port->log_buf;
2831*4882a593Smuzhiyun if (buf[259] & 0x1) {
2832*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
2833*4882a593Smuzhiyun "Write protect bit is set.\n");
2834*4882a593Smuzhiyun set_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag);
2835*4882a593Smuzhiyun }
2836*4882a593Smuzhiyun if (buf[288] == 0xF7) {
2837*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
2838*4882a593Smuzhiyun "Exceeded Tmax, drive in thermal shutdown.\n");
2839*4882a593Smuzhiyun set_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag);
2840*4882a593Smuzhiyun }
2841*4882a593Smuzhiyun if (buf[288] == 0xBF) {
2842*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
2843*4882a593Smuzhiyun "Drive indicates rebuild has failed.\n");
2844*4882a593Smuzhiyun set_bit(MTIP_DDF_REBUILD_FAILED_BIT, &dd->dd_flag);
2845*4882a593Smuzhiyun }
2846*4882a593Smuzhiyun }
2847*4882a593Smuzhiyun
2848*4882a593Smuzhiyun /* get write protect progess */
2849*4882a593Smuzhiyun memset(&attr242, 0, sizeof(struct smart_attr));
2850*4882a593Smuzhiyun if (mtip_get_smart_attr(dd->port, 242, &attr242))
2851*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2852*4882a593Smuzhiyun "Unable to check write protect progress\n");
2853*4882a593Smuzhiyun else
2854*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
2855*4882a593Smuzhiyun "Write protect progress: %u%% (%u blocks)\n",
2856*4882a593Smuzhiyun attr242.cur, le32_to_cpu(attr242.data));
2857*4882a593Smuzhiyun
2858*4882a593Smuzhiyun return rv;
2859*4882a593Smuzhiyun }
2860*4882a593Smuzhiyun
2861*4882a593Smuzhiyun /*
2862*4882a593Smuzhiyun * Called once for each card.
2863*4882a593Smuzhiyun *
2864*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
2865*4882a593Smuzhiyun *
2866*4882a593Smuzhiyun * return value
2867*4882a593Smuzhiyun * 0 on success, else an error code.
2868*4882a593Smuzhiyun */
mtip_hw_init(struct driver_data * dd)2869*4882a593Smuzhiyun static int mtip_hw_init(struct driver_data *dd)
2870*4882a593Smuzhiyun {
2871*4882a593Smuzhiyun int i;
2872*4882a593Smuzhiyun int rv;
2873*4882a593Smuzhiyun unsigned long timeout, timetaken;
2874*4882a593Smuzhiyun
2875*4882a593Smuzhiyun dd->mmio = pcim_iomap_table(dd->pdev)[MTIP_ABAR];
2876*4882a593Smuzhiyun
2877*4882a593Smuzhiyun mtip_detect_product(dd);
2878*4882a593Smuzhiyun if (dd->product_type == MTIP_PRODUCT_UNKNOWN) {
2879*4882a593Smuzhiyun rv = -EIO;
2880*4882a593Smuzhiyun goto out1;
2881*4882a593Smuzhiyun }
2882*4882a593Smuzhiyun
2883*4882a593Smuzhiyun hba_setup(dd);
2884*4882a593Smuzhiyun
2885*4882a593Smuzhiyun dd->port = kzalloc_node(sizeof(struct mtip_port), GFP_KERNEL,
2886*4882a593Smuzhiyun dd->numa_node);
2887*4882a593Smuzhiyun if (!dd->port) {
2888*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2889*4882a593Smuzhiyun "Memory allocation: port structure\n");
2890*4882a593Smuzhiyun return -ENOMEM;
2891*4882a593Smuzhiyun }
2892*4882a593Smuzhiyun
2893*4882a593Smuzhiyun /* Continue workqueue setup */
2894*4882a593Smuzhiyun for (i = 0; i < MTIP_MAX_SLOT_GROUPS; i++)
2895*4882a593Smuzhiyun dd->work[i].port = dd->port;
2896*4882a593Smuzhiyun
2897*4882a593Smuzhiyun /* Enable unaligned IO constraints for some devices */
2898*4882a593Smuzhiyun if (mtip_device_unaligned_constrained(dd))
2899*4882a593Smuzhiyun dd->unal_qdepth = MTIP_MAX_UNALIGNED_SLOTS;
2900*4882a593Smuzhiyun else
2901*4882a593Smuzhiyun dd->unal_qdepth = 0;
2902*4882a593Smuzhiyun
2903*4882a593Smuzhiyun atomic_set(&dd->port->cmd_slot_unal, dd->unal_qdepth);
2904*4882a593Smuzhiyun
2905*4882a593Smuzhiyun /* Spinlock to prevent concurrent issue */
2906*4882a593Smuzhiyun for (i = 0; i < MTIP_MAX_SLOT_GROUPS; i++)
2907*4882a593Smuzhiyun spin_lock_init(&dd->port->cmd_issue_lock[i]);
2908*4882a593Smuzhiyun
2909*4882a593Smuzhiyun /* Set the port mmio base address. */
2910*4882a593Smuzhiyun dd->port->mmio = dd->mmio + PORT_OFFSET;
2911*4882a593Smuzhiyun dd->port->dd = dd;
2912*4882a593Smuzhiyun
2913*4882a593Smuzhiyun /* DMA allocations */
2914*4882a593Smuzhiyun rv = mtip_dma_alloc(dd);
2915*4882a593Smuzhiyun if (rv < 0)
2916*4882a593Smuzhiyun goto out1;
2917*4882a593Smuzhiyun
2918*4882a593Smuzhiyun /* Setup the pointers to the extended s_active and CI registers. */
2919*4882a593Smuzhiyun for (i = 0; i < dd->slot_groups; i++) {
2920*4882a593Smuzhiyun dd->port->s_active[i] =
2921*4882a593Smuzhiyun dd->port->mmio + i*0x80 + PORT_SCR_ACT;
2922*4882a593Smuzhiyun dd->port->cmd_issue[i] =
2923*4882a593Smuzhiyun dd->port->mmio + i*0x80 + PORT_COMMAND_ISSUE;
2924*4882a593Smuzhiyun dd->port->completed[i] =
2925*4882a593Smuzhiyun dd->port->mmio + i*0x80 + PORT_SDBV;
2926*4882a593Smuzhiyun }
2927*4882a593Smuzhiyun
2928*4882a593Smuzhiyun timetaken = jiffies;
2929*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(30000);
2930*4882a593Smuzhiyun while (((readl(dd->port->mmio + PORT_SCR_STAT) & 0x0F) != 0x03) &&
2931*4882a593Smuzhiyun time_before(jiffies, timeout)) {
2932*4882a593Smuzhiyun mdelay(100);
2933*4882a593Smuzhiyun }
2934*4882a593Smuzhiyun if (unlikely(mtip_check_surprise_removal(dd->pdev))) {
2935*4882a593Smuzhiyun timetaken = jiffies - timetaken;
2936*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2937*4882a593Smuzhiyun "Surprise removal detected at %u ms\n",
2938*4882a593Smuzhiyun jiffies_to_msecs(timetaken));
2939*4882a593Smuzhiyun rv = -ENODEV;
2940*4882a593Smuzhiyun goto out2 ;
2941*4882a593Smuzhiyun }
2942*4882a593Smuzhiyun if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))) {
2943*4882a593Smuzhiyun timetaken = jiffies - timetaken;
2944*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
2945*4882a593Smuzhiyun "Removal detected at %u ms\n",
2946*4882a593Smuzhiyun jiffies_to_msecs(timetaken));
2947*4882a593Smuzhiyun rv = -EFAULT;
2948*4882a593Smuzhiyun goto out2;
2949*4882a593Smuzhiyun }
2950*4882a593Smuzhiyun
2951*4882a593Smuzhiyun /* Conditionally reset the HBA. */
2952*4882a593Smuzhiyun if (!(readl(dd->mmio + HOST_CAP) & HOST_CAP_NZDMA)) {
2953*4882a593Smuzhiyun if (mtip_hba_reset(dd) < 0) {
2954*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2955*4882a593Smuzhiyun "Card did not reset within timeout\n");
2956*4882a593Smuzhiyun rv = -EIO;
2957*4882a593Smuzhiyun goto out2;
2958*4882a593Smuzhiyun }
2959*4882a593Smuzhiyun } else {
2960*4882a593Smuzhiyun /* Clear any pending interrupts on the HBA */
2961*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_IRQ_STAT),
2962*4882a593Smuzhiyun dd->mmio + HOST_IRQ_STAT);
2963*4882a593Smuzhiyun }
2964*4882a593Smuzhiyun
2965*4882a593Smuzhiyun mtip_init_port(dd->port);
2966*4882a593Smuzhiyun mtip_start_port(dd->port);
2967*4882a593Smuzhiyun
2968*4882a593Smuzhiyun /* Setup the ISR and enable interrupts. */
2969*4882a593Smuzhiyun rv = request_irq(dd->pdev->irq, mtip_irq_handler, IRQF_SHARED,
2970*4882a593Smuzhiyun dev_driver_string(&dd->pdev->dev), dd);
2971*4882a593Smuzhiyun if (rv) {
2972*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
2973*4882a593Smuzhiyun "Unable to allocate IRQ %d\n", dd->pdev->irq);
2974*4882a593Smuzhiyun goto out2;
2975*4882a593Smuzhiyun }
2976*4882a593Smuzhiyun irq_set_affinity_hint(dd->pdev->irq, get_cpu_mask(dd->isr_binding));
2977*4882a593Smuzhiyun
2978*4882a593Smuzhiyun /* Enable interrupts on the HBA. */
2979*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
2980*4882a593Smuzhiyun dd->mmio + HOST_CTL);
2981*4882a593Smuzhiyun
2982*4882a593Smuzhiyun init_waitqueue_head(&dd->port->svc_wait);
2983*4882a593Smuzhiyun
2984*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)) {
2985*4882a593Smuzhiyun rv = -EFAULT;
2986*4882a593Smuzhiyun goto out3;
2987*4882a593Smuzhiyun }
2988*4882a593Smuzhiyun
2989*4882a593Smuzhiyun return rv;
2990*4882a593Smuzhiyun
2991*4882a593Smuzhiyun out3:
2992*4882a593Smuzhiyun /* Disable interrupts on the HBA. */
2993*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
2994*4882a593Smuzhiyun dd->mmio + HOST_CTL);
2995*4882a593Smuzhiyun
2996*4882a593Smuzhiyun /* Release the IRQ. */
2997*4882a593Smuzhiyun irq_set_affinity_hint(dd->pdev->irq, NULL);
2998*4882a593Smuzhiyun free_irq(dd->pdev->irq, dd);
2999*4882a593Smuzhiyun
3000*4882a593Smuzhiyun out2:
3001*4882a593Smuzhiyun mtip_deinit_port(dd->port);
3002*4882a593Smuzhiyun mtip_dma_free(dd);
3003*4882a593Smuzhiyun
3004*4882a593Smuzhiyun out1:
3005*4882a593Smuzhiyun /* Free the memory allocated for the for structure. */
3006*4882a593Smuzhiyun kfree(dd->port);
3007*4882a593Smuzhiyun
3008*4882a593Smuzhiyun return rv;
3009*4882a593Smuzhiyun }
3010*4882a593Smuzhiyun
mtip_standby_drive(struct driver_data * dd)3011*4882a593Smuzhiyun static int mtip_standby_drive(struct driver_data *dd)
3012*4882a593Smuzhiyun {
3013*4882a593Smuzhiyun int rv = 0;
3014*4882a593Smuzhiyun
3015*4882a593Smuzhiyun if (dd->sr || !dd->port)
3016*4882a593Smuzhiyun return -ENODEV;
3017*4882a593Smuzhiyun /*
3018*4882a593Smuzhiyun * Send standby immediate (E0h) to the drive so that it
3019*4882a593Smuzhiyun * saves its state.
3020*4882a593Smuzhiyun */
3021*4882a593Smuzhiyun if (!test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags) &&
3022*4882a593Smuzhiyun !test_bit(MTIP_DDF_REBUILD_FAILED_BIT, &dd->dd_flag) &&
3023*4882a593Smuzhiyun !test_bit(MTIP_DDF_SEC_LOCK_BIT, &dd->dd_flag)) {
3024*4882a593Smuzhiyun rv = mtip_standby_immediate(dd->port);
3025*4882a593Smuzhiyun if (rv)
3026*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
3027*4882a593Smuzhiyun "STANDBY IMMEDIATE failed\n");
3028*4882a593Smuzhiyun }
3029*4882a593Smuzhiyun return rv;
3030*4882a593Smuzhiyun }
3031*4882a593Smuzhiyun
3032*4882a593Smuzhiyun /*
3033*4882a593Smuzhiyun * Called to deinitialize an interface.
3034*4882a593Smuzhiyun *
3035*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3036*4882a593Smuzhiyun *
3037*4882a593Smuzhiyun * return value
3038*4882a593Smuzhiyun * 0
3039*4882a593Smuzhiyun */
mtip_hw_exit(struct driver_data * dd)3040*4882a593Smuzhiyun static int mtip_hw_exit(struct driver_data *dd)
3041*4882a593Smuzhiyun {
3042*4882a593Smuzhiyun if (!dd->sr) {
3043*4882a593Smuzhiyun /* de-initialize the port. */
3044*4882a593Smuzhiyun mtip_deinit_port(dd->port);
3045*4882a593Smuzhiyun
3046*4882a593Smuzhiyun /* Disable interrupts on the HBA. */
3047*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
3048*4882a593Smuzhiyun dd->mmio + HOST_CTL);
3049*4882a593Smuzhiyun }
3050*4882a593Smuzhiyun
3051*4882a593Smuzhiyun /* Release the IRQ. */
3052*4882a593Smuzhiyun irq_set_affinity_hint(dd->pdev->irq, NULL);
3053*4882a593Smuzhiyun free_irq(dd->pdev->irq, dd);
3054*4882a593Smuzhiyun msleep(1000);
3055*4882a593Smuzhiyun
3056*4882a593Smuzhiyun /* Free dma regions */
3057*4882a593Smuzhiyun mtip_dma_free(dd);
3058*4882a593Smuzhiyun
3059*4882a593Smuzhiyun /* Free the memory allocated for the for structure. */
3060*4882a593Smuzhiyun kfree(dd->port);
3061*4882a593Smuzhiyun dd->port = NULL;
3062*4882a593Smuzhiyun
3063*4882a593Smuzhiyun return 0;
3064*4882a593Smuzhiyun }
3065*4882a593Smuzhiyun
3066*4882a593Smuzhiyun /*
3067*4882a593Smuzhiyun * Issue a Standby Immediate command to the device.
3068*4882a593Smuzhiyun *
3069*4882a593Smuzhiyun * This function is called by the Block Layer just before the
3070*4882a593Smuzhiyun * system powers off during a shutdown.
3071*4882a593Smuzhiyun *
3072*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3073*4882a593Smuzhiyun *
3074*4882a593Smuzhiyun * return value
3075*4882a593Smuzhiyun * 0
3076*4882a593Smuzhiyun */
mtip_hw_shutdown(struct driver_data * dd)3077*4882a593Smuzhiyun static int mtip_hw_shutdown(struct driver_data *dd)
3078*4882a593Smuzhiyun {
3079*4882a593Smuzhiyun /*
3080*4882a593Smuzhiyun * Send standby immediate (E0h) to the drive so that it
3081*4882a593Smuzhiyun * saves its state.
3082*4882a593Smuzhiyun */
3083*4882a593Smuzhiyun mtip_standby_drive(dd);
3084*4882a593Smuzhiyun
3085*4882a593Smuzhiyun return 0;
3086*4882a593Smuzhiyun }
3087*4882a593Smuzhiyun
3088*4882a593Smuzhiyun /*
3089*4882a593Smuzhiyun * Suspend function
3090*4882a593Smuzhiyun *
3091*4882a593Smuzhiyun * This function is called by the Block Layer just before the
3092*4882a593Smuzhiyun * system hibernates.
3093*4882a593Smuzhiyun *
3094*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3095*4882a593Smuzhiyun *
3096*4882a593Smuzhiyun * return value
3097*4882a593Smuzhiyun * 0 Suspend was successful
3098*4882a593Smuzhiyun * -EFAULT Suspend was not successful
3099*4882a593Smuzhiyun */
mtip_hw_suspend(struct driver_data * dd)3100*4882a593Smuzhiyun static int mtip_hw_suspend(struct driver_data *dd)
3101*4882a593Smuzhiyun {
3102*4882a593Smuzhiyun /*
3103*4882a593Smuzhiyun * Send standby immediate (E0h) to the drive
3104*4882a593Smuzhiyun * so that it saves its state.
3105*4882a593Smuzhiyun */
3106*4882a593Smuzhiyun if (mtip_standby_drive(dd) != 0) {
3107*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
3108*4882a593Smuzhiyun "Failed standby-immediate command\n");
3109*4882a593Smuzhiyun return -EFAULT;
3110*4882a593Smuzhiyun }
3111*4882a593Smuzhiyun
3112*4882a593Smuzhiyun /* Disable interrupts on the HBA.*/
3113*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
3114*4882a593Smuzhiyun dd->mmio + HOST_CTL);
3115*4882a593Smuzhiyun mtip_deinit_port(dd->port);
3116*4882a593Smuzhiyun
3117*4882a593Smuzhiyun return 0;
3118*4882a593Smuzhiyun }
3119*4882a593Smuzhiyun
3120*4882a593Smuzhiyun /*
3121*4882a593Smuzhiyun * Resume function
3122*4882a593Smuzhiyun *
3123*4882a593Smuzhiyun * This function is called by the Block Layer as the
3124*4882a593Smuzhiyun * system resumes.
3125*4882a593Smuzhiyun *
3126*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3127*4882a593Smuzhiyun *
3128*4882a593Smuzhiyun * return value
3129*4882a593Smuzhiyun * 0 Resume was successful
3130*4882a593Smuzhiyun * -EFAULT Resume was not successful
3131*4882a593Smuzhiyun */
mtip_hw_resume(struct driver_data * dd)3132*4882a593Smuzhiyun static int mtip_hw_resume(struct driver_data *dd)
3133*4882a593Smuzhiyun {
3134*4882a593Smuzhiyun /* Perform any needed hardware setup steps */
3135*4882a593Smuzhiyun hba_setup(dd);
3136*4882a593Smuzhiyun
3137*4882a593Smuzhiyun /* Reset the HBA */
3138*4882a593Smuzhiyun if (mtip_hba_reset(dd) != 0) {
3139*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
3140*4882a593Smuzhiyun "Unable to reset the HBA\n");
3141*4882a593Smuzhiyun return -EFAULT;
3142*4882a593Smuzhiyun }
3143*4882a593Smuzhiyun
3144*4882a593Smuzhiyun /*
3145*4882a593Smuzhiyun * Enable the port, DMA engine, and FIS reception specific
3146*4882a593Smuzhiyun * h/w in controller.
3147*4882a593Smuzhiyun */
3148*4882a593Smuzhiyun mtip_init_port(dd->port);
3149*4882a593Smuzhiyun mtip_start_port(dd->port);
3150*4882a593Smuzhiyun
3151*4882a593Smuzhiyun /* Enable interrupts on the HBA.*/
3152*4882a593Smuzhiyun writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
3153*4882a593Smuzhiyun dd->mmio + HOST_CTL);
3154*4882a593Smuzhiyun
3155*4882a593Smuzhiyun return 0;
3156*4882a593Smuzhiyun }
3157*4882a593Smuzhiyun
3158*4882a593Smuzhiyun /*
3159*4882a593Smuzhiyun * Helper function for reusing disk name
3160*4882a593Smuzhiyun * upon hot insertion.
3161*4882a593Smuzhiyun */
rssd_disk_name_format(char * prefix,int index,char * buf,int buflen)3162*4882a593Smuzhiyun static int rssd_disk_name_format(char *prefix,
3163*4882a593Smuzhiyun int index,
3164*4882a593Smuzhiyun char *buf,
3165*4882a593Smuzhiyun int buflen)
3166*4882a593Smuzhiyun {
3167*4882a593Smuzhiyun const int base = 'z' - 'a' + 1;
3168*4882a593Smuzhiyun char *begin = buf + strlen(prefix);
3169*4882a593Smuzhiyun char *end = buf + buflen;
3170*4882a593Smuzhiyun char *p;
3171*4882a593Smuzhiyun int unit;
3172*4882a593Smuzhiyun
3173*4882a593Smuzhiyun p = end - 1;
3174*4882a593Smuzhiyun *p = '\0';
3175*4882a593Smuzhiyun unit = base;
3176*4882a593Smuzhiyun do {
3177*4882a593Smuzhiyun if (p == begin)
3178*4882a593Smuzhiyun return -EINVAL;
3179*4882a593Smuzhiyun *--p = 'a' + (index % unit);
3180*4882a593Smuzhiyun index = (index / unit) - 1;
3181*4882a593Smuzhiyun } while (index >= 0);
3182*4882a593Smuzhiyun
3183*4882a593Smuzhiyun memmove(begin, p, end - p);
3184*4882a593Smuzhiyun memcpy(buf, prefix, strlen(prefix));
3185*4882a593Smuzhiyun
3186*4882a593Smuzhiyun return 0;
3187*4882a593Smuzhiyun }
3188*4882a593Smuzhiyun
3189*4882a593Smuzhiyun /*
3190*4882a593Smuzhiyun * Block layer IOCTL handler.
3191*4882a593Smuzhiyun *
3192*4882a593Smuzhiyun * @dev Pointer to the block_device structure.
3193*4882a593Smuzhiyun * @mode ignored
3194*4882a593Smuzhiyun * @cmd IOCTL command passed from the user application.
3195*4882a593Smuzhiyun * @arg Argument passed from the user application.
3196*4882a593Smuzhiyun *
3197*4882a593Smuzhiyun * return value
3198*4882a593Smuzhiyun * 0 IOCTL completed successfully.
3199*4882a593Smuzhiyun * -ENOTTY IOCTL not supported or invalid driver data
3200*4882a593Smuzhiyun * structure pointer.
3201*4882a593Smuzhiyun */
mtip_block_ioctl(struct block_device * dev,fmode_t mode,unsigned cmd,unsigned long arg)3202*4882a593Smuzhiyun static int mtip_block_ioctl(struct block_device *dev,
3203*4882a593Smuzhiyun fmode_t mode,
3204*4882a593Smuzhiyun unsigned cmd,
3205*4882a593Smuzhiyun unsigned long arg)
3206*4882a593Smuzhiyun {
3207*4882a593Smuzhiyun struct driver_data *dd = dev->bd_disk->private_data;
3208*4882a593Smuzhiyun
3209*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
3210*4882a593Smuzhiyun return -EACCES;
3211*4882a593Smuzhiyun
3212*4882a593Smuzhiyun if (!dd)
3213*4882a593Smuzhiyun return -ENOTTY;
3214*4882a593Smuzhiyun
3215*4882a593Smuzhiyun if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)))
3216*4882a593Smuzhiyun return -ENOTTY;
3217*4882a593Smuzhiyun
3218*4882a593Smuzhiyun switch (cmd) {
3219*4882a593Smuzhiyun case BLKFLSBUF:
3220*4882a593Smuzhiyun return -ENOTTY;
3221*4882a593Smuzhiyun default:
3222*4882a593Smuzhiyun return mtip_hw_ioctl(dd, cmd, arg);
3223*4882a593Smuzhiyun }
3224*4882a593Smuzhiyun }
3225*4882a593Smuzhiyun
3226*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
3227*4882a593Smuzhiyun /*
3228*4882a593Smuzhiyun * Block layer compat IOCTL handler.
3229*4882a593Smuzhiyun *
3230*4882a593Smuzhiyun * @dev Pointer to the block_device structure.
3231*4882a593Smuzhiyun * @mode ignored
3232*4882a593Smuzhiyun * @cmd IOCTL command passed from the user application.
3233*4882a593Smuzhiyun * @arg Argument passed from the user application.
3234*4882a593Smuzhiyun *
3235*4882a593Smuzhiyun * return value
3236*4882a593Smuzhiyun * 0 IOCTL completed successfully.
3237*4882a593Smuzhiyun * -ENOTTY IOCTL not supported or invalid driver data
3238*4882a593Smuzhiyun * structure pointer.
3239*4882a593Smuzhiyun */
mtip_block_compat_ioctl(struct block_device * dev,fmode_t mode,unsigned cmd,unsigned long arg)3240*4882a593Smuzhiyun static int mtip_block_compat_ioctl(struct block_device *dev,
3241*4882a593Smuzhiyun fmode_t mode,
3242*4882a593Smuzhiyun unsigned cmd,
3243*4882a593Smuzhiyun unsigned long arg)
3244*4882a593Smuzhiyun {
3245*4882a593Smuzhiyun struct driver_data *dd = dev->bd_disk->private_data;
3246*4882a593Smuzhiyun
3247*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
3248*4882a593Smuzhiyun return -EACCES;
3249*4882a593Smuzhiyun
3250*4882a593Smuzhiyun if (!dd)
3251*4882a593Smuzhiyun return -ENOTTY;
3252*4882a593Smuzhiyun
3253*4882a593Smuzhiyun if (unlikely(test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)))
3254*4882a593Smuzhiyun return -ENOTTY;
3255*4882a593Smuzhiyun
3256*4882a593Smuzhiyun switch (cmd) {
3257*4882a593Smuzhiyun case BLKFLSBUF:
3258*4882a593Smuzhiyun return -ENOTTY;
3259*4882a593Smuzhiyun case HDIO_DRIVE_TASKFILE: {
3260*4882a593Smuzhiyun struct mtip_compat_ide_task_request_s __user *compat_req_task;
3261*4882a593Smuzhiyun ide_task_request_t req_task;
3262*4882a593Smuzhiyun int compat_tasksize, outtotal, ret;
3263*4882a593Smuzhiyun
3264*4882a593Smuzhiyun compat_tasksize =
3265*4882a593Smuzhiyun sizeof(struct mtip_compat_ide_task_request_s);
3266*4882a593Smuzhiyun
3267*4882a593Smuzhiyun compat_req_task =
3268*4882a593Smuzhiyun (struct mtip_compat_ide_task_request_s __user *) arg;
3269*4882a593Smuzhiyun
3270*4882a593Smuzhiyun if (copy_from_user(&req_task, (void __user *) arg,
3271*4882a593Smuzhiyun compat_tasksize - (2 * sizeof(compat_long_t))))
3272*4882a593Smuzhiyun return -EFAULT;
3273*4882a593Smuzhiyun
3274*4882a593Smuzhiyun if (get_user(req_task.out_size, &compat_req_task->out_size))
3275*4882a593Smuzhiyun return -EFAULT;
3276*4882a593Smuzhiyun
3277*4882a593Smuzhiyun if (get_user(req_task.in_size, &compat_req_task->in_size))
3278*4882a593Smuzhiyun return -EFAULT;
3279*4882a593Smuzhiyun
3280*4882a593Smuzhiyun outtotal = sizeof(struct mtip_compat_ide_task_request_s);
3281*4882a593Smuzhiyun
3282*4882a593Smuzhiyun ret = exec_drive_taskfile(dd, (void __user *) arg,
3283*4882a593Smuzhiyun &req_task, outtotal);
3284*4882a593Smuzhiyun
3285*4882a593Smuzhiyun if (copy_to_user((void __user *) arg, &req_task,
3286*4882a593Smuzhiyun compat_tasksize -
3287*4882a593Smuzhiyun (2 * sizeof(compat_long_t))))
3288*4882a593Smuzhiyun return -EFAULT;
3289*4882a593Smuzhiyun
3290*4882a593Smuzhiyun if (put_user(req_task.out_size, &compat_req_task->out_size))
3291*4882a593Smuzhiyun return -EFAULT;
3292*4882a593Smuzhiyun
3293*4882a593Smuzhiyun if (put_user(req_task.in_size, &compat_req_task->in_size))
3294*4882a593Smuzhiyun return -EFAULT;
3295*4882a593Smuzhiyun
3296*4882a593Smuzhiyun return ret;
3297*4882a593Smuzhiyun }
3298*4882a593Smuzhiyun default:
3299*4882a593Smuzhiyun return mtip_hw_ioctl(dd, cmd, arg);
3300*4882a593Smuzhiyun }
3301*4882a593Smuzhiyun }
3302*4882a593Smuzhiyun #endif
3303*4882a593Smuzhiyun
3304*4882a593Smuzhiyun /*
3305*4882a593Smuzhiyun * Obtain the geometry of the device.
3306*4882a593Smuzhiyun *
3307*4882a593Smuzhiyun * You may think that this function is obsolete, but some applications,
3308*4882a593Smuzhiyun * fdisk for example still used CHS values. This function describes the
3309*4882a593Smuzhiyun * device as having 224 heads and 56 sectors per cylinder. These values are
3310*4882a593Smuzhiyun * chosen so that each cylinder is aligned on a 4KB boundary. Since a
3311*4882a593Smuzhiyun * partition is described in terms of a start and end cylinder this means
3312*4882a593Smuzhiyun * that each partition is also 4KB aligned. Non-aligned partitions adversely
3313*4882a593Smuzhiyun * affects performance.
3314*4882a593Smuzhiyun *
3315*4882a593Smuzhiyun * @dev Pointer to the block_device strucutre.
3316*4882a593Smuzhiyun * @geo Pointer to a hd_geometry structure.
3317*4882a593Smuzhiyun *
3318*4882a593Smuzhiyun * return value
3319*4882a593Smuzhiyun * 0 Operation completed successfully.
3320*4882a593Smuzhiyun * -ENOTTY An error occurred while reading the drive capacity.
3321*4882a593Smuzhiyun */
mtip_block_getgeo(struct block_device * dev,struct hd_geometry * geo)3322*4882a593Smuzhiyun static int mtip_block_getgeo(struct block_device *dev,
3323*4882a593Smuzhiyun struct hd_geometry *geo)
3324*4882a593Smuzhiyun {
3325*4882a593Smuzhiyun struct driver_data *dd = dev->bd_disk->private_data;
3326*4882a593Smuzhiyun sector_t capacity;
3327*4882a593Smuzhiyun
3328*4882a593Smuzhiyun if (!dd)
3329*4882a593Smuzhiyun return -ENOTTY;
3330*4882a593Smuzhiyun
3331*4882a593Smuzhiyun if (!(mtip_hw_get_capacity(dd, &capacity))) {
3332*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
3333*4882a593Smuzhiyun "Could not get drive capacity.\n");
3334*4882a593Smuzhiyun return -ENOTTY;
3335*4882a593Smuzhiyun }
3336*4882a593Smuzhiyun
3337*4882a593Smuzhiyun geo->heads = 224;
3338*4882a593Smuzhiyun geo->sectors = 56;
3339*4882a593Smuzhiyun sector_div(capacity, (geo->heads * geo->sectors));
3340*4882a593Smuzhiyun geo->cylinders = capacity;
3341*4882a593Smuzhiyun return 0;
3342*4882a593Smuzhiyun }
3343*4882a593Smuzhiyun
mtip_block_open(struct block_device * dev,fmode_t mode)3344*4882a593Smuzhiyun static int mtip_block_open(struct block_device *dev, fmode_t mode)
3345*4882a593Smuzhiyun {
3346*4882a593Smuzhiyun struct driver_data *dd;
3347*4882a593Smuzhiyun
3348*4882a593Smuzhiyun if (dev && dev->bd_disk) {
3349*4882a593Smuzhiyun dd = (struct driver_data *) dev->bd_disk->private_data;
3350*4882a593Smuzhiyun
3351*4882a593Smuzhiyun if (dd) {
3352*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVAL_BIT,
3353*4882a593Smuzhiyun &dd->dd_flag)) {
3354*4882a593Smuzhiyun return -ENODEV;
3355*4882a593Smuzhiyun }
3356*4882a593Smuzhiyun return 0;
3357*4882a593Smuzhiyun }
3358*4882a593Smuzhiyun }
3359*4882a593Smuzhiyun return -ENODEV;
3360*4882a593Smuzhiyun }
3361*4882a593Smuzhiyun
mtip_block_release(struct gendisk * disk,fmode_t mode)3362*4882a593Smuzhiyun static void mtip_block_release(struct gendisk *disk, fmode_t mode)
3363*4882a593Smuzhiyun {
3364*4882a593Smuzhiyun }
3365*4882a593Smuzhiyun
3366*4882a593Smuzhiyun /*
3367*4882a593Smuzhiyun * Block device operation function.
3368*4882a593Smuzhiyun *
3369*4882a593Smuzhiyun * This structure contains pointers to the functions required by the block
3370*4882a593Smuzhiyun * layer.
3371*4882a593Smuzhiyun */
3372*4882a593Smuzhiyun static const struct block_device_operations mtip_block_ops = {
3373*4882a593Smuzhiyun .open = mtip_block_open,
3374*4882a593Smuzhiyun .release = mtip_block_release,
3375*4882a593Smuzhiyun .ioctl = mtip_block_ioctl,
3376*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
3377*4882a593Smuzhiyun .compat_ioctl = mtip_block_compat_ioctl,
3378*4882a593Smuzhiyun #endif
3379*4882a593Smuzhiyun .getgeo = mtip_block_getgeo,
3380*4882a593Smuzhiyun .owner = THIS_MODULE
3381*4882a593Smuzhiyun };
3382*4882a593Smuzhiyun
is_se_active(struct driver_data * dd)3383*4882a593Smuzhiyun static inline bool is_se_active(struct driver_data *dd)
3384*4882a593Smuzhiyun {
3385*4882a593Smuzhiyun if (unlikely(test_bit(MTIP_PF_SE_ACTIVE_BIT, &dd->port->flags))) {
3386*4882a593Smuzhiyun if (dd->port->ic_pause_timer) {
3387*4882a593Smuzhiyun unsigned long to = dd->port->ic_pause_timer +
3388*4882a593Smuzhiyun msecs_to_jiffies(1000);
3389*4882a593Smuzhiyun if (time_after(jiffies, to)) {
3390*4882a593Smuzhiyun clear_bit(MTIP_PF_SE_ACTIVE_BIT,
3391*4882a593Smuzhiyun &dd->port->flags);
3392*4882a593Smuzhiyun clear_bit(MTIP_DDF_SEC_LOCK_BIT, &dd->dd_flag);
3393*4882a593Smuzhiyun dd->port->ic_pause_timer = 0;
3394*4882a593Smuzhiyun wake_up_interruptible(&dd->port->svc_wait);
3395*4882a593Smuzhiyun return false;
3396*4882a593Smuzhiyun }
3397*4882a593Smuzhiyun }
3398*4882a593Smuzhiyun return true;
3399*4882a593Smuzhiyun }
3400*4882a593Smuzhiyun return false;
3401*4882a593Smuzhiyun }
3402*4882a593Smuzhiyun
is_stopped(struct driver_data * dd,struct request * rq)3403*4882a593Smuzhiyun static inline bool is_stopped(struct driver_data *dd, struct request *rq)
3404*4882a593Smuzhiyun {
3405*4882a593Smuzhiyun if (likely(!(dd->dd_flag & MTIP_DDF_STOP_IO)))
3406*4882a593Smuzhiyun return false;
3407*4882a593Smuzhiyun
3408*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))
3409*4882a593Smuzhiyun return true;
3410*4882a593Smuzhiyun if (test_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag))
3411*4882a593Smuzhiyun return true;
3412*4882a593Smuzhiyun if (test_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag) &&
3413*4882a593Smuzhiyun rq_data_dir(rq))
3414*4882a593Smuzhiyun return true;
3415*4882a593Smuzhiyun if (test_bit(MTIP_DDF_SEC_LOCK_BIT, &dd->dd_flag))
3416*4882a593Smuzhiyun return true;
3417*4882a593Smuzhiyun if (test_bit(MTIP_DDF_REBUILD_FAILED_BIT, &dd->dd_flag))
3418*4882a593Smuzhiyun return true;
3419*4882a593Smuzhiyun
3420*4882a593Smuzhiyun return false;
3421*4882a593Smuzhiyun }
3422*4882a593Smuzhiyun
mtip_check_unal_depth(struct blk_mq_hw_ctx * hctx,struct request * rq)3423*4882a593Smuzhiyun static bool mtip_check_unal_depth(struct blk_mq_hw_ctx *hctx,
3424*4882a593Smuzhiyun struct request *rq)
3425*4882a593Smuzhiyun {
3426*4882a593Smuzhiyun struct driver_data *dd = hctx->queue->queuedata;
3427*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
3428*4882a593Smuzhiyun
3429*4882a593Smuzhiyun if (rq_data_dir(rq) == READ || !dd->unal_qdepth)
3430*4882a593Smuzhiyun return false;
3431*4882a593Smuzhiyun
3432*4882a593Smuzhiyun /*
3433*4882a593Smuzhiyun * If unaligned depth must be limited on this controller, mark it
3434*4882a593Smuzhiyun * as unaligned if the IO isn't on a 4k boundary (start of length).
3435*4882a593Smuzhiyun */
3436*4882a593Smuzhiyun if (blk_rq_sectors(rq) <= 64) {
3437*4882a593Smuzhiyun if ((blk_rq_pos(rq) & 7) || (blk_rq_sectors(rq) & 7))
3438*4882a593Smuzhiyun cmd->unaligned = 1;
3439*4882a593Smuzhiyun }
3440*4882a593Smuzhiyun
3441*4882a593Smuzhiyun if (cmd->unaligned && atomic_dec_if_positive(&dd->port->cmd_slot_unal) >= 0)
3442*4882a593Smuzhiyun return true;
3443*4882a593Smuzhiyun
3444*4882a593Smuzhiyun return false;
3445*4882a593Smuzhiyun }
3446*4882a593Smuzhiyun
mtip_issue_reserved_cmd(struct blk_mq_hw_ctx * hctx,struct request * rq)3447*4882a593Smuzhiyun static blk_status_t mtip_issue_reserved_cmd(struct blk_mq_hw_ctx *hctx,
3448*4882a593Smuzhiyun struct request *rq)
3449*4882a593Smuzhiyun {
3450*4882a593Smuzhiyun struct driver_data *dd = hctx->queue->queuedata;
3451*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
3452*4882a593Smuzhiyun struct mtip_int_cmd *icmd = cmd->icmd;
3453*4882a593Smuzhiyun struct mtip_cmd_hdr *hdr =
3454*4882a593Smuzhiyun dd->port->command_list + sizeof(struct mtip_cmd_hdr) * rq->tag;
3455*4882a593Smuzhiyun struct mtip_cmd_sg *command_sg;
3456*4882a593Smuzhiyun
3457*4882a593Smuzhiyun if (mtip_commands_active(dd->port))
3458*4882a593Smuzhiyun return BLK_STS_DEV_RESOURCE;
3459*4882a593Smuzhiyun
3460*4882a593Smuzhiyun hdr->ctba = cpu_to_le32(cmd->command_dma & 0xFFFFFFFF);
3461*4882a593Smuzhiyun if (test_bit(MTIP_PF_HOST_CAP_64, &dd->port->flags))
3462*4882a593Smuzhiyun hdr->ctbau = cpu_to_le32((cmd->command_dma >> 16) >> 16);
3463*4882a593Smuzhiyun /* Populate the SG list */
3464*4882a593Smuzhiyun hdr->opts = cpu_to_le32(icmd->opts | icmd->fis_len);
3465*4882a593Smuzhiyun if (icmd->buf_len) {
3466*4882a593Smuzhiyun command_sg = cmd->command + AHCI_CMD_TBL_HDR_SZ;
3467*4882a593Smuzhiyun
3468*4882a593Smuzhiyun command_sg->info = cpu_to_le32((icmd->buf_len-1) & 0x3FFFFF);
3469*4882a593Smuzhiyun command_sg->dba = cpu_to_le32(icmd->buffer & 0xFFFFFFFF);
3470*4882a593Smuzhiyun command_sg->dba_upper =
3471*4882a593Smuzhiyun cpu_to_le32((icmd->buffer >> 16) >> 16);
3472*4882a593Smuzhiyun
3473*4882a593Smuzhiyun hdr->opts |= cpu_to_le32((1 << 16));
3474*4882a593Smuzhiyun }
3475*4882a593Smuzhiyun
3476*4882a593Smuzhiyun /* Populate the command header */
3477*4882a593Smuzhiyun hdr->byte_count = 0;
3478*4882a593Smuzhiyun
3479*4882a593Smuzhiyun blk_mq_start_request(rq);
3480*4882a593Smuzhiyun mtip_issue_non_ncq_command(dd->port, rq->tag);
3481*4882a593Smuzhiyun return 0;
3482*4882a593Smuzhiyun }
3483*4882a593Smuzhiyun
mtip_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)3484*4882a593Smuzhiyun static blk_status_t mtip_queue_rq(struct blk_mq_hw_ctx *hctx,
3485*4882a593Smuzhiyun const struct blk_mq_queue_data *bd)
3486*4882a593Smuzhiyun {
3487*4882a593Smuzhiyun struct driver_data *dd = hctx->queue->queuedata;
3488*4882a593Smuzhiyun struct request *rq = bd->rq;
3489*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
3490*4882a593Smuzhiyun
3491*4882a593Smuzhiyun if (blk_rq_is_passthrough(rq))
3492*4882a593Smuzhiyun return mtip_issue_reserved_cmd(hctx, rq);
3493*4882a593Smuzhiyun
3494*4882a593Smuzhiyun if (unlikely(mtip_check_unal_depth(hctx, rq)))
3495*4882a593Smuzhiyun return BLK_STS_DEV_RESOURCE;
3496*4882a593Smuzhiyun
3497*4882a593Smuzhiyun if (is_se_active(dd) || is_stopped(dd, rq))
3498*4882a593Smuzhiyun return BLK_STS_IOERR;
3499*4882a593Smuzhiyun
3500*4882a593Smuzhiyun blk_mq_start_request(rq);
3501*4882a593Smuzhiyun
3502*4882a593Smuzhiyun mtip_hw_submit_io(dd, rq, cmd, hctx);
3503*4882a593Smuzhiyun return BLK_STS_OK;
3504*4882a593Smuzhiyun }
3505*4882a593Smuzhiyun
mtip_free_cmd(struct blk_mq_tag_set * set,struct request * rq,unsigned int hctx_idx)3506*4882a593Smuzhiyun static void mtip_free_cmd(struct blk_mq_tag_set *set, struct request *rq,
3507*4882a593Smuzhiyun unsigned int hctx_idx)
3508*4882a593Smuzhiyun {
3509*4882a593Smuzhiyun struct driver_data *dd = set->driver_data;
3510*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
3511*4882a593Smuzhiyun
3512*4882a593Smuzhiyun if (!cmd->command)
3513*4882a593Smuzhiyun return;
3514*4882a593Smuzhiyun
3515*4882a593Smuzhiyun dma_free_coherent(&dd->pdev->dev, CMD_DMA_ALLOC_SZ, cmd->command,
3516*4882a593Smuzhiyun cmd->command_dma);
3517*4882a593Smuzhiyun }
3518*4882a593Smuzhiyun
mtip_init_cmd(struct blk_mq_tag_set * set,struct request * rq,unsigned int hctx_idx,unsigned int numa_node)3519*4882a593Smuzhiyun static int mtip_init_cmd(struct blk_mq_tag_set *set, struct request *rq,
3520*4882a593Smuzhiyun unsigned int hctx_idx, unsigned int numa_node)
3521*4882a593Smuzhiyun {
3522*4882a593Smuzhiyun struct driver_data *dd = set->driver_data;
3523*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
3524*4882a593Smuzhiyun
3525*4882a593Smuzhiyun cmd->command = dma_alloc_coherent(&dd->pdev->dev, CMD_DMA_ALLOC_SZ,
3526*4882a593Smuzhiyun &cmd->command_dma, GFP_KERNEL);
3527*4882a593Smuzhiyun if (!cmd->command)
3528*4882a593Smuzhiyun return -ENOMEM;
3529*4882a593Smuzhiyun
3530*4882a593Smuzhiyun sg_init_table(cmd->sg, MTIP_MAX_SG);
3531*4882a593Smuzhiyun return 0;
3532*4882a593Smuzhiyun }
3533*4882a593Smuzhiyun
mtip_cmd_timeout(struct request * req,bool reserved)3534*4882a593Smuzhiyun static enum blk_eh_timer_return mtip_cmd_timeout(struct request *req,
3535*4882a593Smuzhiyun bool reserved)
3536*4882a593Smuzhiyun {
3537*4882a593Smuzhiyun struct driver_data *dd = req->q->queuedata;
3538*4882a593Smuzhiyun
3539*4882a593Smuzhiyun if (reserved) {
3540*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(req);
3541*4882a593Smuzhiyun
3542*4882a593Smuzhiyun cmd->status = BLK_STS_TIMEOUT;
3543*4882a593Smuzhiyun blk_mq_complete_request(req);
3544*4882a593Smuzhiyun return BLK_EH_DONE;
3545*4882a593Smuzhiyun }
3546*4882a593Smuzhiyun
3547*4882a593Smuzhiyun if (test_bit(req->tag, dd->port->cmds_to_issue))
3548*4882a593Smuzhiyun goto exit_handler;
3549*4882a593Smuzhiyun
3550*4882a593Smuzhiyun if (test_and_set_bit(MTIP_PF_TO_ACTIVE_BIT, &dd->port->flags))
3551*4882a593Smuzhiyun goto exit_handler;
3552*4882a593Smuzhiyun
3553*4882a593Smuzhiyun wake_up_interruptible(&dd->port->svc_wait);
3554*4882a593Smuzhiyun exit_handler:
3555*4882a593Smuzhiyun return BLK_EH_RESET_TIMER;
3556*4882a593Smuzhiyun }
3557*4882a593Smuzhiyun
3558*4882a593Smuzhiyun static const struct blk_mq_ops mtip_mq_ops = {
3559*4882a593Smuzhiyun .queue_rq = mtip_queue_rq,
3560*4882a593Smuzhiyun .init_request = mtip_init_cmd,
3561*4882a593Smuzhiyun .exit_request = mtip_free_cmd,
3562*4882a593Smuzhiyun .complete = mtip_softirq_done_fn,
3563*4882a593Smuzhiyun .timeout = mtip_cmd_timeout,
3564*4882a593Smuzhiyun };
3565*4882a593Smuzhiyun
3566*4882a593Smuzhiyun /*
3567*4882a593Smuzhiyun * Block layer initialization function.
3568*4882a593Smuzhiyun *
3569*4882a593Smuzhiyun * This function is called once by the PCI layer for each P320
3570*4882a593Smuzhiyun * device that is connected to the system.
3571*4882a593Smuzhiyun *
3572*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3573*4882a593Smuzhiyun *
3574*4882a593Smuzhiyun * return value
3575*4882a593Smuzhiyun * 0 on success else an error code.
3576*4882a593Smuzhiyun */
mtip_block_initialize(struct driver_data * dd)3577*4882a593Smuzhiyun static int mtip_block_initialize(struct driver_data *dd)
3578*4882a593Smuzhiyun {
3579*4882a593Smuzhiyun int rv = 0, wait_for_rebuild = 0;
3580*4882a593Smuzhiyun sector_t capacity;
3581*4882a593Smuzhiyun unsigned int index = 0;
3582*4882a593Smuzhiyun struct kobject *kobj;
3583*4882a593Smuzhiyun
3584*4882a593Smuzhiyun if (dd->disk)
3585*4882a593Smuzhiyun goto skip_create_disk; /* hw init done, before rebuild */
3586*4882a593Smuzhiyun
3587*4882a593Smuzhiyun if (mtip_hw_init(dd)) {
3588*4882a593Smuzhiyun rv = -EINVAL;
3589*4882a593Smuzhiyun goto protocol_init_error;
3590*4882a593Smuzhiyun }
3591*4882a593Smuzhiyun
3592*4882a593Smuzhiyun dd->disk = alloc_disk_node(MTIP_MAX_MINORS, dd->numa_node);
3593*4882a593Smuzhiyun if (dd->disk == NULL) {
3594*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
3595*4882a593Smuzhiyun "Unable to allocate gendisk structure\n");
3596*4882a593Smuzhiyun rv = -EINVAL;
3597*4882a593Smuzhiyun goto alloc_disk_error;
3598*4882a593Smuzhiyun }
3599*4882a593Smuzhiyun
3600*4882a593Smuzhiyun rv = ida_alloc(&rssd_index_ida, GFP_KERNEL);
3601*4882a593Smuzhiyun if (rv < 0)
3602*4882a593Smuzhiyun goto ida_get_error;
3603*4882a593Smuzhiyun index = rv;
3604*4882a593Smuzhiyun
3605*4882a593Smuzhiyun rv = rssd_disk_name_format("rssd",
3606*4882a593Smuzhiyun index,
3607*4882a593Smuzhiyun dd->disk->disk_name,
3608*4882a593Smuzhiyun DISK_NAME_LEN);
3609*4882a593Smuzhiyun if (rv)
3610*4882a593Smuzhiyun goto disk_index_error;
3611*4882a593Smuzhiyun
3612*4882a593Smuzhiyun dd->disk->major = dd->major;
3613*4882a593Smuzhiyun dd->disk->first_minor = index * MTIP_MAX_MINORS;
3614*4882a593Smuzhiyun dd->disk->minors = MTIP_MAX_MINORS;
3615*4882a593Smuzhiyun dd->disk->fops = &mtip_block_ops;
3616*4882a593Smuzhiyun dd->disk->private_data = dd;
3617*4882a593Smuzhiyun dd->index = index;
3618*4882a593Smuzhiyun
3619*4882a593Smuzhiyun mtip_hw_debugfs_init(dd);
3620*4882a593Smuzhiyun
3621*4882a593Smuzhiyun memset(&dd->tags, 0, sizeof(dd->tags));
3622*4882a593Smuzhiyun dd->tags.ops = &mtip_mq_ops;
3623*4882a593Smuzhiyun dd->tags.nr_hw_queues = 1;
3624*4882a593Smuzhiyun dd->tags.queue_depth = MTIP_MAX_COMMAND_SLOTS;
3625*4882a593Smuzhiyun dd->tags.reserved_tags = 1;
3626*4882a593Smuzhiyun dd->tags.cmd_size = sizeof(struct mtip_cmd);
3627*4882a593Smuzhiyun dd->tags.numa_node = dd->numa_node;
3628*4882a593Smuzhiyun dd->tags.flags = BLK_MQ_F_SHOULD_MERGE;
3629*4882a593Smuzhiyun dd->tags.driver_data = dd;
3630*4882a593Smuzhiyun dd->tags.timeout = MTIP_NCQ_CMD_TIMEOUT_MS;
3631*4882a593Smuzhiyun
3632*4882a593Smuzhiyun rv = blk_mq_alloc_tag_set(&dd->tags);
3633*4882a593Smuzhiyun if (rv) {
3634*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
3635*4882a593Smuzhiyun "Unable to allocate request queue\n");
3636*4882a593Smuzhiyun goto block_queue_alloc_tag_error;
3637*4882a593Smuzhiyun }
3638*4882a593Smuzhiyun
3639*4882a593Smuzhiyun /* Allocate the request queue. */
3640*4882a593Smuzhiyun dd->queue = blk_mq_init_queue(&dd->tags);
3641*4882a593Smuzhiyun if (IS_ERR(dd->queue)) {
3642*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
3643*4882a593Smuzhiyun "Unable to allocate request queue\n");
3644*4882a593Smuzhiyun rv = -ENOMEM;
3645*4882a593Smuzhiyun goto block_queue_alloc_init_error;
3646*4882a593Smuzhiyun }
3647*4882a593Smuzhiyun
3648*4882a593Smuzhiyun dd->disk->queue = dd->queue;
3649*4882a593Smuzhiyun dd->queue->queuedata = dd;
3650*4882a593Smuzhiyun
3651*4882a593Smuzhiyun skip_create_disk:
3652*4882a593Smuzhiyun /* Initialize the protocol layer. */
3653*4882a593Smuzhiyun wait_for_rebuild = mtip_hw_get_identify(dd);
3654*4882a593Smuzhiyun if (wait_for_rebuild < 0) {
3655*4882a593Smuzhiyun dev_err(&dd->pdev->dev,
3656*4882a593Smuzhiyun "Protocol layer initialization failed\n");
3657*4882a593Smuzhiyun rv = -EINVAL;
3658*4882a593Smuzhiyun goto init_hw_cmds_error;
3659*4882a593Smuzhiyun }
3660*4882a593Smuzhiyun
3661*4882a593Smuzhiyun /*
3662*4882a593Smuzhiyun * if rebuild pending, start the service thread, and delay the block
3663*4882a593Smuzhiyun * queue creation and device_add_disk()
3664*4882a593Smuzhiyun */
3665*4882a593Smuzhiyun if (wait_for_rebuild == MTIP_FTL_REBUILD_MAGIC)
3666*4882a593Smuzhiyun goto start_service_thread;
3667*4882a593Smuzhiyun
3668*4882a593Smuzhiyun /* Set device limits. */
3669*4882a593Smuzhiyun blk_queue_flag_set(QUEUE_FLAG_NONROT, dd->queue);
3670*4882a593Smuzhiyun blk_queue_flag_clear(QUEUE_FLAG_ADD_RANDOM, dd->queue);
3671*4882a593Smuzhiyun blk_queue_max_segments(dd->queue, MTIP_MAX_SG);
3672*4882a593Smuzhiyun blk_queue_physical_block_size(dd->queue, 4096);
3673*4882a593Smuzhiyun blk_queue_max_hw_sectors(dd->queue, 0xffff);
3674*4882a593Smuzhiyun blk_queue_max_segment_size(dd->queue, 0x400000);
3675*4882a593Smuzhiyun dma_set_max_seg_size(&dd->pdev->dev, 0x400000);
3676*4882a593Smuzhiyun blk_queue_io_min(dd->queue, 4096);
3677*4882a593Smuzhiyun
3678*4882a593Smuzhiyun /* Set the capacity of the device in 512 byte sectors. */
3679*4882a593Smuzhiyun if (!(mtip_hw_get_capacity(dd, &capacity))) {
3680*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
3681*4882a593Smuzhiyun "Could not read drive capacity\n");
3682*4882a593Smuzhiyun rv = -EIO;
3683*4882a593Smuzhiyun goto read_capacity_error;
3684*4882a593Smuzhiyun }
3685*4882a593Smuzhiyun set_capacity(dd->disk, capacity);
3686*4882a593Smuzhiyun
3687*4882a593Smuzhiyun /* Enable the block device and add it to /dev */
3688*4882a593Smuzhiyun device_add_disk(&dd->pdev->dev, dd->disk, NULL);
3689*4882a593Smuzhiyun
3690*4882a593Smuzhiyun dd->bdev = bdget_disk(dd->disk, 0);
3691*4882a593Smuzhiyun /*
3692*4882a593Smuzhiyun * Now that the disk is active, initialize any sysfs attributes
3693*4882a593Smuzhiyun * managed by the protocol layer.
3694*4882a593Smuzhiyun */
3695*4882a593Smuzhiyun kobj = kobject_get(&disk_to_dev(dd->disk)->kobj);
3696*4882a593Smuzhiyun if (kobj) {
3697*4882a593Smuzhiyun mtip_hw_sysfs_init(dd, kobj);
3698*4882a593Smuzhiyun kobject_put(kobj);
3699*4882a593Smuzhiyun }
3700*4882a593Smuzhiyun
3701*4882a593Smuzhiyun if (dd->mtip_svc_handler) {
3702*4882a593Smuzhiyun set_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag);
3703*4882a593Smuzhiyun return rv; /* service thread created for handling rebuild */
3704*4882a593Smuzhiyun }
3705*4882a593Smuzhiyun
3706*4882a593Smuzhiyun start_service_thread:
3707*4882a593Smuzhiyun dd->mtip_svc_handler = kthread_create_on_node(mtip_service_thread,
3708*4882a593Smuzhiyun dd, dd->numa_node,
3709*4882a593Smuzhiyun "mtip_svc_thd_%02d", index);
3710*4882a593Smuzhiyun
3711*4882a593Smuzhiyun if (IS_ERR(dd->mtip_svc_handler)) {
3712*4882a593Smuzhiyun dev_err(&dd->pdev->dev, "service thread failed to start\n");
3713*4882a593Smuzhiyun dd->mtip_svc_handler = NULL;
3714*4882a593Smuzhiyun rv = -EFAULT;
3715*4882a593Smuzhiyun goto kthread_run_error;
3716*4882a593Smuzhiyun }
3717*4882a593Smuzhiyun wake_up_process(dd->mtip_svc_handler);
3718*4882a593Smuzhiyun if (wait_for_rebuild == MTIP_FTL_REBUILD_MAGIC)
3719*4882a593Smuzhiyun rv = wait_for_rebuild;
3720*4882a593Smuzhiyun
3721*4882a593Smuzhiyun return rv;
3722*4882a593Smuzhiyun
3723*4882a593Smuzhiyun kthread_run_error:
3724*4882a593Smuzhiyun bdput(dd->bdev);
3725*4882a593Smuzhiyun dd->bdev = NULL;
3726*4882a593Smuzhiyun
3727*4882a593Smuzhiyun /* Delete our gendisk. This also removes the device from /dev */
3728*4882a593Smuzhiyun del_gendisk(dd->disk);
3729*4882a593Smuzhiyun
3730*4882a593Smuzhiyun read_capacity_error:
3731*4882a593Smuzhiyun init_hw_cmds_error:
3732*4882a593Smuzhiyun blk_cleanup_queue(dd->queue);
3733*4882a593Smuzhiyun block_queue_alloc_init_error:
3734*4882a593Smuzhiyun blk_mq_free_tag_set(&dd->tags);
3735*4882a593Smuzhiyun block_queue_alloc_tag_error:
3736*4882a593Smuzhiyun mtip_hw_debugfs_exit(dd);
3737*4882a593Smuzhiyun disk_index_error:
3738*4882a593Smuzhiyun ida_free(&rssd_index_ida, index);
3739*4882a593Smuzhiyun
3740*4882a593Smuzhiyun ida_get_error:
3741*4882a593Smuzhiyun put_disk(dd->disk);
3742*4882a593Smuzhiyun
3743*4882a593Smuzhiyun alloc_disk_error:
3744*4882a593Smuzhiyun mtip_hw_exit(dd); /* De-initialize the protocol layer. */
3745*4882a593Smuzhiyun
3746*4882a593Smuzhiyun protocol_init_error:
3747*4882a593Smuzhiyun return rv;
3748*4882a593Smuzhiyun }
3749*4882a593Smuzhiyun
mtip_no_dev_cleanup(struct request * rq,void * data,bool reserv)3750*4882a593Smuzhiyun static bool mtip_no_dev_cleanup(struct request *rq, void *data, bool reserv)
3751*4882a593Smuzhiyun {
3752*4882a593Smuzhiyun struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
3753*4882a593Smuzhiyun
3754*4882a593Smuzhiyun cmd->status = BLK_STS_IOERR;
3755*4882a593Smuzhiyun blk_mq_complete_request(rq);
3756*4882a593Smuzhiyun return true;
3757*4882a593Smuzhiyun }
3758*4882a593Smuzhiyun
3759*4882a593Smuzhiyun /*
3760*4882a593Smuzhiyun * Block layer deinitialization function.
3761*4882a593Smuzhiyun *
3762*4882a593Smuzhiyun * Called by the PCI layer as each P320 device is removed.
3763*4882a593Smuzhiyun *
3764*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3765*4882a593Smuzhiyun *
3766*4882a593Smuzhiyun * return value
3767*4882a593Smuzhiyun * 0
3768*4882a593Smuzhiyun */
mtip_block_remove(struct driver_data * dd)3769*4882a593Smuzhiyun static int mtip_block_remove(struct driver_data *dd)
3770*4882a593Smuzhiyun {
3771*4882a593Smuzhiyun struct kobject *kobj;
3772*4882a593Smuzhiyun
3773*4882a593Smuzhiyun mtip_hw_debugfs_exit(dd);
3774*4882a593Smuzhiyun
3775*4882a593Smuzhiyun if (dd->mtip_svc_handler) {
3776*4882a593Smuzhiyun set_bit(MTIP_PF_SVC_THD_STOP_BIT, &dd->port->flags);
3777*4882a593Smuzhiyun wake_up_interruptible(&dd->port->svc_wait);
3778*4882a593Smuzhiyun kthread_stop(dd->mtip_svc_handler);
3779*4882a593Smuzhiyun }
3780*4882a593Smuzhiyun
3781*4882a593Smuzhiyun /* Clean up the sysfs attributes, if created */
3782*4882a593Smuzhiyun if (test_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag)) {
3783*4882a593Smuzhiyun kobj = kobject_get(&disk_to_dev(dd->disk)->kobj);
3784*4882a593Smuzhiyun if (kobj) {
3785*4882a593Smuzhiyun mtip_hw_sysfs_exit(dd, kobj);
3786*4882a593Smuzhiyun kobject_put(kobj);
3787*4882a593Smuzhiyun }
3788*4882a593Smuzhiyun }
3789*4882a593Smuzhiyun
3790*4882a593Smuzhiyun if (!dd->sr) {
3791*4882a593Smuzhiyun /*
3792*4882a593Smuzhiyun * Explicitly wait here for IOs to quiesce,
3793*4882a593Smuzhiyun * as mtip_standby_drive usually won't wait for IOs.
3794*4882a593Smuzhiyun */
3795*4882a593Smuzhiyun if (!mtip_quiesce_io(dd->port, MTIP_QUIESCE_IO_TIMEOUT_MS))
3796*4882a593Smuzhiyun mtip_standby_drive(dd);
3797*4882a593Smuzhiyun }
3798*4882a593Smuzhiyun else
3799*4882a593Smuzhiyun dev_info(&dd->pdev->dev, "device %s surprise removal\n",
3800*4882a593Smuzhiyun dd->disk->disk_name);
3801*4882a593Smuzhiyun
3802*4882a593Smuzhiyun blk_freeze_queue_start(dd->queue);
3803*4882a593Smuzhiyun blk_mq_quiesce_queue(dd->queue);
3804*4882a593Smuzhiyun blk_mq_tagset_busy_iter(&dd->tags, mtip_no_dev_cleanup, dd);
3805*4882a593Smuzhiyun blk_mq_unquiesce_queue(dd->queue);
3806*4882a593Smuzhiyun
3807*4882a593Smuzhiyun /*
3808*4882a593Smuzhiyun * Delete our gendisk structure. This also removes the device
3809*4882a593Smuzhiyun * from /dev
3810*4882a593Smuzhiyun */
3811*4882a593Smuzhiyun if (dd->bdev) {
3812*4882a593Smuzhiyun bdput(dd->bdev);
3813*4882a593Smuzhiyun dd->bdev = NULL;
3814*4882a593Smuzhiyun }
3815*4882a593Smuzhiyun if (dd->disk) {
3816*4882a593Smuzhiyun if (test_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag))
3817*4882a593Smuzhiyun del_gendisk(dd->disk);
3818*4882a593Smuzhiyun if (dd->disk->queue) {
3819*4882a593Smuzhiyun blk_cleanup_queue(dd->queue);
3820*4882a593Smuzhiyun blk_mq_free_tag_set(&dd->tags);
3821*4882a593Smuzhiyun dd->queue = NULL;
3822*4882a593Smuzhiyun }
3823*4882a593Smuzhiyun put_disk(dd->disk);
3824*4882a593Smuzhiyun }
3825*4882a593Smuzhiyun dd->disk = NULL;
3826*4882a593Smuzhiyun
3827*4882a593Smuzhiyun ida_free(&rssd_index_ida, dd->index);
3828*4882a593Smuzhiyun
3829*4882a593Smuzhiyun /* De-initialize the protocol layer. */
3830*4882a593Smuzhiyun mtip_hw_exit(dd);
3831*4882a593Smuzhiyun
3832*4882a593Smuzhiyun return 0;
3833*4882a593Smuzhiyun }
3834*4882a593Smuzhiyun
3835*4882a593Smuzhiyun /*
3836*4882a593Smuzhiyun * Function called by the PCI layer when just before the
3837*4882a593Smuzhiyun * machine shuts down.
3838*4882a593Smuzhiyun *
3839*4882a593Smuzhiyun * If a protocol layer shutdown function is present it will be called
3840*4882a593Smuzhiyun * by this function.
3841*4882a593Smuzhiyun *
3842*4882a593Smuzhiyun * @dd Pointer to the driver data structure.
3843*4882a593Smuzhiyun *
3844*4882a593Smuzhiyun * return value
3845*4882a593Smuzhiyun * 0
3846*4882a593Smuzhiyun */
mtip_block_shutdown(struct driver_data * dd)3847*4882a593Smuzhiyun static int mtip_block_shutdown(struct driver_data *dd)
3848*4882a593Smuzhiyun {
3849*4882a593Smuzhiyun mtip_hw_shutdown(dd);
3850*4882a593Smuzhiyun
3851*4882a593Smuzhiyun /* Delete our gendisk structure, and cleanup the blk queue. */
3852*4882a593Smuzhiyun if (dd->disk) {
3853*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
3854*4882a593Smuzhiyun "Shutting down %s ...\n", dd->disk->disk_name);
3855*4882a593Smuzhiyun
3856*4882a593Smuzhiyun if (test_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag))
3857*4882a593Smuzhiyun del_gendisk(dd->disk);
3858*4882a593Smuzhiyun if (dd->disk->queue) {
3859*4882a593Smuzhiyun blk_cleanup_queue(dd->queue);
3860*4882a593Smuzhiyun blk_mq_free_tag_set(&dd->tags);
3861*4882a593Smuzhiyun }
3862*4882a593Smuzhiyun put_disk(dd->disk);
3863*4882a593Smuzhiyun dd->disk = NULL;
3864*4882a593Smuzhiyun dd->queue = NULL;
3865*4882a593Smuzhiyun }
3866*4882a593Smuzhiyun
3867*4882a593Smuzhiyun ida_free(&rssd_index_ida, dd->index);
3868*4882a593Smuzhiyun return 0;
3869*4882a593Smuzhiyun }
3870*4882a593Smuzhiyun
mtip_block_suspend(struct driver_data * dd)3871*4882a593Smuzhiyun static int mtip_block_suspend(struct driver_data *dd)
3872*4882a593Smuzhiyun {
3873*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
3874*4882a593Smuzhiyun "Suspending %s ...\n", dd->disk->disk_name);
3875*4882a593Smuzhiyun mtip_hw_suspend(dd);
3876*4882a593Smuzhiyun return 0;
3877*4882a593Smuzhiyun }
3878*4882a593Smuzhiyun
mtip_block_resume(struct driver_data * dd)3879*4882a593Smuzhiyun static int mtip_block_resume(struct driver_data *dd)
3880*4882a593Smuzhiyun {
3881*4882a593Smuzhiyun dev_info(&dd->pdev->dev, "Resuming %s ...\n",
3882*4882a593Smuzhiyun dd->disk->disk_name);
3883*4882a593Smuzhiyun mtip_hw_resume(dd);
3884*4882a593Smuzhiyun return 0;
3885*4882a593Smuzhiyun }
3886*4882a593Smuzhiyun
drop_cpu(int cpu)3887*4882a593Smuzhiyun static void drop_cpu(int cpu)
3888*4882a593Smuzhiyun {
3889*4882a593Smuzhiyun cpu_use[cpu]--;
3890*4882a593Smuzhiyun }
3891*4882a593Smuzhiyun
get_least_used_cpu_on_node(int node)3892*4882a593Smuzhiyun static int get_least_used_cpu_on_node(int node)
3893*4882a593Smuzhiyun {
3894*4882a593Smuzhiyun int cpu, least_used_cpu, least_cnt;
3895*4882a593Smuzhiyun const struct cpumask *node_mask;
3896*4882a593Smuzhiyun
3897*4882a593Smuzhiyun node_mask = cpumask_of_node(node);
3898*4882a593Smuzhiyun least_used_cpu = cpumask_first(node_mask);
3899*4882a593Smuzhiyun least_cnt = cpu_use[least_used_cpu];
3900*4882a593Smuzhiyun cpu = least_used_cpu;
3901*4882a593Smuzhiyun
3902*4882a593Smuzhiyun for_each_cpu(cpu, node_mask) {
3903*4882a593Smuzhiyun if (cpu_use[cpu] < least_cnt) {
3904*4882a593Smuzhiyun least_used_cpu = cpu;
3905*4882a593Smuzhiyun least_cnt = cpu_use[cpu];
3906*4882a593Smuzhiyun }
3907*4882a593Smuzhiyun }
3908*4882a593Smuzhiyun cpu_use[least_used_cpu]++;
3909*4882a593Smuzhiyun return least_used_cpu;
3910*4882a593Smuzhiyun }
3911*4882a593Smuzhiyun
3912*4882a593Smuzhiyun /* Helper for selecting a node in round robin mode */
mtip_get_next_rr_node(void)3913*4882a593Smuzhiyun static inline int mtip_get_next_rr_node(void)
3914*4882a593Smuzhiyun {
3915*4882a593Smuzhiyun static int next_node = NUMA_NO_NODE;
3916*4882a593Smuzhiyun
3917*4882a593Smuzhiyun if (next_node == NUMA_NO_NODE) {
3918*4882a593Smuzhiyun next_node = first_online_node;
3919*4882a593Smuzhiyun return next_node;
3920*4882a593Smuzhiyun }
3921*4882a593Smuzhiyun
3922*4882a593Smuzhiyun next_node = next_online_node(next_node);
3923*4882a593Smuzhiyun if (next_node == MAX_NUMNODES)
3924*4882a593Smuzhiyun next_node = first_online_node;
3925*4882a593Smuzhiyun return next_node;
3926*4882a593Smuzhiyun }
3927*4882a593Smuzhiyun
3928*4882a593Smuzhiyun static DEFINE_HANDLER(0);
3929*4882a593Smuzhiyun static DEFINE_HANDLER(1);
3930*4882a593Smuzhiyun static DEFINE_HANDLER(2);
3931*4882a593Smuzhiyun static DEFINE_HANDLER(3);
3932*4882a593Smuzhiyun static DEFINE_HANDLER(4);
3933*4882a593Smuzhiyun static DEFINE_HANDLER(5);
3934*4882a593Smuzhiyun static DEFINE_HANDLER(6);
3935*4882a593Smuzhiyun static DEFINE_HANDLER(7);
3936*4882a593Smuzhiyun
mtip_disable_link_opts(struct driver_data * dd,struct pci_dev * pdev)3937*4882a593Smuzhiyun static void mtip_disable_link_opts(struct driver_data *dd, struct pci_dev *pdev)
3938*4882a593Smuzhiyun {
3939*4882a593Smuzhiyun int pos;
3940*4882a593Smuzhiyun unsigned short pcie_dev_ctrl;
3941*4882a593Smuzhiyun
3942*4882a593Smuzhiyun pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3943*4882a593Smuzhiyun if (pos) {
3944*4882a593Smuzhiyun pci_read_config_word(pdev,
3945*4882a593Smuzhiyun pos + PCI_EXP_DEVCTL,
3946*4882a593Smuzhiyun &pcie_dev_ctrl);
3947*4882a593Smuzhiyun if (pcie_dev_ctrl & (1 << 11) ||
3948*4882a593Smuzhiyun pcie_dev_ctrl & (1 << 4)) {
3949*4882a593Smuzhiyun dev_info(&dd->pdev->dev,
3950*4882a593Smuzhiyun "Disabling ERO/No-Snoop on bridge device %04x:%04x\n",
3951*4882a593Smuzhiyun pdev->vendor, pdev->device);
3952*4882a593Smuzhiyun pcie_dev_ctrl &= ~(PCI_EXP_DEVCTL_NOSNOOP_EN |
3953*4882a593Smuzhiyun PCI_EXP_DEVCTL_RELAX_EN);
3954*4882a593Smuzhiyun pci_write_config_word(pdev,
3955*4882a593Smuzhiyun pos + PCI_EXP_DEVCTL,
3956*4882a593Smuzhiyun pcie_dev_ctrl);
3957*4882a593Smuzhiyun }
3958*4882a593Smuzhiyun }
3959*4882a593Smuzhiyun }
3960*4882a593Smuzhiyun
mtip_fix_ero_nosnoop(struct driver_data * dd,struct pci_dev * pdev)3961*4882a593Smuzhiyun static void mtip_fix_ero_nosnoop(struct driver_data *dd, struct pci_dev *pdev)
3962*4882a593Smuzhiyun {
3963*4882a593Smuzhiyun /*
3964*4882a593Smuzhiyun * This workaround is specific to AMD/ATI chipset with a PCI upstream
3965*4882a593Smuzhiyun * device with device id 0x5aXX
3966*4882a593Smuzhiyun */
3967*4882a593Smuzhiyun if (pdev->bus && pdev->bus->self) {
3968*4882a593Smuzhiyun if (pdev->bus->self->vendor == PCI_VENDOR_ID_ATI &&
3969*4882a593Smuzhiyun ((pdev->bus->self->device & 0xff00) == 0x5a00)) {
3970*4882a593Smuzhiyun mtip_disable_link_opts(dd, pdev->bus->self);
3971*4882a593Smuzhiyun } else {
3972*4882a593Smuzhiyun /* Check further up the topology */
3973*4882a593Smuzhiyun struct pci_dev *parent_dev = pdev->bus->self;
3974*4882a593Smuzhiyun if (parent_dev->bus &&
3975*4882a593Smuzhiyun parent_dev->bus->parent &&
3976*4882a593Smuzhiyun parent_dev->bus->parent->self &&
3977*4882a593Smuzhiyun parent_dev->bus->parent->self->vendor ==
3978*4882a593Smuzhiyun PCI_VENDOR_ID_ATI &&
3979*4882a593Smuzhiyun (parent_dev->bus->parent->self->device &
3980*4882a593Smuzhiyun 0xff00) == 0x5a00) {
3981*4882a593Smuzhiyun mtip_disable_link_opts(dd,
3982*4882a593Smuzhiyun parent_dev->bus->parent->self);
3983*4882a593Smuzhiyun }
3984*4882a593Smuzhiyun }
3985*4882a593Smuzhiyun }
3986*4882a593Smuzhiyun }
3987*4882a593Smuzhiyun
3988*4882a593Smuzhiyun /*
3989*4882a593Smuzhiyun * Called for each supported PCI device detected.
3990*4882a593Smuzhiyun *
3991*4882a593Smuzhiyun * This function allocates the private data structure, enables the
3992*4882a593Smuzhiyun * PCI device and then calls the block layer initialization function.
3993*4882a593Smuzhiyun *
3994*4882a593Smuzhiyun * return value
3995*4882a593Smuzhiyun * 0 on success else an error code.
3996*4882a593Smuzhiyun */
mtip_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3997*4882a593Smuzhiyun static int mtip_pci_probe(struct pci_dev *pdev,
3998*4882a593Smuzhiyun const struct pci_device_id *ent)
3999*4882a593Smuzhiyun {
4000*4882a593Smuzhiyun int rv = 0;
4001*4882a593Smuzhiyun struct driver_data *dd = NULL;
4002*4882a593Smuzhiyun char cpu_list[256];
4003*4882a593Smuzhiyun const struct cpumask *node_mask;
4004*4882a593Smuzhiyun int cpu, i = 0, j = 0;
4005*4882a593Smuzhiyun int my_node = NUMA_NO_NODE;
4006*4882a593Smuzhiyun unsigned long flags;
4007*4882a593Smuzhiyun
4008*4882a593Smuzhiyun /* Allocate memory for this devices private data. */
4009*4882a593Smuzhiyun my_node = pcibus_to_node(pdev->bus);
4010*4882a593Smuzhiyun if (my_node != NUMA_NO_NODE) {
4011*4882a593Smuzhiyun if (!node_online(my_node))
4012*4882a593Smuzhiyun my_node = mtip_get_next_rr_node();
4013*4882a593Smuzhiyun } else {
4014*4882a593Smuzhiyun dev_info(&pdev->dev, "Kernel not reporting proximity, choosing a node\n");
4015*4882a593Smuzhiyun my_node = mtip_get_next_rr_node();
4016*4882a593Smuzhiyun }
4017*4882a593Smuzhiyun dev_info(&pdev->dev, "NUMA node %d (closest: %d,%d, probe on %d:%d)\n",
4018*4882a593Smuzhiyun my_node, pcibus_to_node(pdev->bus), dev_to_node(&pdev->dev),
4019*4882a593Smuzhiyun cpu_to_node(raw_smp_processor_id()), raw_smp_processor_id());
4020*4882a593Smuzhiyun
4021*4882a593Smuzhiyun dd = kzalloc_node(sizeof(struct driver_data), GFP_KERNEL, my_node);
4022*4882a593Smuzhiyun if (dd == NULL) {
4023*4882a593Smuzhiyun dev_err(&pdev->dev,
4024*4882a593Smuzhiyun "Unable to allocate memory for driver data\n");
4025*4882a593Smuzhiyun return -ENOMEM;
4026*4882a593Smuzhiyun }
4027*4882a593Smuzhiyun
4028*4882a593Smuzhiyun /* Attach the private data to this PCI device. */
4029*4882a593Smuzhiyun pci_set_drvdata(pdev, dd);
4030*4882a593Smuzhiyun
4031*4882a593Smuzhiyun rv = pcim_enable_device(pdev);
4032*4882a593Smuzhiyun if (rv < 0) {
4033*4882a593Smuzhiyun dev_err(&pdev->dev, "Unable to enable device\n");
4034*4882a593Smuzhiyun goto iomap_err;
4035*4882a593Smuzhiyun }
4036*4882a593Smuzhiyun
4037*4882a593Smuzhiyun /* Map BAR5 to memory. */
4038*4882a593Smuzhiyun rv = pcim_iomap_regions(pdev, 1 << MTIP_ABAR, MTIP_DRV_NAME);
4039*4882a593Smuzhiyun if (rv < 0) {
4040*4882a593Smuzhiyun dev_err(&pdev->dev, "Unable to map regions\n");
4041*4882a593Smuzhiyun goto iomap_err;
4042*4882a593Smuzhiyun }
4043*4882a593Smuzhiyun
4044*4882a593Smuzhiyun rv = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4045*4882a593Smuzhiyun if (rv) {
4046*4882a593Smuzhiyun dev_warn(&pdev->dev, "64-bit DMA enable failed\n");
4047*4882a593Smuzhiyun goto setmask_err;
4048*4882a593Smuzhiyun }
4049*4882a593Smuzhiyun
4050*4882a593Smuzhiyun /* Copy the info we may need later into the private data structure. */
4051*4882a593Smuzhiyun dd->major = mtip_major;
4052*4882a593Smuzhiyun dd->instance = instance;
4053*4882a593Smuzhiyun dd->pdev = pdev;
4054*4882a593Smuzhiyun dd->numa_node = my_node;
4055*4882a593Smuzhiyun
4056*4882a593Smuzhiyun INIT_LIST_HEAD(&dd->online_list);
4057*4882a593Smuzhiyun INIT_LIST_HEAD(&dd->remove_list);
4058*4882a593Smuzhiyun
4059*4882a593Smuzhiyun memset(dd->workq_name, 0, 32);
4060*4882a593Smuzhiyun snprintf(dd->workq_name, 31, "mtipq%d", dd->instance);
4061*4882a593Smuzhiyun
4062*4882a593Smuzhiyun dd->isr_workq = create_workqueue(dd->workq_name);
4063*4882a593Smuzhiyun if (!dd->isr_workq) {
4064*4882a593Smuzhiyun dev_warn(&pdev->dev, "Can't create wq %d\n", dd->instance);
4065*4882a593Smuzhiyun rv = -ENOMEM;
4066*4882a593Smuzhiyun goto setmask_err;
4067*4882a593Smuzhiyun }
4068*4882a593Smuzhiyun
4069*4882a593Smuzhiyun memset(cpu_list, 0, sizeof(cpu_list));
4070*4882a593Smuzhiyun
4071*4882a593Smuzhiyun node_mask = cpumask_of_node(dd->numa_node);
4072*4882a593Smuzhiyun if (!cpumask_empty(node_mask)) {
4073*4882a593Smuzhiyun for_each_cpu(cpu, node_mask)
4074*4882a593Smuzhiyun {
4075*4882a593Smuzhiyun snprintf(&cpu_list[j], 256 - j, "%d ", cpu);
4076*4882a593Smuzhiyun j = strlen(cpu_list);
4077*4882a593Smuzhiyun }
4078*4882a593Smuzhiyun
4079*4882a593Smuzhiyun dev_info(&pdev->dev, "Node %d on package %d has %d cpu(s): %s\n",
4080*4882a593Smuzhiyun dd->numa_node,
4081*4882a593Smuzhiyun topology_physical_package_id(cpumask_first(node_mask)),
4082*4882a593Smuzhiyun nr_cpus_node(dd->numa_node),
4083*4882a593Smuzhiyun cpu_list);
4084*4882a593Smuzhiyun } else
4085*4882a593Smuzhiyun dev_dbg(&pdev->dev, "mtip32xx: node_mask empty\n");
4086*4882a593Smuzhiyun
4087*4882a593Smuzhiyun dd->isr_binding = get_least_used_cpu_on_node(dd->numa_node);
4088*4882a593Smuzhiyun dev_info(&pdev->dev, "Initial IRQ binding node:cpu %d:%d\n",
4089*4882a593Smuzhiyun cpu_to_node(dd->isr_binding), dd->isr_binding);
4090*4882a593Smuzhiyun
4091*4882a593Smuzhiyun /* first worker context always runs in ISR */
4092*4882a593Smuzhiyun dd->work[0].cpu_binding = dd->isr_binding;
4093*4882a593Smuzhiyun dd->work[1].cpu_binding = get_least_used_cpu_on_node(dd->numa_node);
4094*4882a593Smuzhiyun dd->work[2].cpu_binding = get_least_used_cpu_on_node(dd->numa_node);
4095*4882a593Smuzhiyun dd->work[3].cpu_binding = dd->work[0].cpu_binding;
4096*4882a593Smuzhiyun dd->work[4].cpu_binding = dd->work[1].cpu_binding;
4097*4882a593Smuzhiyun dd->work[5].cpu_binding = dd->work[2].cpu_binding;
4098*4882a593Smuzhiyun dd->work[6].cpu_binding = dd->work[2].cpu_binding;
4099*4882a593Smuzhiyun dd->work[7].cpu_binding = dd->work[1].cpu_binding;
4100*4882a593Smuzhiyun
4101*4882a593Smuzhiyun /* Log the bindings */
4102*4882a593Smuzhiyun for_each_present_cpu(cpu) {
4103*4882a593Smuzhiyun memset(cpu_list, 0, sizeof(cpu_list));
4104*4882a593Smuzhiyun for (i = 0, j = 0; i < MTIP_MAX_SLOT_GROUPS; i++) {
4105*4882a593Smuzhiyun if (dd->work[i].cpu_binding == cpu) {
4106*4882a593Smuzhiyun snprintf(&cpu_list[j], 256 - j, "%d ", i);
4107*4882a593Smuzhiyun j = strlen(cpu_list);
4108*4882a593Smuzhiyun }
4109*4882a593Smuzhiyun }
4110*4882a593Smuzhiyun if (j)
4111*4882a593Smuzhiyun dev_info(&pdev->dev, "CPU %d: WQs %s\n", cpu, cpu_list);
4112*4882a593Smuzhiyun }
4113*4882a593Smuzhiyun
4114*4882a593Smuzhiyun INIT_WORK(&dd->work[0].work, mtip_workq_sdbf0);
4115*4882a593Smuzhiyun INIT_WORK(&dd->work[1].work, mtip_workq_sdbf1);
4116*4882a593Smuzhiyun INIT_WORK(&dd->work[2].work, mtip_workq_sdbf2);
4117*4882a593Smuzhiyun INIT_WORK(&dd->work[3].work, mtip_workq_sdbf3);
4118*4882a593Smuzhiyun INIT_WORK(&dd->work[4].work, mtip_workq_sdbf4);
4119*4882a593Smuzhiyun INIT_WORK(&dd->work[5].work, mtip_workq_sdbf5);
4120*4882a593Smuzhiyun INIT_WORK(&dd->work[6].work, mtip_workq_sdbf6);
4121*4882a593Smuzhiyun INIT_WORK(&dd->work[7].work, mtip_workq_sdbf7);
4122*4882a593Smuzhiyun
4123*4882a593Smuzhiyun pci_set_master(pdev);
4124*4882a593Smuzhiyun rv = pci_enable_msi(pdev);
4125*4882a593Smuzhiyun if (rv) {
4126*4882a593Smuzhiyun dev_warn(&pdev->dev,
4127*4882a593Smuzhiyun "Unable to enable MSI interrupt.\n");
4128*4882a593Smuzhiyun goto msi_initialize_err;
4129*4882a593Smuzhiyun }
4130*4882a593Smuzhiyun
4131*4882a593Smuzhiyun mtip_fix_ero_nosnoop(dd, pdev);
4132*4882a593Smuzhiyun
4133*4882a593Smuzhiyun /* Initialize the block layer. */
4134*4882a593Smuzhiyun rv = mtip_block_initialize(dd);
4135*4882a593Smuzhiyun if (rv < 0) {
4136*4882a593Smuzhiyun dev_err(&pdev->dev,
4137*4882a593Smuzhiyun "Unable to initialize block layer\n");
4138*4882a593Smuzhiyun goto block_initialize_err;
4139*4882a593Smuzhiyun }
4140*4882a593Smuzhiyun
4141*4882a593Smuzhiyun /*
4142*4882a593Smuzhiyun * Increment the instance count so that each device has a unique
4143*4882a593Smuzhiyun * instance number.
4144*4882a593Smuzhiyun */
4145*4882a593Smuzhiyun instance++;
4146*4882a593Smuzhiyun if (rv != MTIP_FTL_REBUILD_MAGIC)
4147*4882a593Smuzhiyun set_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag);
4148*4882a593Smuzhiyun else
4149*4882a593Smuzhiyun rv = 0; /* device in rebuild state, return 0 from probe */
4150*4882a593Smuzhiyun
4151*4882a593Smuzhiyun /* Add to online list even if in ftl rebuild */
4152*4882a593Smuzhiyun spin_lock_irqsave(&dev_lock, flags);
4153*4882a593Smuzhiyun list_add(&dd->online_list, &online_list);
4154*4882a593Smuzhiyun spin_unlock_irqrestore(&dev_lock, flags);
4155*4882a593Smuzhiyun
4156*4882a593Smuzhiyun goto done;
4157*4882a593Smuzhiyun
4158*4882a593Smuzhiyun block_initialize_err:
4159*4882a593Smuzhiyun pci_disable_msi(pdev);
4160*4882a593Smuzhiyun
4161*4882a593Smuzhiyun msi_initialize_err:
4162*4882a593Smuzhiyun if (dd->isr_workq) {
4163*4882a593Smuzhiyun flush_workqueue(dd->isr_workq);
4164*4882a593Smuzhiyun destroy_workqueue(dd->isr_workq);
4165*4882a593Smuzhiyun drop_cpu(dd->work[0].cpu_binding);
4166*4882a593Smuzhiyun drop_cpu(dd->work[1].cpu_binding);
4167*4882a593Smuzhiyun drop_cpu(dd->work[2].cpu_binding);
4168*4882a593Smuzhiyun }
4169*4882a593Smuzhiyun setmask_err:
4170*4882a593Smuzhiyun pcim_iounmap_regions(pdev, 1 << MTIP_ABAR);
4171*4882a593Smuzhiyun
4172*4882a593Smuzhiyun iomap_err:
4173*4882a593Smuzhiyun kfree(dd);
4174*4882a593Smuzhiyun pci_set_drvdata(pdev, NULL);
4175*4882a593Smuzhiyun return rv;
4176*4882a593Smuzhiyun done:
4177*4882a593Smuzhiyun return rv;
4178*4882a593Smuzhiyun }
4179*4882a593Smuzhiyun
4180*4882a593Smuzhiyun /*
4181*4882a593Smuzhiyun * Called for each probed device when the device is removed or the
4182*4882a593Smuzhiyun * driver is unloaded.
4183*4882a593Smuzhiyun *
4184*4882a593Smuzhiyun * return value
4185*4882a593Smuzhiyun * None
4186*4882a593Smuzhiyun */
mtip_pci_remove(struct pci_dev * pdev)4187*4882a593Smuzhiyun static void mtip_pci_remove(struct pci_dev *pdev)
4188*4882a593Smuzhiyun {
4189*4882a593Smuzhiyun struct driver_data *dd = pci_get_drvdata(pdev);
4190*4882a593Smuzhiyun unsigned long flags, to;
4191*4882a593Smuzhiyun
4192*4882a593Smuzhiyun set_bit(MTIP_DDF_REMOVAL_BIT, &dd->dd_flag);
4193*4882a593Smuzhiyun
4194*4882a593Smuzhiyun spin_lock_irqsave(&dev_lock, flags);
4195*4882a593Smuzhiyun list_del_init(&dd->online_list);
4196*4882a593Smuzhiyun list_add(&dd->remove_list, &removing_list);
4197*4882a593Smuzhiyun spin_unlock_irqrestore(&dev_lock, flags);
4198*4882a593Smuzhiyun
4199*4882a593Smuzhiyun mtip_check_surprise_removal(pdev);
4200*4882a593Smuzhiyun synchronize_irq(dd->pdev->irq);
4201*4882a593Smuzhiyun
4202*4882a593Smuzhiyun /* Spin until workers are done */
4203*4882a593Smuzhiyun to = jiffies + msecs_to_jiffies(4000);
4204*4882a593Smuzhiyun do {
4205*4882a593Smuzhiyun msleep(20);
4206*4882a593Smuzhiyun } while (atomic_read(&dd->irq_workers_active) != 0 &&
4207*4882a593Smuzhiyun time_before(jiffies, to));
4208*4882a593Smuzhiyun
4209*4882a593Smuzhiyun if (!dd->sr)
4210*4882a593Smuzhiyun fsync_bdev(dd->bdev);
4211*4882a593Smuzhiyun
4212*4882a593Smuzhiyun if (atomic_read(&dd->irq_workers_active) != 0) {
4213*4882a593Smuzhiyun dev_warn(&dd->pdev->dev,
4214*4882a593Smuzhiyun "Completion workers still active!\n");
4215*4882a593Smuzhiyun }
4216*4882a593Smuzhiyun
4217*4882a593Smuzhiyun blk_set_queue_dying(dd->queue);
4218*4882a593Smuzhiyun set_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag);
4219*4882a593Smuzhiyun
4220*4882a593Smuzhiyun /* Clean up the block layer. */
4221*4882a593Smuzhiyun mtip_block_remove(dd);
4222*4882a593Smuzhiyun
4223*4882a593Smuzhiyun if (dd->isr_workq) {
4224*4882a593Smuzhiyun flush_workqueue(dd->isr_workq);
4225*4882a593Smuzhiyun destroy_workqueue(dd->isr_workq);
4226*4882a593Smuzhiyun drop_cpu(dd->work[0].cpu_binding);
4227*4882a593Smuzhiyun drop_cpu(dd->work[1].cpu_binding);
4228*4882a593Smuzhiyun drop_cpu(dd->work[2].cpu_binding);
4229*4882a593Smuzhiyun }
4230*4882a593Smuzhiyun
4231*4882a593Smuzhiyun pci_disable_msi(pdev);
4232*4882a593Smuzhiyun
4233*4882a593Smuzhiyun spin_lock_irqsave(&dev_lock, flags);
4234*4882a593Smuzhiyun list_del_init(&dd->remove_list);
4235*4882a593Smuzhiyun spin_unlock_irqrestore(&dev_lock, flags);
4236*4882a593Smuzhiyun
4237*4882a593Smuzhiyun kfree(dd);
4238*4882a593Smuzhiyun
4239*4882a593Smuzhiyun pcim_iounmap_regions(pdev, 1 << MTIP_ABAR);
4240*4882a593Smuzhiyun pci_set_drvdata(pdev, NULL);
4241*4882a593Smuzhiyun }
4242*4882a593Smuzhiyun
4243*4882a593Smuzhiyun /*
4244*4882a593Smuzhiyun * Called for each probed device when the device is suspended.
4245*4882a593Smuzhiyun *
4246*4882a593Smuzhiyun * return value
4247*4882a593Smuzhiyun * 0 Success
4248*4882a593Smuzhiyun * <0 Error
4249*4882a593Smuzhiyun */
mtip_pci_suspend(struct pci_dev * pdev,pm_message_t mesg)4250*4882a593Smuzhiyun static int mtip_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
4251*4882a593Smuzhiyun {
4252*4882a593Smuzhiyun int rv = 0;
4253*4882a593Smuzhiyun struct driver_data *dd = pci_get_drvdata(pdev);
4254*4882a593Smuzhiyun
4255*4882a593Smuzhiyun if (!dd) {
4256*4882a593Smuzhiyun dev_err(&pdev->dev,
4257*4882a593Smuzhiyun "Driver private datastructure is NULL\n");
4258*4882a593Smuzhiyun return -EFAULT;
4259*4882a593Smuzhiyun }
4260*4882a593Smuzhiyun
4261*4882a593Smuzhiyun set_bit(MTIP_DDF_RESUME_BIT, &dd->dd_flag);
4262*4882a593Smuzhiyun
4263*4882a593Smuzhiyun /* Disable ports & interrupts then send standby immediate */
4264*4882a593Smuzhiyun rv = mtip_block_suspend(dd);
4265*4882a593Smuzhiyun if (rv < 0) {
4266*4882a593Smuzhiyun dev_err(&pdev->dev,
4267*4882a593Smuzhiyun "Failed to suspend controller\n");
4268*4882a593Smuzhiyun return rv;
4269*4882a593Smuzhiyun }
4270*4882a593Smuzhiyun
4271*4882a593Smuzhiyun /*
4272*4882a593Smuzhiyun * Save the pci config space to pdev structure &
4273*4882a593Smuzhiyun * disable the device
4274*4882a593Smuzhiyun */
4275*4882a593Smuzhiyun pci_save_state(pdev);
4276*4882a593Smuzhiyun pci_disable_device(pdev);
4277*4882a593Smuzhiyun
4278*4882a593Smuzhiyun /* Move to Low power state*/
4279*4882a593Smuzhiyun pci_set_power_state(pdev, PCI_D3hot);
4280*4882a593Smuzhiyun
4281*4882a593Smuzhiyun return rv;
4282*4882a593Smuzhiyun }
4283*4882a593Smuzhiyun
4284*4882a593Smuzhiyun /*
4285*4882a593Smuzhiyun * Called for each probed device when the device is resumed.
4286*4882a593Smuzhiyun *
4287*4882a593Smuzhiyun * return value
4288*4882a593Smuzhiyun * 0 Success
4289*4882a593Smuzhiyun * <0 Error
4290*4882a593Smuzhiyun */
mtip_pci_resume(struct pci_dev * pdev)4291*4882a593Smuzhiyun static int mtip_pci_resume(struct pci_dev *pdev)
4292*4882a593Smuzhiyun {
4293*4882a593Smuzhiyun int rv = 0;
4294*4882a593Smuzhiyun struct driver_data *dd;
4295*4882a593Smuzhiyun
4296*4882a593Smuzhiyun dd = pci_get_drvdata(pdev);
4297*4882a593Smuzhiyun if (!dd) {
4298*4882a593Smuzhiyun dev_err(&pdev->dev,
4299*4882a593Smuzhiyun "Driver private datastructure is NULL\n");
4300*4882a593Smuzhiyun return -EFAULT;
4301*4882a593Smuzhiyun }
4302*4882a593Smuzhiyun
4303*4882a593Smuzhiyun /* Move the device to active State */
4304*4882a593Smuzhiyun pci_set_power_state(pdev, PCI_D0);
4305*4882a593Smuzhiyun
4306*4882a593Smuzhiyun /* Restore PCI configuration space */
4307*4882a593Smuzhiyun pci_restore_state(pdev);
4308*4882a593Smuzhiyun
4309*4882a593Smuzhiyun /* Enable the PCI device*/
4310*4882a593Smuzhiyun rv = pcim_enable_device(pdev);
4311*4882a593Smuzhiyun if (rv < 0) {
4312*4882a593Smuzhiyun dev_err(&pdev->dev,
4313*4882a593Smuzhiyun "Failed to enable card during resume\n");
4314*4882a593Smuzhiyun goto err;
4315*4882a593Smuzhiyun }
4316*4882a593Smuzhiyun pci_set_master(pdev);
4317*4882a593Smuzhiyun
4318*4882a593Smuzhiyun /*
4319*4882a593Smuzhiyun * Calls hbaReset, initPort, & startPort function
4320*4882a593Smuzhiyun * then enables interrupts
4321*4882a593Smuzhiyun */
4322*4882a593Smuzhiyun rv = mtip_block_resume(dd);
4323*4882a593Smuzhiyun if (rv < 0)
4324*4882a593Smuzhiyun dev_err(&pdev->dev, "Unable to resume\n");
4325*4882a593Smuzhiyun
4326*4882a593Smuzhiyun err:
4327*4882a593Smuzhiyun clear_bit(MTIP_DDF_RESUME_BIT, &dd->dd_flag);
4328*4882a593Smuzhiyun
4329*4882a593Smuzhiyun return rv;
4330*4882a593Smuzhiyun }
4331*4882a593Smuzhiyun
4332*4882a593Smuzhiyun /*
4333*4882a593Smuzhiyun * Shutdown routine
4334*4882a593Smuzhiyun *
4335*4882a593Smuzhiyun * return value
4336*4882a593Smuzhiyun * None
4337*4882a593Smuzhiyun */
mtip_pci_shutdown(struct pci_dev * pdev)4338*4882a593Smuzhiyun static void mtip_pci_shutdown(struct pci_dev *pdev)
4339*4882a593Smuzhiyun {
4340*4882a593Smuzhiyun struct driver_data *dd = pci_get_drvdata(pdev);
4341*4882a593Smuzhiyun if (dd)
4342*4882a593Smuzhiyun mtip_block_shutdown(dd);
4343*4882a593Smuzhiyun }
4344*4882a593Smuzhiyun
4345*4882a593Smuzhiyun /* Table of device ids supported by this driver. */
4346*4882a593Smuzhiyun static const struct pci_device_id mtip_pci_tbl[] = {
4347*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P320H_DEVICE_ID) },
4348*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P320M_DEVICE_ID) },
4349*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P320S_DEVICE_ID) },
4350*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P325M_DEVICE_ID) },
4351*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P420H_DEVICE_ID) },
4352*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P420M_DEVICE_ID) },
4353*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MICRON, P425M_DEVICE_ID) },
4354*4882a593Smuzhiyun { 0 }
4355*4882a593Smuzhiyun };
4356*4882a593Smuzhiyun
4357*4882a593Smuzhiyun /* Structure that describes the PCI driver functions. */
4358*4882a593Smuzhiyun static struct pci_driver mtip_pci_driver = {
4359*4882a593Smuzhiyun .name = MTIP_DRV_NAME,
4360*4882a593Smuzhiyun .id_table = mtip_pci_tbl,
4361*4882a593Smuzhiyun .probe = mtip_pci_probe,
4362*4882a593Smuzhiyun .remove = mtip_pci_remove,
4363*4882a593Smuzhiyun .suspend = mtip_pci_suspend,
4364*4882a593Smuzhiyun .resume = mtip_pci_resume,
4365*4882a593Smuzhiyun .shutdown = mtip_pci_shutdown,
4366*4882a593Smuzhiyun };
4367*4882a593Smuzhiyun
4368*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mtip_pci_tbl);
4369*4882a593Smuzhiyun
4370*4882a593Smuzhiyun /*
4371*4882a593Smuzhiyun * Module initialization function.
4372*4882a593Smuzhiyun *
4373*4882a593Smuzhiyun * Called once when the module is loaded. This function allocates a major
4374*4882a593Smuzhiyun * block device number to the Cyclone devices and registers the PCI layer
4375*4882a593Smuzhiyun * of the driver.
4376*4882a593Smuzhiyun *
4377*4882a593Smuzhiyun * Return value
4378*4882a593Smuzhiyun * 0 on success else error code.
4379*4882a593Smuzhiyun */
mtip_init(void)4380*4882a593Smuzhiyun static int __init mtip_init(void)
4381*4882a593Smuzhiyun {
4382*4882a593Smuzhiyun int error;
4383*4882a593Smuzhiyun
4384*4882a593Smuzhiyun pr_info(MTIP_DRV_NAME " Version " MTIP_DRV_VERSION "\n");
4385*4882a593Smuzhiyun
4386*4882a593Smuzhiyun spin_lock_init(&dev_lock);
4387*4882a593Smuzhiyun
4388*4882a593Smuzhiyun INIT_LIST_HEAD(&online_list);
4389*4882a593Smuzhiyun INIT_LIST_HEAD(&removing_list);
4390*4882a593Smuzhiyun
4391*4882a593Smuzhiyun /* Allocate a major block device number to use with this driver. */
4392*4882a593Smuzhiyun error = register_blkdev(0, MTIP_DRV_NAME);
4393*4882a593Smuzhiyun if (error <= 0) {
4394*4882a593Smuzhiyun pr_err("Unable to register block device (%d)\n",
4395*4882a593Smuzhiyun error);
4396*4882a593Smuzhiyun return -EBUSY;
4397*4882a593Smuzhiyun }
4398*4882a593Smuzhiyun mtip_major = error;
4399*4882a593Smuzhiyun
4400*4882a593Smuzhiyun dfs_parent = debugfs_create_dir("rssd", NULL);
4401*4882a593Smuzhiyun if (IS_ERR_OR_NULL(dfs_parent)) {
4402*4882a593Smuzhiyun pr_warn("Error creating debugfs parent\n");
4403*4882a593Smuzhiyun dfs_parent = NULL;
4404*4882a593Smuzhiyun }
4405*4882a593Smuzhiyun if (dfs_parent) {
4406*4882a593Smuzhiyun dfs_device_status = debugfs_create_file("device_status",
4407*4882a593Smuzhiyun 0444, dfs_parent, NULL,
4408*4882a593Smuzhiyun &mtip_device_status_fops);
4409*4882a593Smuzhiyun if (IS_ERR_OR_NULL(dfs_device_status)) {
4410*4882a593Smuzhiyun pr_err("Error creating device_status node\n");
4411*4882a593Smuzhiyun dfs_device_status = NULL;
4412*4882a593Smuzhiyun }
4413*4882a593Smuzhiyun }
4414*4882a593Smuzhiyun
4415*4882a593Smuzhiyun /* Register our PCI operations. */
4416*4882a593Smuzhiyun error = pci_register_driver(&mtip_pci_driver);
4417*4882a593Smuzhiyun if (error) {
4418*4882a593Smuzhiyun debugfs_remove(dfs_parent);
4419*4882a593Smuzhiyun unregister_blkdev(mtip_major, MTIP_DRV_NAME);
4420*4882a593Smuzhiyun }
4421*4882a593Smuzhiyun
4422*4882a593Smuzhiyun return error;
4423*4882a593Smuzhiyun }
4424*4882a593Smuzhiyun
4425*4882a593Smuzhiyun /*
4426*4882a593Smuzhiyun * Module de-initialization function.
4427*4882a593Smuzhiyun *
4428*4882a593Smuzhiyun * Called once when the module is unloaded. This function deallocates
4429*4882a593Smuzhiyun * the major block device number allocated by mtip_init() and
4430*4882a593Smuzhiyun * unregisters the PCI layer of the driver.
4431*4882a593Smuzhiyun *
4432*4882a593Smuzhiyun * Return value
4433*4882a593Smuzhiyun * none
4434*4882a593Smuzhiyun */
mtip_exit(void)4435*4882a593Smuzhiyun static void __exit mtip_exit(void)
4436*4882a593Smuzhiyun {
4437*4882a593Smuzhiyun /* Release the allocated major block device number. */
4438*4882a593Smuzhiyun unregister_blkdev(mtip_major, MTIP_DRV_NAME);
4439*4882a593Smuzhiyun
4440*4882a593Smuzhiyun /* Unregister the PCI driver. */
4441*4882a593Smuzhiyun pci_unregister_driver(&mtip_pci_driver);
4442*4882a593Smuzhiyun
4443*4882a593Smuzhiyun debugfs_remove_recursive(dfs_parent);
4444*4882a593Smuzhiyun }
4445*4882a593Smuzhiyun
4446*4882a593Smuzhiyun MODULE_AUTHOR("Micron Technology, Inc");
4447*4882a593Smuzhiyun MODULE_DESCRIPTION("Micron RealSSD PCIe Block Driver");
4448*4882a593Smuzhiyun MODULE_LICENSE("GPL");
4449*4882a593Smuzhiyun MODULE_VERSION(MTIP_DRV_VERSION);
4450*4882a593Smuzhiyun
4451*4882a593Smuzhiyun module_init(mtip_init);
4452*4882a593Smuzhiyun module_exit(mtip_exit);
4453