1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Register map access API - W1 (1-Wire) support
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2017 Radioavionica Corporation
6*4882a593Smuzhiyun // Author: Alex A. Mihaylov <minimumlaw@rambler.ru>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/regmap.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/w1.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "internal.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define W1_CMD_READ_DATA 0x69
15*4882a593Smuzhiyun #define W1_CMD_WRITE_DATA 0x6C
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * 1-Wire slaves registers with addess 8 bit and data 8 bit
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
w1_reg_a8_v8_read(void * context,unsigned int reg,unsigned int * val)21*4882a593Smuzhiyun static int w1_reg_a8_v8_read(void *context, unsigned int reg, unsigned int *val)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct device *dev = context;
24*4882a593Smuzhiyun struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
25*4882a593Smuzhiyun int ret = 0;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun if (reg > 255)
28*4882a593Smuzhiyun return -EINVAL;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun mutex_lock(&sl->master->bus_mutex);
31*4882a593Smuzhiyun if (!w1_reset_select_slave(sl)) {
32*4882a593Smuzhiyun w1_write_8(sl->master, W1_CMD_READ_DATA);
33*4882a593Smuzhiyun w1_write_8(sl->master, reg);
34*4882a593Smuzhiyun *val = w1_read_8(sl->master);
35*4882a593Smuzhiyun } else {
36*4882a593Smuzhiyun ret = -ENODEV;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun mutex_unlock(&sl->master->bus_mutex);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return ret;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
w1_reg_a8_v8_write(void * context,unsigned int reg,unsigned int val)43*4882a593Smuzhiyun static int w1_reg_a8_v8_write(void *context, unsigned int reg, unsigned int val)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct device *dev = context;
46*4882a593Smuzhiyun struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
47*4882a593Smuzhiyun int ret = 0;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (reg > 255)
50*4882a593Smuzhiyun return -EINVAL;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun mutex_lock(&sl->master->bus_mutex);
53*4882a593Smuzhiyun if (!w1_reset_select_slave(sl)) {
54*4882a593Smuzhiyun w1_write_8(sl->master, W1_CMD_WRITE_DATA);
55*4882a593Smuzhiyun w1_write_8(sl->master, reg);
56*4882a593Smuzhiyun w1_write_8(sl->master, val);
57*4882a593Smuzhiyun } else {
58*4882a593Smuzhiyun ret = -ENODEV;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun mutex_unlock(&sl->master->bus_mutex);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return ret;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * 1-Wire slaves registers with addess 8 bit and data 16 bit
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun
w1_reg_a8_v16_read(void * context,unsigned int reg,unsigned int * val)69*4882a593Smuzhiyun static int w1_reg_a8_v16_read(void *context, unsigned int reg,
70*4882a593Smuzhiyun unsigned int *val)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct device *dev = context;
73*4882a593Smuzhiyun struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
74*4882a593Smuzhiyun int ret = 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (reg > 255)
77*4882a593Smuzhiyun return -EINVAL;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun mutex_lock(&sl->master->bus_mutex);
80*4882a593Smuzhiyun if (!w1_reset_select_slave(sl)) {
81*4882a593Smuzhiyun w1_write_8(sl->master, W1_CMD_READ_DATA);
82*4882a593Smuzhiyun w1_write_8(sl->master, reg);
83*4882a593Smuzhiyun *val = w1_read_8(sl->master);
84*4882a593Smuzhiyun *val |= w1_read_8(sl->master)<<8;
85*4882a593Smuzhiyun } else {
86*4882a593Smuzhiyun ret = -ENODEV;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun mutex_unlock(&sl->master->bus_mutex);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return ret;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
w1_reg_a8_v16_write(void * context,unsigned int reg,unsigned int val)93*4882a593Smuzhiyun static int w1_reg_a8_v16_write(void *context, unsigned int reg,
94*4882a593Smuzhiyun unsigned int val)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct device *dev = context;
97*4882a593Smuzhiyun struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
98*4882a593Smuzhiyun int ret = 0;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if (reg > 255)
101*4882a593Smuzhiyun return -EINVAL;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun mutex_lock(&sl->master->bus_mutex);
104*4882a593Smuzhiyun if (!w1_reset_select_slave(sl)) {
105*4882a593Smuzhiyun w1_write_8(sl->master, W1_CMD_WRITE_DATA);
106*4882a593Smuzhiyun w1_write_8(sl->master, reg);
107*4882a593Smuzhiyun w1_write_8(sl->master, val & 0x00FF);
108*4882a593Smuzhiyun w1_write_8(sl->master, val>>8 & 0x00FF);
109*4882a593Smuzhiyun } else {
110*4882a593Smuzhiyun ret = -ENODEV;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun mutex_unlock(&sl->master->bus_mutex);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return ret;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * 1-Wire slaves registers with addess 16 bit and data 16 bit
119*4882a593Smuzhiyun */
120*4882a593Smuzhiyun
w1_reg_a16_v16_read(void * context,unsigned int reg,unsigned int * val)121*4882a593Smuzhiyun static int w1_reg_a16_v16_read(void *context, unsigned int reg,
122*4882a593Smuzhiyun unsigned int *val)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct device *dev = context;
125*4882a593Smuzhiyun struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
126*4882a593Smuzhiyun int ret = 0;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (reg > 65535)
129*4882a593Smuzhiyun return -EINVAL;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun mutex_lock(&sl->master->bus_mutex);
132*4882a593Smuzhiyun if (!w1_reset_select_slave(sl)) {
133*4882a593Smuzhiyun w1_write_8(sl->master, W1_CMD_READ_DATA);
134*4882a593Smuzhiyun w1_write_8(sl->master, reg & 0x00FF);
135*4882a593Smuzhiyun w1_write_8(sl->master, reg>>8 & 0x00FF);
136*4882a593Smuzhiyun *val = w1_read_8(sl->master);
137*4882a593Smuzhiyun *val |= w1_read_8(sl->master)<<8;
138*4882a593Smuzhiyun } else {
139*4882a593Smuzhiyun ret = -ENODEV;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun mutex_unlock(&sl->master->bus_mutex);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun return ret;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
w1_reg_a16_v16_write(void * context,unsigned int reg,unsigned int val)146*4882a593Smuzhiyun static int w1_reg_a16_v16_write(void *context, unsigned int reg,
147*4882a593Smuzhiyun unsigned int val)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct device *dev = context;
150*4882a593Smuzhiyun struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
151*4882a593Smuzhiyun int ret = 0;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (reg > 65535)
154*4882a593Smuzhiyun return -EINVAL;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun mutex_lock(&sl->master->bus_mutex);
157*4882a593Smuzhiyun if (!w1_reset_select_slave(sl)) {
158*4882a593Smuzhiyun w1_write_8(sl->master, W1_CMD_WRITE_DATA);
159*4882a593Smuzhiyun w1_write_8(sl->master, reg & 0x00FF);
160*4882a593Smuzhiyun w1_write_8(sl->master, reg>>8 & 0x00FF);
161*4882a593Smuzhiyun w1_write_8(sl->master, val & 0x00FF);
162*4882a593Smuzhiyun w1_write_8(sl->master, val>>8 & 0x00FF);
163*4882a593Smuzhiyun } else {
164*4882a593Smuzhiyun ret = -ENODEV;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun mutex_unlock(&sl->master->bus_mutex);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return ret;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /*
172*4882a593Smuzhiyun * Various types of supported bus addressing
173*4882a593Smuzhiyun */
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static struct regmap_bus regmap_w1_bus_a8_v8 = {
176*4882a593Smuzhiyun .reg_read = w1_reg_a8_v8_read,
177*4882a593Smuzhiyun .reg_write = w1_reg_a8_v8_write,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun static struct regmap_bus regmap_w1_bus_a8_v16 = {
181*4882a593Smuzhiyun .reg_read = w1_reg_a8_v16_read,
182*4882a593Smuzhiyun .reg_write = w1_reg_a8_v16_write,
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static struct regmap_bus regmap_w1_bus_a16_v16 = {
186*4882a593Smuzhiyun .reg_read = w1_reg_a16_v16_read,
187*4882a593Smuzhiyun .reg_write = w1_reg_a16_v16_write,
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
regmap_get_w1_bus(struct device * w1_dev,const struct regmap_config * config)190*4882a593Smuzhiyun static const struct regmap_bus *regmap_get_w1_bus(struct device *w1_dev,
191*4882a593Smuzhiyun const struct regmap_config *config)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun if (config->reg_bits == 8 && config->val_bits == 8)
194*4882a593Smuzhiyun return ®map_w1_bus_a8_v8;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (config->reg_bits == 8 && config->val_bits == 16)
197*4882a593Smuzhiyun return ®map_w1_bus_a8_v16;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun if (config->reg_bits == 16 && config->val_bits == 16)
200*4882a593Smuzhiyun return ®map_w1_bus_a16_v16;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun return ERR_PTR(-ENOTSUPP);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
__regmap_init_w1(struct device * w1_dev,const struct regmap_config * config,struct lock_class_key * lock_key,const char * lock_name)205*4882a593Smuzhiyun struct regmap *__regmap_init_w1(struct device *w1_dev,
206*4882a593Smuzhiyun const struct regmap_config *config,
207*4882a593Smuzhiyun struct lock_class_key *lock_key,
208*4882a593Smuzhiyun const char *lock_name)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun const struct regmap_bus *bus = regmap_get_w1_bus(w1_dev, config);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (IS_ERR(bus))
214*4882a593Smuzhiyun return ERR_CAST(bus);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return __regmap_init(w1_dev, bus, w1_dev, config,
217*4882a593Smuzhiyun lock_key, lock_name);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__regmap_init_w1);
220*4882a593Smuzhiyun
__devm_regmap_init_w1(struct device * w1_dev,const struct regmap_config * config,struct lock_class_key * lock_key,const char * lock_name)221*4882a593Smuzhiyun struct regmap *__devm_regmap_init_w1(struct device *w1_dev,
222*4882a593Smuzhiyun const struct regmap_config *config,
223*4882a593Smuzhiyun struct lock_class_key *lock_key,
224*4882a593Smuzhiyun const char *lock_name)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun const struct regmap_bus *bus = regmap_get_w1_bus(w1_dev, config);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun if (IS_ERR(bus))
230*4882a593Smuzhiyun return ERR_CAST(bus);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun return __devm_regmap_init(w1_dev, bus, w1_dev, config,
233*4882a593Smuzhiyun lock_key, lock_name);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__devm_regmap_init_w1);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun MODULE_LICENSE("GPL");
238