1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef DRIVER_ATM_ZATM_H 8*4882a593Smuzhiyun #define DRIVER_ATM_ZATM_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/skbuff.h> 11*4882a593Smuzhiyun #include <linux/atm.h> 12*4882a593Smuzhiyun #include <linux/atmdev.h> 13*4882a593Smuzhiyun #include <linux/sonet.h> 14*4882a593Smuzhiyun #include <linux/pci.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define DEV_LABEL "zatm" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */ 20*4882a593Smuzhiyun #define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define LOW_MARK 12 /* start adding new buffers if less than 12 */ 23*4882a593Smuzhiyun #define HIGH_MARK 30 /* stop adding buffers after reaching 30 */ 24*4882a593Smuzhiyun #define OFF_CNG_THRES 5 /* threshold for offset changes */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define RX_SIZE 2 /* RX lookup entry size (in bytes) */ 27*4882a593Smuzhiyun #define NR_POOLS 32 /* number of free buffer pointers */ 28*4882a593Smuzhiyun #define POOL_SIZE 8 /* buffer entry size (in bytes) */ 29*4882a593Smuzhiyun #define NR_SHAPERS 16 /* number of shapers */ 30*4882a593Smuzhiyun #define SHAPER_SIZE 4 /* shaper entry size (in bytes) */ 31*4882a593Smuzhiyun #define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define RING_ENTRIES 32 /* ring entries (without back pointer) */ 34*4882a593Smuzhiyun #define RING_WORDS 4 /* ring element size */ 35*4882a593Smuzhiyun #define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define NR_MBX 4 /* four mailboxes */ 38*4882a593Smuzhiyun #define MBX_RX_0 0 /* mailbox indices */ 39*4882a593Smuzhiyun #define MBX_RX_1 1 40*4882a593Smuzhiyun #define MBX_TX_0 2 41*4882a593Smuzhiyun #define MBX_TX_1 3 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct zatm_vcc { 44*4882a593Smuzhiyun /*-------------------------------- RX part */ 45*4882a593Smuzhiyun int rx_chan; /* RX channel, 0 if none */ 46*4882a593Smuzhiyun int pool; /* free buffer pool */ 47*4882a593Smuzhiyun /*-------------------------------- TX part */ 48*4882a593Smuzhiyun int tx_chan; /* TX channel, 0 if none */ 49*4882a593Smuzhiyun int shaper; /* shaper, <0 if none */ 50*4882a593Smuzhiyun struct sk_buff_head tx_queue; /* list of buffers in transit */ 51*4882a593Smuzhiyun wait_queue_head_t tx_wait; /* for close */ 52*4882a593Smuzhiyun u32 *ring; /* transmit ring */ 53*4882a593Smuzhiyun int ring_curr; /* current write position */ 54*4882a593Smuzhiyun int txing; /* number of transmits in progress */ 55*4882a593Smuzhiyun struct sk_buff_head backlog; /* list of buffers waiting for ring */ 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct zatm_dev { 59*4882a593Smuzhiyun /*-------------------------------- TX part */ 60*4882a593Smuzhiyun int tx_bw; /* remaining bandwidth */ 61*4882a593Smuzhiyun u32 free_shapers; /* bit set */ 62*4882a593Smuzhiyun int ubr; /* UBR shaper; -1 if none */ 63*4882a593Smuzhiyun int ubr_ref_cnt; /* number of VCs using UBR shaper */ 64*4882a593Smuzhiyun /*-------------------------------- RX part */ 65*4882a593Smuzhiyun int pool_ref[NR_POOLS]; /* free buffer pool usage counters */ 66*4882a593Smuzhiyun volatile struct sk_buff *last_free[NR_POOLS]; 67*4882a593Smuzhiyun /* last entry in respective pool */ 68*4882a593Smuzhiyun struct sk_buff_head pool[NR_POOLS];/* free buffer pools */ 69*4882a593Smuzhiyun struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */ 70*4882a593Smuzhiyun /*-------------------------------- maps */ 71*4882a593Smuzhiyun struct atm_vcc **tx_map; /* TX VCCs */ 72*4882a593Smuzhiyun struct atm_vcc **rx_map; /* RX VCCs */ 73*4882a593Smuzhiyun int chans; /* map size, must be 2^n */ 74*4882a593Smuzhiyun /*-------------------------------- mailboxes */ 75*4882a593Smuzhiyun unsigned long mbx_start[NR_MBX];/* start addresses */ 76*4882a593Smuzhiyun dma_addr_t mbx_dma[NR_MBX]; 77*4882a593Smuzhiyun u16 mbx_end[NR_MBX]; /* end offset (in bytes) */ 78*4882a593Smuzhiyun /*-------------------------------- other pointers */ 79*4882a593Smuzhiyun u32 pool_base; /* Free buffer pool dsc (word addr) */ 80*4882a593Smuzhiyun /*-------------------------------- ZATM links */ 81*4882a593Smuzhiyun struct atm_dev *more; /* other ZATM devices */ 82*4882a593Smuzhiyun /*-------------------------------- general information */ 83*4882a593Smuzhiyun int mem; /* RAM on board (in bytes) */ 84*4882a593Smuzhiyun int khz; /* timer clock */ 85*4882a593Smuzhiyun int copper; /* PHY type */ 86*4882a593Smuzhiyun unsigned char irq; /* IRQ */ 87*4882a593Smuzhiyun unsigned int base; /* IO base address */ 88*4882a593Smuzhiyun struct pci_dev *pci_dev; /* PCI stuff */ 89*4882a593Smuzhiyun spinlock_t lock; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data) 94*4882a593Smuzhiyun #define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun struct zatm_skb_prv { 98*4882a593Smuzhiyun struct atm_skb_data _; /* reserved */ 99*4882a593Smuzhiyun u32 *dsc; /* pointer to skb's descriptor */ 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif 105