xref: /OK3568_Linux_fs/kernel/drivers/atm/zatm.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* drivers/atm/zatm.c - ZeitNet ZN122x device driver */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/mm.h>
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <linux/atm.h>
13*4882a593Smuzhiyun #include <linux/atmdev.h>
14*4882a593Smuzhiyun #include <linux/sonet.h>
15*4882a593Smuzhiyun #include <linux/skbuff.h>
16*4882a593Smuzhiyun #include <linux/netdevice.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/uio.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/dma-mapping.h>
22*4882a593Smuzhiyun #include <linux/atm_zatm.h>
23*4882a593Smuzhiyun #include <linux/capability.h>
24*4882a593Smuzhiyun #include <linux/bitops.h>
25*4882a593Smuzhiyun #include <linux/wait.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun #include <asm/byteorder.h>
28*4882a593Smuzhiyun #include <asm/string.h>
29*4882a593Smuzhiyun #include <asm/io.h>
30*4882a593Smuzhiyun #include <linux/atomic.h>
31*4882a593Smuzhiyun #include <linux/uaccess.h>
32*4882a593Smuzhiyun #include <linux/nospec.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include "uPD98401.h"
35*4882a593Smuzhiyun #include "uPD98402.h"
36*4882a593Smuzhiyun #include "zeprom.h"
37*4882a593Smuzhiyun #include "zatm.h"
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun  * TODO:
42*4882a593Smuzhiyun  *
43*4882a593Smuzhiyun  * Minor features
44*4882a593Smuzhiyun  *  - support 64 kB SDUs (will have to use multibuffer batches then :-( )
45*4882a593Smuzhiyun  *  - proper use of CDV, credit = max(1,CDVT*PCR)
46*4882a593Smuzhiyun  *  - AAL0
47*4882a593Smuzhiyun  *  - better receive timestamps
48*4882a593Smuzhiyun  *  - OAM
49*4882a593Smuzhiyun  */
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define ZATM_COPPER	1
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #if 0
54*4882a593Smuzhiyun #define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
55*4882a593Smuzhiyun #else
56*4882a593Smuzhiyun #define DPRINTK(format,args...)
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #ifndef CONFIG_ATM_ZATM_DEBUG
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define NULLCHECK(x)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define EVENT(s,a,b)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 
event_dump(void)67*4882a593Smuzhiyun static void event_dump(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #else
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun  * NULL pointer checking
77*4882a593Smuzhiyun  */
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define NULLCHECK(x) \
80*4882a593Smuzhiyun   if ((unsigned long) (x) < 0x30) printk(KERN_CRIT #x "==0x%x\n", (int) (x))
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun  * Very extensive activity logging. Greatly improves bug detection speed but
84*4882a593Smuzhiyun  * costs a few Mbps if enabled.
85*4882a593Smuzhiyun  */
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define EV 64
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun static const char *ev[EV];
90*4882a593Smuzhiyun static unsigned long ev_a[EV],ev_b[EV];
91*4882a593Smuzhiyun static int ec = 0;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 
EVENT(const char * s,unsigned long a,unsigned long b)94*4882a593Smuzhiyun static void EVENT(const char *s,unsigned long a,unsigned long b)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	ev[ec] = s;
97*4882a593Smuzhiyun 	ev_a[ec] = a;
98*4882a593Smuzhiyun 	ev_b[ec] = b;
99*4882a593Smuzhiyun 	ec = (ec+1) % EV;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 
event_dump(void)103*4882a593Smuzhiyun static void event_dump(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	int n,i;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	printk(KERN_NOTICE "----- event dump follows -----\n");
108*4882a593Smuzhiyun 	for (n = 0; n < EV; n++) {
109*4882a593Smuzhiyun 		i = (ec+n) % EV;
110*4882a593Smuzhiyun 		printk(KERN_NOTICE);
111*4882a593Smuzhiyun 		printk(ev[i] ? ev[i] : "(null)",ev_a[i],ev_b[i]);
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun 	printk(KERN_NOTICE "----- event dump ends here -----\n");
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #endif /* CONFIG_ATM_ZATM_DEBUG */
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define RING_BUSY	1	/* indication from do_tx that PDU has to be
121*4882a593Smuzhiyun 				   backlogged */
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun static struct atm_dev *zatm_boards = NULL;
124*4882a593Smuzhiyun static unsigned long dummy[2] = {0,0};
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define zin_n(r) inl(zatm_dev->base+r*4)
128*4882a593Smuzhiyun #define zin(r) inl(zatm_dev->base+uPD98401_##r*4)
129*4882a593Smuzhiyun #define zout(v,r) outl(v,zatm_dev->base+uPD98401_##r*4)
130*4882a593Smuzhiyun #define zwait() do {} while (zin(CMR) & uPD98401_BUSY)
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* RX0, RX1, TX0, TX1 */
133*4882a593Smuzhiyun static const int mbx_entries[NR_MBX] = { 1024,1024,1024,1024 };
134*4882a593Smuzhiyun static const int mbx_esize[NR_MBX] = { 16,16,4,4 }; /* entry size in bytes */
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define MBX_SIZE(i) (mbx_entries[i]*mbx_esize[i])
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /*-------------------------------- utilities --------------------------------*/
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 
zpokel(struct zatm_dev * zatm_dev,u32 value,u32 addr)142*4882a593Smuzhiyun static void zpokel(struct zatm_dev *zatm_dev,u32 value,u32 addr)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	zwait();
145*4882a593Smuzhiyun 	zout(value,CER);
146*4882a593Smuzhiyun 	zout(uPD98401_IND_ACC | uPD98401_IA_BALL |
147*4882a593Smuzhiyun 	    (uPD98401_IA_TGT_CM << uPD98401_IA_TGT_SHIFT) | addr,CMR);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 
zpeekl(struct zatm_dev * zatm_dev,u32 addr)151*4882a593Smuzhiyun static u32 zpeekl(struct zatm_dev *zatm_dev,u32 addr)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	zwait();
154*4882a593Smuzhiyun 	zout(uPD98401_IND_ACC | uPD98401_IA_BALL | uPD98401_IA_RW |
155*4882a593Smuzhiyun 	  (uPD98401_IA_TGT_CM << uPD98401_IA_TGT_SHIFT) | addr,CMR);
156*4882a593Smuzhiyun 	zwait();
157*4882a593Smuzhiyun 	return zin(CER);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /*------------------------------- free lists --------------------------------*/
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /*
165*4882a593Smuzhiyun  * Free buffer head structure:
166*4882a593Smuzhiyun  *   [0] pointer to buffer (for SAR)
167*4882a593Smuzhiyun  *   [1] buffer descr link pointer (for SAR)
168*4882a593Smuzhiyun  *   [2] back pointer to skb (for poll_rx)
169*4882a593Smuzhiyun  *   [3] data
170*4882a593Smuzhiyun  *   ...
171*4882a593Smuzhiyun  */
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun struct rx_buffer_head {
174*4882a593Smuzhiyun 	u32		buffer;	/* pointer to buffer (for SAR) */
175*4882a593Smuzhiyun 	u32		link;	/* buffer descriptor link pointer (for SAR) */
176*4882a593Smuzhiyun 	struct sk_buff	*skb;	/* back pointer to skb (for poll_rx) */
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 
refill_pool(struct atm_dev * dev,int pool)180*4882a593Smuzhiyun static void refill_pool(struct atm_dev *dev,int pool)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
183*4882a593Smuzhiyun 	struct sk_buff *skb;
184*4882a593Smuzhiyun 	struct rx_buffer_head *first;
185*4882a593Smuzhiyun 	unsigned long flags;
186*4882a593Smuzhiyun 	int align,offset,free,count,size;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	EVENT("refill_pool\n",0,0);
189*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
190*4882a593Smuzhiyun 	size = (64 << (pool <= ZATM_AAL5_POOL_BASE ? 0 :
191*4882a593Smuzhiyun 	    pool-ZATM_AAL5_POOL_BASE))+sizeof(struct rx_buffer_head);
192*4882a593Smuzhiyun 	if (size < PAGE_SIZE) {
193*4882a593Smuzhiyun 		align = 32; /* for 32 byte alignment */
194*4882a593Smuzhiyun 		offset = sizeof(struct rx_buffer_head);
195*4882a593Smuzhiyun 	}
196*4882a593Smuzhiyun 	else {
197*4882a593Smuzhiyun 		align = 4096;
198*4882a593Smuzhiyun 		offset = zatm_dev->pool_info[pool].offset+
199*4882a593Smuzhiyun 		    sizeof(struct rx_buffer_head);
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 	size += align;
202*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
203*4882a593Smuzhiyun 	free = zpeekl(zatm_dev,zatm_dev->pool_base+2*pool) &
204*4882a593Smuzhiyun 	    uPD98401_RXFP_REMAIN;
205*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
206*4882a593Smuzhiyun 	if (free >= zatm_dev->pool_info[pool].low_water) return;
207*4882a593Smuzhiyun 	EVENT("starting ... POOL: 0x%x, 0x%x\n",
208*4882a593Smuzhiyun 	    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool),
209*4882a593Smuzhiyun 	    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool+1));
210*4882a593Smuzhiyun 	EVENT("dummy: 0x%08lx, 0x%08lx\n",dummy[0],dummy[1]);
211*4882a593Smuzhiyun 	count = 0;
212*4882a593Smuzhiyun 	first = NULL;
213*4882a593Smuzhiyun 	while (free < zatm_dev->pool_info[pool].high_water) {
214*4882a593Smuzhiyun 		struct rx_buffer_head *head;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 		skb = alloc_skb(size,GFP_ATOMIC);
217*4882a593Smuzhiyun 		if (!skb) {
218*4882a593Smuzhiyun 			printk(KERN_WARNING DEV_LABEL "(Itf %d): got no new "
219*4882a593Smuzhiyun 			    "skb (%d) with %d free\n",dev->number,size,free);
220*4882a593Smuzhiyun 			break;
221*4882a593Smuzhiyun 		}
222*4882a593Smuzhiyun 		skb_reserve(skb,(unsigned char *) ((((unsigned long) skb->data+
223*4882a593Smuzhiyun 		    align+offset-1) & ~(unsigned long) (align-1))-offset)-
224*4882a593Smuzhiyun 		    skb->data);
225*4882a593Smuzhiyun 		head = (struct rx_buffer_head *) skb->data;
226*4882a593Smuzhiyun 		skb_reserve(skb,sizeof(struct rx_buffer_head));
227*4882a593Smuzhiyun 		if (!first) first = head;
228*4882a593Smuzhiyun 		count++;
229*4882a593Smuzhiyun 		head->buffer = virt_to_bus(skb->data);
230*4882a593Smuzhiyun 		head->link = 0;
231*4882a593Smuzhiyun 		head->skb = skb;
232*4882a593Smuzhiyun 		EVENT("enq skb 0x%08lx/0x%08lx\n",(unsigned long) skb,
233*4882a593Smuzhiyun 		    (unsigned long) head);
234*4882a593Smuzhiyun 		spin_lock_irqsave(&zatm_dev->lock, flags);
235*4882a593Smuzhiyun 		if (zatm_dev->last_free[pool])
236*4882a593Smuzhiyun 			((struct rx_buffer_head *) (zatm_dev->last_free[pool]->
237*4882a593Smuzhiyun 			    data))[-1].link = virt_to_bus(head);
238*4882a593Smuzhiyun 		zatm_dev->last_free[pool] = skb;
239*4882a593Smuzhiyun 		skb_queue_tail(&zatm_dev->pool[pool],skb);
240*4882a593Smuzhiyun 		spin_unlock_irqrestore(&zatm_dev->lock, flags);
241*4882a593Smuzhiyun 		free++;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 	if (first) {
244*4882a593Smuzhiyun 		spin_lock_irqsave(&zatm_dev->lock, flags);
245*4882a593Smuzhiyun 		zwait();
246*4882a593Smuzhiyun 		zout(virt_to_bus(first),CER);
247*4882a593Smuzhiyun 		zout(uPD98401_ADD_BAT | (pool << uPD98401_POOL_SHIFT) | count,
248*4882a593Smuzhiyun 		    CMR);
249*4882a593Smuzhiyun 		spin_unlock_irqrestore(&zatm_dev->lock, flags);
250*4882a593Smuzhiyun 		EVENT ("POOL: 0x%x, 0x%x\n",
251*4882a593Smuzhiyun 		    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool),
252*4882a593Smuzhiyun 		    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool+1));
253*4882a593Smuzhiyun 		EVENT("dummy: 0x%08lx, 0x%08lx\n",dummy[0],dummy[1]);
254*4882a593Smuzhiyun 	}
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 
drain_free(struct atm_dev * dev,int pool)258*4882a593Smuzhiyun static void drain_free(struct atm_dev *dev,int pool)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	skb_queue_purge(&ZATM_DEV(dev)->pool[pool]);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 
pool_index(int max_pdu)264*4882a593Smuzhiyun static int pool_index(int max_pdu)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	int i;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	if (max_pdu % ATM_CELL_PAYLOAD)
269*4882a593Smuzhiyun 		printk(KERN_ERR DEV_LABEL ": driver error in pool_index: "
270*4882a593Smuzhiyun 		    "max_pdu is %d\n",max_pdu);
271*4882a593Smuzhiyun 	if (max_pdu > 65536) return -1;
272*4882a593Smuzhiyun 	for (i = 0; (64 << i) < max_pdu; i++);
273*4882a593Smuzhiyun 	return i+ZATM_AAL5_POOL_BASE;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun /* use_pool isn't reentrant */
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 
use_pool(struct atm_dev * dev,int pool)280*4882a593Smuzhiyun static void use_pool(struct atm_dev *dev,int pool)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
283*4882a593Smuzhiyun 	unsigned long flags;
284*4882a593Smuzhiyun 	int size;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
287*4882a593Smuzhiyun 	if (!(zatm_dev->pool_info[pool].ref_count++)) {
288*4882a593Smuzhiyun 		skb_queue_head_init(&zatm_dev->pool[pool]);
289*4882a593Smuzhiyun 		size = pool-ZATM_AAL5_POOL_BASE;
290*4882a593Smuzhiyun 		if (size < 0) size = 0; /* 64B... */
291*4882a593Smuzhiyun 		else if (size > 10) size = 10; /* ... 64kB */
292*4882a593Smuzhiyun 		spin_lock_irqsave(&zatm_dev->lock, flags);
293*4882a593Smuzhiyun 		zpokel(zatm_dev,((zatm_dev->pool_info[pool].low_water/4) <<
294*4882a593Smuzhiyun 		    uPD98401_RXFP_ALERT_SHIFT) |
295*4882a593Smuzhiyun 		    (1 << uPD98401_RXFP_BTSZ_SHIFT) |
296*4882a593Smuzhiyun 		    (size << uPD98401_RXFP_BFSZ_SHIFT),
297*4882a593Smuzhiyun 		    zatm_dev->pool_base+pool*2);
298*4882a593Smuzhiyun 		zpokel(zatm_dev,(unsigned long) dummy,zatm_dev->pool_base+
299*4882a593Smuzhiyun 		    pool*2+1);
300*4882a593Smuzhiyun 		spin_unlock_irqrestore(&zatm_dev->lock, flags);
301*4882a593Smuzhiyun 		zatm_dev->last_free[pool] = NULL;
302*4882a593Smuzhiyun 		refill_pool(dev,pool);
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 	DPRINTK("pool %d: %d\n",pool,zatm_dev->pool_info[pool].ref_count);
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 
unuse_pool(struct atm_dev * dev,int pool)308*4882a593Smuzhiyun static void unuse_pool(struct atm_dev *dev,int pool)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	if (!(--ZATM_DEV(dev)->pool_info[pool].ref_count))
311*4882a593Smuzhiyun 		drain_free(dev,pool);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun /*----------------------------------- RX ------------------------------------*/
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun #if 0
318*4882a593Smuzhiyun static void exception(struct atm_vcc *vcc)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun    static int count = 0;
321*4882a593Smuzhiyun    struct zatm_dev *zatm_dev = ZATM_DEV(vcc->dev);
322*4882a593Smuzhiyun    struct zatm_vcc *zatm_vcc = ZATM_VCC(vcc);
323*4882a593Smuzhiyun    unsigned long *qrp;
324*4882a593Smuzhiyun    int i;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun    if (count++ > 2) return;
327*4882a593Smuzhiyun    for (i = 0; i < 8; i++)
328*4882a593Smuzhiyun 	printk("TX%d: 0x%08lx\n",i,
329*4882a593Smuzhiyun 	  zpeekl(zatm_dev,zatm_vcc->tx_chan*VC_SIZE/4+i));
330*4882a593Smuzhiyun    for (i = 0; i < 5; i++)
331*4882a593Smuzhiyun 	printk("SH%d: 0x%08lx\n",i,
332*4882a593Smuzhiyun 	  zpeekl(zatm_dev,uPD98401_IM(zatm_vcc->shaper)+16*i));
333*4882a593Smuzhiyun    qrp = (unsigned long *) zpeekl(zatm_dev,zatm_vcc->tx_chan*VC_SIZE/4+
334*4882a593Smuzhiyun      uPD98401_TXVC_QRP);
335*4882a593Smuzhiyun    printk("qrp=0x%08lx\n",(unsigned long) qrp);
336*4882a593Smuzhiyun    for (i = 0; i < 4; i++) printk("QRP[%d]: 0x%08lx",i,qrp[i]);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun #endif
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun static const char *err_txt[] = {
342*4882a593Smuzhiyun 	"No error",
343*4882a593Smuzhiyun 	"RX buf underflow",
344*4882a593Smuzhiyun 	"RX FIFO overrun",
345*4882a593Smuzhiyun 	"Maximum len violation",
346*4882a593Smuzhiyun 	"CRC error",
347*4882a593Smuzhiyun 	"User abort",
348*4882a593Smuzhiyun 	"Length violation",
349*4882a593Smuzhiyun 	"T1 error",
350*4882a593Smuzhiyun 	"Deactivated",
351*4882a593Smuzhiyun 	"???",
352*4882a593Smuzhiyun 	"???",
353*4882a593Smuzhiyun 	"???",
354*4882a593Smuzhiyun 	"???",
355*4882a593Smuzhiyun 	"???",
356*4882a593Smuzhiyun 	"???",
357*4882a593Smuzhiyun 	"???"
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 
poll_rx(struct atm_dev * dev,int mbx)361*4882a593Smuzhiyun static void poll_rx(struct atm_dev *dev,int mbx)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
364*4882a593Smuzhiyun 	unsigned long pos;
365*4882a593Smuzhiyun 	u32 x;
366*4882a593Smuzhiyun 	int error;
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	EVENT("poll_rx\n",0,0);
369*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
370*4882a593Smuzhiyun 	pos = (zatm_dev->mbx_start[mbx] & ~0xffffUL) | zin(MTA(mbx));
371*4882a593Smuzhiyun 	while (x = zin(MWA(mbx)), (pos & 0xffff) != x) {
372*4882a593Smuzhiyun 		u32 *here;
373*4882a593Smuzhiyun 		struct sk_buff *skb;
374*4882a593Smuzhiyun 		struct atm_vcc *vcc;
375*4882a593Smuzhiyun 		int cells,size,chan;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 		EVENT("MBX: host 0x%lx, nic 0x%x\n",pos,x);
378*4882a593Smuzhiyun 		here = (u32 *) pos;
379*4882a593Smuzhiyun 		if (((pos += 16) & 0xffff) == zatm_dev->mbx_end[mbx])
380*4882a593Smuzhiyun 			pos = zatm_dev->mbx_start[mbx];
381*4882a593Smuzhiyun 		cells = here[0] & uPD98401_AAL5_SIZE;
382*4882a593Smuzhiyun #if 0
383*4882a593Smuzhiyun printk("RX IND: 0x%x, 0x%x, 0x%x, 0x%x\n",here[0],here[1],here[2],here[3]);
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun unsigned long *x;
386*4882a593Smuzhiyun 		printk("POOL: 0x%08x, 0x%08x\n",zpeekl(zatm_dev,
387*4882a593Smuzhiyun 		      zatm_dev->pool_base),
388*4882a593Smuzhiyun 		      zpeekl(zatm_dev,zatm_dev->pool_base+1));
389*4882a593Smuzhiyun 		x = (unsigned long *) here[2];
390*4882a593Smuzhiyun 		printk("[0..3] = 0x%08lx, 0x%08lx, 0x%08lx, 0x%08lx\n",
391*4882a593Smuzhiyun 		    x[0],x[1],x[2],x[3]);
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun #endif
394*4882a593Smuzhiyun 		error = 0;
395*4882a593Smuzhiyun 		if (here[3] & uPD98401_AAL5_ERR) {
396*4882a593Smuzhiyun 			error = (here[3] & uPD98401_AAL5_ES) >>
397*4882a593Smuzhiyun 			    uPD98401_AAL5_ES_SHIFT;
398*4882a593Smuzhiyun 			if (error == uPD98401_AAL5_ES_DEACT ||
399*4882a593Smuzhiyun 			    error == uPD98401_AAL5_ES_FREE) continue;
400*4882a593Smuzhiyun 		}
401*4882a593Smuzhiyun EVENT("error code 0x%x/0x%x\n",(here[3] & uPD98401_AAL5_ES) >>
402*4882a593Smuzhiyun   uPD98401_AAL5_ES_SHIFT,error);
403*4882a593Smuzhiyun 		skb = ((struct rx_buffer_head *) bus_to_virt(here[2]))->skb;
404*4882a593Smuzhiyun 		__net_timestamp(skb);
405*4882a593Smuzhiyun #if 0
406*4882a593Smuzhiyun printk("[-3..0] 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",((unsigned *) skb->data)[-3],
407*4882a593Smuzhiyun   ((unsigned *) skb->data)[-2],((unsigned *) skb->data)[-1],
408*4882a593Smuzhiyun   ((unsigned *) skb->data)[0]);
409*4882a593Smuzhiyun #endif
410*4882a593Smuzhiyun 		EVENT("skb 0x%lx, here 0x%lx\n",(unsigned long) skb,
411*4882a593Smuzhiyun 		    (unsigned long) here);
412*4882a593Smuzhiyun #if 0
413*4882a593Smuzhiyun printk("dummy: 0x%08lx, 0x%08lx\n",dummy[0],dummy[1]);
414*4882a593Smuzhiyun #endif
415*4882a593Smuzhiyun 		size = error ? 0 : ntohs(((__be16 *) skb->data)[cells*
416*4882a593Smuzhiyun 		    ATM_CELL_PAYLOAD/sizeof(u16)-3]);
417*4882a593Smuzhiyun 		EVENT("got skb 0x%lx, size %d\n",(unsigned long) skb,size);
418*4882a593Smuzhiyun 		chan = (here[3] & uPD98401_AAL5_CHAN) >>
419*4882a593Smuzhiyun 		    uPD98401_AAL5_CHAN_SHIFT;
420*4882a593Smuzhiyun 		if (chan < zatm_dev->chans && zatm_dev->rx_map[chan]) {
421*4882a593Smuzhiyun 			int pos;
422*4882a593Smuzhiyun 			vcc = zatm_dev->rx_map[chan];
423*4882a593Smuzhiyun 			pos = ZATM_VCC(vcc)->pool;
424*4882a593Smuzhiyun 			if (skb == zatm_dev->last_free[pos])
425*4882a593Smuzhiyun 				zatm_dev->last_free[pos] = NULL;
426*4882a593Smuzhiyun 			skb_unlink(skb, zatm_dev->pool + pos);
427*4882a593Smuzhiyun 		}
428*4882a593Smuzhiyun 		else {
429*4882a593Smuzhiyun 			printk(KERN_ERR DEV_LABEL "(itf %d): RX indication "
430*4882a593Smuzhiyun 			    "for non-existing channel\n",dev->number);
431*4882a593Smuzhiyun 			size = 0;
432*4882a593Smuzhiyun 			vcc = NULL;
433*4882a593Smuzhiyun 			event_dump();
434*4882a593Smuzhiyun 		}
435*4882a593Smuzhiyun 		if (error) {
436*4882a593Smuzhiyun 			static unsigned long silence = 0;
437*4882a593Smuzhiyun 			static int last_error = 0;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 			if (error != last_error ||
440*4882a593Smuzhiyun 			    time_after(jiffies, silence)  || silence == 0){
441*4882a593Smuzhiyun 				printk(KERN_WARNING DEV_LABEL "(itf %d): "
442*4882a593Smuzhiyun 				    "chan %d error %s\n",dev->number,chan,
443*4882a593Smuzhiyun 				    err_txt[error]);
444*4882a593Smuzhiyun 				last_error = error;
445*4882a593Smuzhiyun 				silence = (jiffies+2*HZ)|1;
446*4882a593Smuzhiyun 			}
447*4882a593Smuzhiyun 			size = 0;
448*4882a593Smuzhiyun 		}
449*4882a593Smuzhiyun 		if (size && (size > cells*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER ||
450*4882a593Smuzhiyun 		    size <= (cells-1)*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER)) {
451*4882a593Smuzhiyun 			printk(KERN_ERR DEV_LABEL "(itf %d): size %d with %d "
452*4882a593Smuzhiyun 			    "cells\n",dev->number,size,cells);
453*4882a593Smuzhiyun 			size = 0;
454*4882a593Smuzhiyun 			event_dump();
455*4882a593Smuzhiyun 		}
456*4882a593Smuzhiyun 		if (size > ATM_MAX_AAL5_PDU) {
457*4882a593Smuzhiyun 			printk(KERN_ERR DEV_LABEL "(itf %d): size too big "
458*4882a593Smuzhiyun 			    "(%d)\n",dev->number,size);
459*4882a593Smuzhiyun 			size = 0;
460*4882a593Smuzhiyun 			event_dump();
461*4882a593Smuzhiyun 		}
462*4882a593Smuzhiyun 		if (!size) {
463*4882a593Smuzhiyun 			dev_kfree_skb_irq(skb);
464*4882a593Smuzhiyun 			if (vcc) atomic_inc(&vcc->stats->rx_err);
465*4882a593Smuzhiyun 			continue;
466*4882a593Smuzhiyun 		}
467*4882a593Smuzhiyun 		if (!atm_charge(vcc,skb->truesize)) {
468*4882a593Smuzhiyun 			dev_kfree_skb_irq(skb);
469*4882a593Smuzhiyun 			continue;
470*4882a593Smuzhiyun 		}
471*4882a593Smuzhiyun 		skb->len = size;
472*4882a593Smuzhiyun 		ATM_SKB(skb)->vcc = vcc;
473*4882a593Smuzhiyun 		vcc->push(vcc,skb);
474*4882a593Smuzhiyun 		atomic_inc(&vcc->stats->rx);
475*4882a593Smuzhiyun 	}
476*4882a593Smuzhiyun 	zout(pos & 0xffff,MTA(mbx));
477*4882a593Smuzhiyun #if 0 /* probably a stupid idea */
478*4882a593Smuzhiyun 	refill_pool(dev,zatm_vcc->pool);
479*4882a593Smuzhiyun 		/* maybe this saves us a few interrupts */
480*4882a593Smuzhiyun #endif
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 
open_rx_first(struct atm_vcc * vcc)484*4882a593Smuzhiyun static int open_rx_first(struct atm_vcc *vcc)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
487*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
488*4882a593Smuzhiyun 	unsigned long flags;
489*4882a593Smuzhiyun 	unsigned short chan;
490*4882a593Smuzhiyun 	int cells;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	DPRINTK("open_rx_first (0x%x)\n",inb_p(0xc053));
493*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
494*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
495*4882a593Smuzhiyun 	zatm_vcc->rx_chan = 0;
496*4882a593Smuzhiyun 	if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
497*4882a593Smuzhiyun 	if (vcc->qos.aal == ATM_AAL5) {
498*4882a593Smuzhiyun 		if (vcc->qos.rxtp.max_sdu > 65464)
499*4882a593Smuzhiyun 			vcc->qos.rxtp.max_sdu = 65464;
500*4882a593Smuzhiyun 			/* fix this - we may want to receive 64kB SDUs
501*4882a593Smuzhiyun 			   later */
502*4882a593Smuzhiyun 		cells = DIV_ROUND_UP(vcc->qos.rxtp.max_sdu + ATM_AAL5_TRAILER,
503*4882a593Smuzhiyun 				ATM_CELL_PAYLOAD);
504*4882a593Smuzhiyun 		zatm_vcc->pool = pool_index(cells*ATM_CELL_PAYLOAD);
505*4882a593Smuzhiyun 	}
506*4882a593Smuzhiyun 	else {
507*4882a593Smuzhiyun 		cells = 1;
508*4882a593Smuzhiyun 		zatm_vcc->pool = ZATM_AAL0_POOL;
509*4882a593Smuzhiyun 	}
510*4882a593Smuzhiyun 	if (zatm_vcc->pool < 0) return -EMSGSIZE;
511*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
512*4882a593Smuzhiyun 	zwait();
513*4882a593Smuzhiyun 	zout(uPD98401_OPEN_CHAN,CMR);
514*4882a593Smuzhiyun 	zwait();
515*4882a593Smuzhiyun 	DPRINTK("0x%x 0x%x\n",zin(CMR),zin(CER));
516*4882a593Smuzhiyun 	chan = (zin(CMR) & uPD98401_CHAN_ADDR) >> uPD98401_CHAN_ADDR_SHIFT;
517*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
518*4882a593Smuzhiyun 	DPRINTK("chan is %d\n",chan);
519*4882a593Smuzhiyun 	if (!chan) return -EAGAIN;
520*4882a593Smuzhiyun 	use_pool(vcc->dev,zatm_vcc->pool);
521*4882a593Smuzhiyun 	DPRINTK("pool %d\n",zatm_vcc->pool);
522*4882a593Smuzhiyun 	/* set up VC descriptor */
523*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
524*4882a593Smuzhiyun 	zpokel(zatm_dev,zatm_vcc->pool << uPD98401_RXVC_POOL_SHIFT,
525*4882a593Smuzhiyun 	    chan*VC_SIZE/4);
526*4882a593Smuzhiyun 	zpokel(zatm_dev,uPD98401_RXVC_OD | (vcc->qos.aal == ATM_AAL5 ?
527*4882a593Smuzhiyun 	    uPD98401_RXVC_AR : 0) | cells,chan*VC_SIZE/4+1);
528*4882a593Smuzhiyun 	zpokel(zatm_dev,0,chan*VC_SIZE/4+2);
529*4882a593Smuzhiyun 	zatm_vcc->rx_chan = chan;
530*4882a593Smuzhiyun 	zatm_dev->rx_map[chan] = vcc;
531*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
532*4882a593Smuzhiyun 	return 0;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 
open_rx_second(struct atm_vcc * vcc)536*4882a593Smuzhiyun static int open_rx_second(struct atm_vcc *vcc)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
539*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
540*4882a593Smuzhiyun 	unsigned long flags;
541*4882a593Smuzhiyun 	int pos,shift;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	DPRINTK("open_rx_second (0x%x)\n",inb_p(0xc053));
544*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
545*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
546*4882a593Smuzhiyun 	if (!zatm_vcc->rx_chan) return 0;
547*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
548*4882a593Smuzhiyun 	/* should also handle VPI @@@ */
549*4882a593Smuzhiyun 	pos = vcc->vci >> 1;
550*4882a593Smuzhiyun 	shift = (1-(vcc->vci & 1)) << 4;
551*4882a593Smuzhiyun 	zpokel(zatm_dev,(zpeekl(zatm_dev,pos) & ~(0xffff << shift)) |
552*4882a593Smuzhiyun 	    ((zatm_vcc->rx_chan | uPD98401_RXLT_ENBL) << shift),pos);
553*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
554*4882a593Smuzhiyun 	return 0;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 
close_rx(struct atm_vcc * vcc)558*4882a593Smuzhiyun static void close_rx(struct atm_vcc *vcc)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
561*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
562*4882a593Smuzhiyun 	unsigned long flags;
563*4882a593Smuzhiyun 	int pos,shift;
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
566*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
567*4882a593Smuzhiyun 	if (!zatm_vcc->rx_chan) return;
568*4882a593Smuzhiyun 	DPRINTK("close_rx\n");
569*4882a593Smuzhiyun 	/* disable receiver */
570*4882a593Smuzhiyun 	if (vcc->vpi != ATM_VPI_UNSPEC && vcc->vci != ATM_VCI_UNSPEC) {
571*4882a593Smuzhiyun 		spin_lock_irqsave(&zatm_dev->lock, flags);
572*4882a593Smuzhiyun 		pos = vcc->vci >> 1;
573*4882a593Smuzhiyun 		shift = (1-(vcc->vci & 1)) << 4;
574*4882a593Smuzhiyun 		zpokel(zatm_dev,zpeekl(zatm_dev,pos) & ~(0xffff << shift),pos);
575*4882a593Smuzhiyun 		zwait();
576*4882a593Smuzhiyun 		zout(uPD98401_NOP,CMR);
577*4882a593Smuzhiyun 		zwait();
578*4882a593Smuzhiyun 		zout(uPD98401_NOP,CMR);
579*4882a593Smuzhiyun 		spin_unlock_irqrestore(&zatm_dev->lock, flags);
580*4882a593Smuzhiyun 	}
581*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
582*4882a593Smuzhiyun 	zwait();
583*4882a593Smuzhiyun 	zout(uPD98401_DEACT_CHAN | uPD98401_CHAN_RT | (zatm_vcc->rx_chan <<
584*4882a593Smuzhiyun 	    uPD98401_CHAN_ADDR_SHIFT),CMR);
585*4882a593Smuzhiyun 	zwait();
586*4882a593Smuzhiyun 	udelay(10); /* why oh why ... ? */
587*4882a593Smuzhiyun 	zout(uPD98401_CLOSE_CHAN | uPD98401_CHAN_RT | (zatm_vcc->rx_chan <<
588*4882a593Smuzhiyun 	    uPD98401_CHAN_ADDR_SHIFT),CMR);
589*4882a593Smuzhiyun 	zwait();
590*4882a593Smuzhiyun 	if (!(zin(CMR) & uPD98401_CHAN_ADDR))
591*4882a593Smuzhiyun 		printk(KERN_CRIT DEV_LABEL "(itf %d): can't close RX channel "
592*4882a593Smuzhiyun 		    "%d\n",vcc->dev->number,zatm_vcc->rx_chan);
593*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
594*4882a593Smuzhiyun 	zatm_dev->rx_map[zatm_vcc->rx_chan] = NULL;
595*4882a593Smuzhiyun 	zatm_vcc->rx_chan = 0;
596*4882a593Smuzhiyun 	unuse_pool(vcc->dev,zatm_vcc->pool);
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 
start_rx(struct atm_dev * dev)600*4882a593Smuzhiyun static int start_rx(struct atm_dev *dev)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
603*4882a593Smuzhiyun 	int i;
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	DPRINTK("start_rx\n");
606*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
607*4882a593Smuzhiyun 	zatm_dev->rx_map = kcalloc(zatm_dev->chans,
608*4882a593Smuzhiyun 				   sizeof(*zatm_dev->rx_map),
609*4882a593Smuzhiyun 				   GFP_KERNEL);
610*4882a593Smuzhiyun 	if (!zatm_dev->rx_map) return -ENOMEM;
611*4882a593Smuzhiyun 	/* set VPI/VCI split (use all VCIs and give what's left to VPIs) */
612*4882a593Smuzhiyun 	zpokel(zatm_dev,(1 << dev->ci_range.vci_bits)-1,uPD98401_VRR);
613*4882a593Smuzhiyun 	/* prepare free buffer pools */
614*4882a593Smuzhiyun 	for (i = 0; i <= ZATM_LAST_POOL; i++) {
615*4882a593Smuzhiyun 		zatm_dev->pool_info[i].ref_count = 0;
616*4882a593Smuzhiyun 		zatm_dev->pool_info[i].rqa_count = 0;
617*4882a593Smuzhiyun 		zatm_dev->pool_info[i].rqu_count = 0;
618*4882a593Smuzhiyun 		zatm_dev->pool_info[i].low_water = LOW_MARK;
619*4882a593Smuzhiyun 		zatm_dev->pool_info[i].high_water = HIGH_MARK;
620*4882a593Smuzhiyun 		zatm_dev->pool_info[i].offset = 0;
621*4882a593Smuzhiyun 		zatm_dev->pool_info[i].next_off = 0;
622*4882a593Smuzhiyun 		zatm_dev->pool_info[i].next_cnt = 0;
623*4882a593Smuzhiyun 		zatm_dev->pool_info[i].next_thres = OFF_CNG_THRES;
624*4882a593Smuzhiyun 	}
625*4882a593Smuzhiyun 	return 0;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun /*----------------------------------- TX ------------------------------------*/
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 
do_tx(struct sk_buff * skb)632*4882a593Smuzhiyun static int do_tx(struct sk_buff *skb)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun 	struct atm_vcc *vcc;
635*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
636*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
637*4882a593Smuzhiyun 	u32 *dsc;
638*4882a593Smuzhiyun 	unsigned long flags;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	EVENT("do_tx\n",0,0);
641*4882a593Smuzhiyun 	DPRINTK("sending skb %p\n",skb);
642*4882a593Smuzhiyun 	vcc = ATM_SKB(skb)->vcc;
643*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
644*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
645*4882a593Smuzhiyun 	EVENT("iovcnt=%d\n",skb_shinfo(skb)->nr_frags,0);
646*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
647*4882a593Smuzhiyun 	if (!skb_shinfo(skb)->nr_frags) {
648*4882a593Smuzhiyun 		if (zatm_vcc->txing == RING_ENTRIES-1) {
649*4882a593Smuzhiyun 			spin_unlock_irqrestore(&zatm_dev->lock, flags);
650*4882a593Smuzhiyun 			return RING_BUSY;
651*4882a593Smuzhiyun 		}
652*4882a593Smuzhiyun 		zatm_vcc->txing++;
653*4882a593Smuzhiyun 		dsc = zatm_vcc->ring+zatm_vcc->ring_curr;
654*4882a593Smuzhiyun 		zatm_vcc->ring_curr = (zatm_vcc->ring_curr+RING_WORDS) &
655*4882a593Smuzhiyun 		    (RING_ENTRIES*RING_WORDS-1);
656*4882a593Smuzhiyun 		dsc[1] = 0;
657*4882a593Smuzhiyun 		dsc[2] = skb->len;
658*4882a593Smuzhiyun 		dsc[3] = virt_to_bus(skb->data);
659*4882a593Smuzhiyun 		mb();
660*4882a593Smuzhiyun 		dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP | uPD98401_TXPD_SM
661*4882a593Smuzhiyun 		    | (vcc->qos.aal == ATM_AAL5 ? uPD98401_TXPD_AAL5 : 0 |
662*4882a593Smuzhiyun 		    (ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ?
663*4882a593Smuzhiyun 		    uPD98401_CLPM_1 : uPD98401_CLPM_0));
664*4882a593Smuzhiyun 		EVENT("dsc (0x%lx)\n",(unsigned long) dsc,0);
665*4882a593Smuzhiyun 	}
666*4882a593Smuzhiyun 	else {
667*4882a593Smuzhiyun printk("NONONONOO!!!!\n");
668*4882a593Smuzhiyun 		dsc = NULL;
669*4882a593Smuzhiyun #if 0
670*4882a593Smuzhiyun 		u32 *put;
671*4882a593Smuzhiyun 		int i;
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 		dsc = kmalloc(uPD98401_TXPD_SIZE * 2 +
674*4882a593Smuzhiyun 			uPD98401_TXBD_SIZE * ATM_SKB(skb)->iovcnt, GFP_ATOMIC);
675*4882a593Smuzhiyun 		if (!dsc) {
676*4882a593Smuzhiyun 			if (vcc->pop)
677*4882a593Smuzhiyun 				vcc->pop(vcc, skb);
678*4882a593Smuzhiyun 			else
679*4882a593Smuzhiyun 				dev_kfree_skb_irq(skb);
680*4882a593Smuzhiyun 			return -EAGAIN;
681*4882a593Smuzhiyun 		}
682*4882a593Smuzhiyun 		/* @@@ should check alignment */
683*4882a593Smuzhiyun 		put = dsc+8;
684*4882a593Smuzhiyun 		dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP |
685*4882a593Smuzhiyun 		    (vcc->aal == ATM_AAL5 ? uPD98401_TXPD_AAL5 : 0 |
686*4882a593Smuzhiyun 		    (ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ?
687*4882a593Smuzhiyun 		    uPD98401_CLPM_1 : uPD98401_CLPM_0));
688*4882a593Smuzhiyun 		dsc[1] = 0;
689*4882a593Smuzhiyun 		dsc[2] = ATM_SKB(skb)->iovcnt * uPD98401_TXBD_SIZE;
690*4882a593Smuzhiyun 		dsc[3] = virt_to_bus(put);
691*4882a593Smuzhiyun 		for (i = 0; i < ATM_SKB(skb)->iovcnt; i++) {
692*4882a593Smuzhiyun 			*put++ = ((struct iovec *) skb->data)[i].iov_len;
693*4882a593Smuzhiyun 			*put++ = virt_to_bus(((struct iovec *)
694*4882a593Smuzhiyun 			    skb->data)[i].iov_base);
695*4882a593Smuzhiyun 		}
696*4882a593Smuzhiyun 		put[-2] |= uPD98401_TXBD_LAST;
697*4882a593Smuzhiyun #endif
698*4882a593Smuzhiyun 	}
699*4882a593Smuzhiyun 	ZATM_PRV_DSC(skb) = dsc;
700*4882a593Smuzhiyun 	skb_queue_tail(&zatm_vcc->tx_queue,skb);
701*4882a593Smuzhiyun 	DPRINTK("QRP=0x%08lx\n",zpeekl(zatm_dev,zatm_vcc->tx_chan*VC_SIZE/4+
702*4882a593Smuzhiyun 	  uPD98401_TXVC_QRP));
703*4882a593Smuzhiyun 	zwait();
704*4882a593Smuzhiyun 	zout(uPD98401_TX_READY | (zatm_vcc->tx_chan <<
705*4882a593Smuzhiyun 	    uPD98401_CHAN_ADDR_SHIFT),CMR);
706*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
707*4882a593Smuzhiyun 	EVENT("done\n",0,0);
708*4882a593Smuzhiyun 	return 0;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 
dequeue_tx(struct atm_vcc * vcc)712*4882a593Smuzhiyun static inline void dequeue_tx(struct atm_vcc *vcc)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
715*4882a593Smuzhiyun 	struct sk_buff *skb;
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	EVENT("dequeue_tx\n",0,0);
718*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
719*4882a593Smuzhiyun 	skb = skb_dequeue(&zatm_vcc->tx_queue);
720*4882a593Smuzhiyun 	if (!skb) {
721*4882a593Smuzhiyun 		printk(KERN_CRIT DEV_LABEL "(itf %d): dequeue_tx but not "
722*4882a593Smuzhiyun 		    "txing\n",vcc->dev->number);
723*4882a593Smuzhiyun 		return;
724*4882a593Smuzhiyun 	}
725*4882a593Smuzhiyun #if 0 /* @@@ would fail on CLP */
726*4882a593Smuzhiyun if (*ZATM_PRV_DSC(skb) != (uPD98401_TXPD_V | uPD98401_TXPD_DP |
727*4882a593Smuzhiyun   uPD98401_TXPD_SM | uPD98401_TXPD_AAL5)) printk("@#*$!!!!  (%08x)\n",
728*4882a593Smuzhiyun   *ZATM_PRV_DSC(skb));
729*4882a593Smuzhiyun #endif
730*4882a593Smuzhiyun 	*ZATM_PRV_DSC(skb) = 0; /* mark as invalid */
731*4882a593Smuzhiyun 	zatm_vcc->txing--;
732*4882a593Smuzhiyun 	if (vcc->pop) vcc->pop(vcc,skb);
733*4882a593Smuzhiyun 	else dev_kfree_skb_irq(skb);
734*4882a593Smuzhiyun 	while ((skb = skb_dequeue(&zatm_vcc->backlog)))
735*4882a593Smuzhiyun 		if (do_tx(skb) == RING_BUSY) {
736*4882a593Smuzhiyun 			skb_queue_head(&zatm_vcc->backlog,skb);
737*4882a593Smuzhiyun 			break;
738*4882a593Smuzhiyun 		}
739*4882a593Smuzhiyun 	atomic_inc(&vcc->stats->tx);
740*4882a593Smuzhiyun 	wake_up(&zatm_vcc->tx_wait);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 
poll_tx(struct atm_dev * dev,int mbx)744*4882a593Smuzhiyun static void poll_tx(struct atm_dev *dev,int mbx)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
747*4882a593Smuzhiyun 	unsigned long pos;
748*4882a593Smuzhiyun 	u32 x;
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun 	EVENT("poll_tx\n",0,0);
751*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
752*4882a593Smuzhiyun 	pos = (zatm_dev->mbx_start[mbx] & ~0xffffUL) | zin(MTA(mbx));
753*4882a593Smuzhiyun 	while (x = zin(MWA(mbx)), (pos & 0xffff) != x) {
754*4882a593Smuzhiyun 		int chan;
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun #if 1
757*4882a593Smuzhiyun 		u32 data,*addr;
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 		EVENT("MBX: host 0x%lx, nic 0x%x\n",pos,x);
760*4882a593Smuzhiyun 		addr = (u32 *) pos;
761*4882a593Smuzhiyun 		data = *addr;
762*4882a593Smuzhiyun 		chan = (data & uPD98401_TXI_CONN) >> uPD98401_TXI_CONN_SHIFT;
763*4882a593Smuzhiyun 		EVENT("addr = 0x%lx, data = 0x%08x,",(unsigned long) addr,
764*4882a593Smuzhiyun 		    data);
765*4882a593Smuzhiyun 		EVENT("chan = %d\n",chan,0);
766*4882a593Smuzhiyun #else
767*4882a593Smuzhiyun NO !
768*4882a593Smuzhiyun 		chan = (zatm_dev->mbx_start[mbx][pos >> 2] & uPD98401_TXI_CONN)
769*4882a593Smuzhiyun 		>> uPD98401_TXI_CONN_SHIFT;
770*4882a593Smuzhiyun #endif
771*4882a593Smuzhiyun 		if (chan < zatm_dev->chans && zatm_dev->tx_map[chan])
772*4882a593Smuzhiyun 			dequeue_tx(zatm_dev->tx_map[chan]);
773*4882a593Smuzhiyun 		else {
774*4882a593Smuzhiyun 			printk(KERN_CRIT DEV_LABEL "(itf %d): TX indication "
775*4882a593Smuzhiyun 			    "for non-existing channel %d\n",dev->number,chan);
776*4882a593Smuzhiyun 			event_dump();
777*4882a593Smuzhiyun 		}
778*4882a593Smuzhiyun 		if (((pos += 4) & 0xffff) == zatm_dev->mbx_end[mbx])
779*4882a593Smuzhiyun 			pos = zatm_dev->mbx_start[mbx];
780*4882a593Smuzhiyun 	}
781*4882a593Smuzhiyun 	zout(pos & 0xffff,MTA(mbx));
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun /*
786*4882a593Smuzhiyun  * BUG BUG BUG: Doesn't handle "new-style" rate specification yet.
787*4882a593Smuzhiyun  */
788*4882a593Smuzhiyun 
alloc_shaper(struct atm_dev * dev,int * pcr,int min,int max,int ubr)789*4882a593Smuzhiyun static int alloc_shaper(struct atm_dev *dev,int *pcr,int min,int max,int ubr)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
792*4882a593Smuzhiyun 	unsigned long flags;
793*4882a593Smuzhiyun 	unsigned long i,m,c;
794*4882a593Smuzhiyun 	int shaper;
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 	DPRINTK("alloc_shaper (min = %d, max = %d)\n",min,max);
797*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
798*4882a593Smuzhiyun 	if (!zatm_dev->free_shapers) return -EAGAIN;
799*4882a593Smuzhiyun 	for (shaper = 0; !((zatm_dev->free_shapers >> shaper) & 1); shaper++);
800*4882a593Smuzhiyun 	zatm_dev->free_shapers &= ~1 << shaper;
801*4882a593Smuzhiyun 	if (ubr) {
802*4882a593Smuzhiyun 		c = 5;
803*4882a593Smuzhiyun 		i = m = 1;
804*4882a593Smuzhiyun 		zatm_dev->ubr_ref_cnt++;
805*4882a593Smuzhiyun 		zatm_dev->ubr = shaper;
806*4882a593Smuzhiyun 		*pcr = 0;
807*4882a593Smuzhiyun 	}
808*4882a593Smuzhiyun 	else {
809*4882a593Smuzhiyun 		if (min) {
810*4882a593Smuzhiyun 			if (min <= 255) {
811*4882a593Smuzhiyun 				i = min;
812*4882a593Smuzhiyun 				m = ATM_OC3_PCR;
813*4882a593Smuzhiyun 			}
814*4882a593Smuzhiyun 			else {
815*4882a593Smuzhiyun 				i = 255;
816*4882a593Smuzhiyun 				m = ATM_OC3_PCR*255/min;
817*4882a593Smuzhiyun 			}
818*4882a593Smuzhiyun 		}
819*4882a593Smuzhiyun 		else {
820*4882a593Smuzhiyun 			if (max > zatm_dev->tx_bw) max = zatm_dev->tx_bw;
821*4882a593Smuzhiyun 			if (max <= 255) {
822*4882a593Smuzhiyun 				i = max;
823*4882a593Smuzhiyun 				m = ATM_OC3_PCR;
824*4882a593Smuzhiyun 			}
825*4882a593Smuzhiyun 			else {
826*4882a593Smuzhiyun 				i = 255;
827*4882a593Smuzhiyun 				m = DIV_ROUND_UP(ATM_OC3_PCR*255, max);
828*4882a593Smuzhiyun 			}
829*4882a593Smuzhiyun 		}
830*4882a593Smuzhiyun 		if (i > m) {
831*4882a593Smuzhiyun 			printk(KERN_CRIT DEV_LABEL "shaper algorithm botched "
832*4882a593Smuzhiyun 			    "[%d,%d] -> i=%ld,m=%ld\n",min,max,i,m);
833*4882a593Smuzhiyun 			m = i;
834*4882a593Smuzhiyun 		}
835*4882a593Smuzhiyun 		*pcr = i*ATM_OC3_PCR/m;
836*4882a593Smuzhiyun 		c = 20; /* @@@ should use max_cdv ! */
837*4882a593Smuzhiyun 		if ((min && *pcr < min) || (max && *pcr > max)) return -EINVAL;
838*4882a593Smuzhiyun 		if (zatm_dev->tx_bw < *pcr) return -EAGAIN;
839*4882a593Smuzhiyun 		zatm_dev->tx_bw -= *pcr;
840*4882a593Smuzhiyun 	}
841*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
842*4882a593Smuzhiyun 	DPRINTK("i = %d, m = %d, PCR = %d\n",i,m,*pcr);
843*4882a593Smuzhiyun 	zpokel(zatm_dev,(i << uPD98401_IM_I_SHIFT) | m,uPD98401_IM(shaper));
844*4882a593Smuzhiyun 	zpokel(zatm_dev,c << uPD98401_PC_C_SHIFT,uPD98401_PC(shaper));
845*4882a593Smuzhiyun 	zpokel(zatm_dev,0,uPD98401_X(shaper));
846*4882a593Smuzhiyun 	zpokel(zatm_dev,0,uPD98401_Y(shaper));
847*4882a593Smuzhiyun 	zpokel(zatm_dev,uPD98401_PS_E,uPD98401_PS(shaper));
848*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
849*4882a593Smuzhiyun 	return shaper;
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 
dealloc_shaper(struct atm_dev * dev,int shaper)853*4882a593Smuzhiyun static void dealloc_shaper(struct atm_dev *dev,int shaper)
854*4882a593Smuzhiyun {
855*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
856*4882a593Smuzhiyun 	unsigned long flags;
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
859*4882a593Smuzhiyun 	if (shaper == zatm_dev->ubr) {
860*4882a593Smuzhiyun 		if (--zatm_dev->ubr_ref_cnt) return;
861*4882a593Smuzhiyun 		zatm_dev->ubr = -1;
862*4882a593Smuzhiyun 	}
863*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
864*4882a593Smuzhiyun 	zpokel(zatm_dev,zpeekl(zatm_dev,uPD98401_PS(shaper)) & ~uPD98401_PS_E,
865*4882a593Smuzhiyun 	    uPD98401_PS(shaper));
866*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
867*4882a593Smuzhiyun 	zatm_dev->free_shapers |= 1 << shaper;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 
close_tx(struct atm_vcc * vcc)871*4882a593Smuzhiyun static void close_tx(struct atm_vcc *vcc)
872*4882a593Smuzhiyun {
873*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
874*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
875*4882a593Smuzhiyun 	unsigned long flags;
876*4882a593Smuzhiyun 	int chan;
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
879*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
880*4882a593Smuzhiyun 	chan = zatm_vcc->tx_chan;
881*4882a593Smuzhiyun 	if (!chan) return;
882*4882a593Smuzhiyun 	DPRINTK("close_tx\n");
883*4882a593Smuzhiyun 	if (skb_peek(&zatm_vcc->backlog)) {
884*4882a593Smuzhiyun 		printk("waiting for backlog to drain ...\n");
885*4882a593Smuzhiyun 		event_dump();
886*4882a593Smuzhiyun 		wait_event(zatm_vcc->tx_wait, !skb_peek(&zatm_vcc->backlog));
887*4882a593Smuzhiyun 	}
888*4882a593Smuzhiyun 	if (skb_peek(&zatm_vcc->tx_queue)) {
889*4882a593Smuzhiyun 		printk("waiting for TX queue to drain ...\n");
890*4882a593Smuzhiyun 		event_dump();
891*4882a593Smuzhiyun 		wait_event(zatm_vcc->tx_wait, !skb_peek(&zatm_vcc->tx_queue));
892*4882a593Smuzhiyun 	}
893*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
894*4882a593Smuzhiyun #if 0
895*4882a593Smuzhiyun 	zwait();
896*4882a593Smuzhiyun 	zout(uPD98401_DEACT_CHAN | (chan << uPD98401_CHAN_ADDR_SHIFT),CMR);
897*4882a593Smuzhiyun #endif
898*4882a593Smuzhiyun 	zwait();
899*4882a593Smuzhiyun 	zout(uPD98401_CLOSE_CHAN | (chan << uPD98401_CHAN_ADDR_SHIFT),CMR);
900*4882a593Smuzhiyun 	zwait();
901*4882a593Smuzhiyun 	if (!(zin(CMR) & uPD98401_CHAN_ADDR))
902*4882a593Smuzhiyun 		printk(KERN_CRIT DEV_LABEL "(itf %d): can't close TX channel "
903*4882a593Smuzhiyun 		    "%d\n",vcc->dev->number,chan);
904*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
905*4882a593Smuzhiyun 	zatm_vcc->tx_chan = 0;
906*4882a593Smuzhiyun 	zatm_dev->tx_map[chan] = NULL;
907*4882a593Smuzhiyun 	if (zatm_vcc->shaper != zatm_dev->ubr) {
908*4882a593Smuzhiyun 		zatm_dev->tx_bw += vcc->qos.txtp.min_pcr;
909*4882a593Smuzhiyun 		dealloc_shaper(vcc->dev,zatm_vcc->shaper);
910*4882a593Smuzhiyun 	}
911*4882a593Smuzhiyun 	kfree(zatm_vcc->ring);
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 
open_tx_first(struct atm_vcc * vcc)915*4882a593Smuzhiyun static int open_tx_first(struct atm_vcc *vcc)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
918*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
919*4882a593Smuzhiyun 	unsigned long flags;
920*4882a593Smuzhiyun 	u32 *loop;
921*4882a593Smuzhiyun 	unsigned short chan;
922*4882a593Smuzhiyun 	int unlimited;
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun 	DPRINTK("open_tx_first\n");
925*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
926*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
927*4882a593Smuzhiyun 	zatm_vcc->tx_chan = 0;
928*4882a593Smuzhiyun 	if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
929*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
930*4882a593Smuzhiyun 	zwait();
931*4882a593Smuzhiyun 	zout(uPD98401_OPEN_CHAN,CMR);
932*4882a593Smuzhiyun 	zwait();
933*4882a593Smuzhiyun 	DPRINTK("0x%x 0x%x\n",zin(CMR),zin(CER));
934*4882a593Smuzhiyun 	chan = (zin(CMR) & uPD98401_CHAN_ADDR) >> uPD98401_CHAN_ADDR_SHIFT;
935*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
936*4882a593Smuzhiyun 	DPRINTK("chan is %d\n",chan);
937*4882a593Smuzhiyun 	if (!chan) return -EAGAIN;
938*4882a593Smuzhiyun 	unlimited = vcc->qos.txtp.traffic_class == ATM_UBR &&
939*4882a593Smuzhiyun 	    (!vcc->qos.txtp.max_pcr || vcc->qos.txtp.max_pcr == ATM_MAX_PCR ||
940*4882a593Smuzhiyun 	    vcc->qos.txtp.max_pcr >= ATM_OC3_PCR);
941*4882a593Smuzhiyun 	if (unlimited && zatm_dev->ubr != -1) zatm_vcc->shaper = zatm_dev->ubr;
942*4882a593Smuzhiyun 	else {
943*4882a593Smuzhiyun 		int pcr;
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 		if (unlimited) vcc->qos.txtp.max_sdu = ATM_MAX_AAL5_PDU;
946*4882a593Smuzhiyun 		if ((zatm_vcc->shaper = alloc_shaper(vcc->dev,&pcr,
947*4882a593Smuzhiyun 		    vcc->qos.txtp.min_pcr,vcc->qos.txtp.max_pcr,unlimited))
948*4882a593Smuzhiyun 		    < 0) {
949*4882a593Smuzhiyun 			close_tx(vcc);
950*4882a593Smuzhiyun 			return zatm_vcc->shaper;
951*4882a593Smuzhiyun 		}
952*4882a593Smuzhiyun 		if (pcr > ATM_OC3_PCR) pcr = ATM_OC3_PCR;
953*4882a593Smuzhiyun 		vcc->qos.txtp.min_pcr = vcc->qos.txtp.max_pcr = pcr;
954*4882a593Smuzhiyun 	}
955*4882a593Smuzhiyun 	zatm_vcc->tx_chan = chan;
956*4882a593Smuzhiyun 	skb_queue_head_init(&zatm_vcc->tx_queue);
957*4882a593Smuzhiyun 	init_waitqueue_head(&zatm_vcc->tx_wait);
958*4882a593Smuzhiyun 	/* initialize ring */
959*4882a593Smuzhiyun 	zatm_vcc->ring = kzalloc(RING_SIZE,GFP_KERNEL);
960*4882a593Smuzhiyun 	if (!zatm_vcc->ring) return -ENOMEM;
961*4882a593Smuzhiyun 	loop = zatm_vcc->ring+RING_ENTRIES*RING_WORDS;
962*4882a593Smuzhiyun 	loop[0] = uPD98401_TXPD_V;
963*4882a593Smuzhiyun 	loop[1] = loop[2] = 0;
964*4882a593Smuzhiyun 	loop[3] = virt_to_bus(zatm_vcc->ring);
965*4882a593Smuzhiyun 	zatm_vcc->ring_curr = 0;
966*4882a593Smuzhiyun 	zatm_vcc->txing = 0;
967*4882a593Smuzhiyun 	skb_queue_head_init(&zatm_vcc->backlog);
968*4882a593Smuzhiyun 	zpokel(zatm_dev,virt_to_bus(zatm_vcc->ring),
969*4882a593Smuzhiyun 	    chan*VC_SIZE/4+uPD98401_TXVC_QRP);
970*4882a593Smuzhiyun 	return 0;
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 
open_tx_second(struct atm_vcc * vcc)974*4882a593Smuzhiyun static int open_tx_second(struct atm_vcc *vcc)
975*4882a593Smuzhiyun {
976*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
977*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
978*4882a593Smuzhiyun 	unsigned long flags;
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	DPRINTK("open_tx_second\n");
981*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(vcc->dev);
982*4882a593Smuzhiyun 	zatm_vcc = ZATM_VCC(vcc);
983*4882a593Smuzhiyun 	if (!zatm_vcc->tx_chan) return 0;
984*4882a593Smuzhiyun 	/* set up VC descriptor */
985*4882a593Smuzhiyun 	spin_lock_irqsave(&zatm_dev->lock, flags);
986*4882a593Smuzhiyun 	zpokel(zatm_dev,0,zatm_vcc->tx_chan*VC_SIZE/4);
987*4882a593Smuzhiyun 	zpokel(zatm_dev,uPD98401_TXVC_L | (zatm_vcc->shaper <<
988*4882a593Smuzhiyun 	    uPD98401_TXVC_SHP_SHIFT) | (vcc->vpi << uPD98401_TXVC_VPI_SHIFT) |
989*4882a593Smuzhiyun 	    vcc->vci,zatm_vcc->tx_chan*VC_SIZE/4+1);
990*4882a593Smuzhiyun 	zpokel(zatm_dev,0,zatm_vcc->tx_chan*VC_SIZE/4+2);
991*4882a593Smuzhiyun 	spin_unlock_irqrestore(&zatm_dev->lock, flags);
992*4882a593Smuzhiyun 	zatm_dev->tx_map[zatm_vcc->tx_chan] = vcc;
993*4882a593Smuzhiyun 	return 0;
994*4882a593Smuzhiyun }
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 
start_tx(struct atm_dev * dev)997*4882a593Smuzhiyun static int start_tx(struct atm_dev *dev)
998*4882a593Smuzhiyun {
999*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1000*4882a593Smuzhiyun 	int i;
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	DPRINTK("start_tx\n");
1003*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1004*4882a593Smuzhiyun 	zatm_dev->tx_map = kmalloc_array(zatm_dev->chans,
1005*4882a593Smuzhiyun 					 sizeof(*zatm_dev->tx_map),
1006*4882a593Smuzhiyun 					 GFP_KERNEL);
1007*4882a593Smuzhiyun 	if (!zatm_dev->tx_map) return -ENOMEM;
1008*4882a593Smuzhiyun 	zatm_dev->tx_bw = ATM_OC3_PCR;
1009*4882a593Smuzhiyun 	zatm_dev->free_shapers = (1 << NR_SHAPERS)-1;
1010*4882a593Smuzhiyun 	zatm_dev->ubr = -1;
1011*4882a593Smuzhiyun 	zatm_dev->ubr_ref_cnt = 0;
1012*4882a593Smuzhiyun 	/* initialize shapers */
1013*4882a593Smuzhiyun 	for (i = 0; i < NR_SHAPERS; i++) zpokel(zatm_dev,0,uPD98401_PS(i));
1014*4882a593Smuzhiyun 	return 0;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun /*------------------------------- interrupts --------------------------------*/
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 
zatm_int(int irq,void * dev_id)1021*4882a593Smuzhiyun static irqreturn_t zatm_int(int irq,void *dev_id)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun 	struct atm_dev *dev;
1024*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1025*4882a593Smuzhiyun 	u32 reason;
1026*4882a593Smuzhiyun 	int handled = 0;
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	dev = dev_id;
1029*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1030*4882a593Smuzhiyun 	while ((reason = zin(GSR))) {
1031*4882a593Smuzhiyun 		handled = 1;
1032*4882a593Smuzhiyun 		EVENT("reason 0x%x\n",reason,0);
1033*4882a593Smuzhiyun 		if (reason & uPD98401_INT_PI) {
1034*4882a593Smuzhiyun 			EVENT("PHY int\n",0,0);
1035*4882a593Smuzhiyun 			dev->phy->interrupt(dev);
1036*4882a593Smuzhiyun 		}
1037*4882a593Smuzhiyun 		if (reason & uPD98401_INT_RQA) {
1038*4882a593Smuzhiyun 			unsigned long pools;
1039*4882a593Smuzhiyun 			int i;
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 			pools = zin(RQA);
1042*4882a593Smuzhiyun 			EVENT("RQA (0x%08x)\n",pools,0);
1043*4882a593Smuzhiyun 			for (i = 0; pools; i++) {
1044*4882a593Smuzhiyun 				if (pools & 1) {
1045*4882a593Smuzhiyun 					refill_pool(dev,i);
1046*4882a593Smuzhiyun 					zatm_dev->pool_info[i].rqa_count++;
1047*4882a593Smuzhiyun 				}
1048*4882a593Smuzhiyun 				pools >>= 1;
1049*4882a593Smuzhiyun 			}
1050*4882a593Smuzhiyun 		}
1051*4882a593Smuzhiyun 		if (reason & uPD98401_INT_RQU) {
1052*4882a593Smuzhiyun 			unsigned long pools;
1053*4882a593Smuzhiyun 			int i;
1054*4882a593Smuzhiyun 			pools = zin(RQU);
1055*4882a593Smuzhiyun 			printk(KERN_WARNING DEV_LABEL "(itf %d): RQU 0x%08lx\n",
1056*4882a593Smuzhiyun 			    dev->number,pools);
1057*4882a593Smuzhiyun 			event_dump();
1058*4882a593Smuzhiyun 			for (i = 0; pools; i++) {
1059*4882a593Smuzhiyun 				if (pools & 1) {
1060*4882a593Smuzhiyun 					refill_pool(dev,i);
1061*4882a593Smuzhiyun 					zatm_dev->pool_info[i].rqu_count++;
1062*4882a593Smuzhiyun 				}
1063*4882a593Smuzhiyun 				pools >>= 1;
1064*4882a593Smuzhiyun 			}
1065*4882a593Smuzhiyun 		}
1066*4882a593Smuzhiyun 		/* don't handle RD */
1067*4882a593Smuzhiyun 		if (reason & uPD98401_INT_SPE)
1068*4882a593Smuzhiyun 			printk(KERN_ALERT DEV_LABEL "(itf %d): system parity "
1069*4882a593Smuzhiyun 			    "error at 0x%08x\n",dev->number,zin(ADDR));
1070*4882a593Smuzhiyun 		if (reason & uPD98401_INT_CPE)
1071*4882a593Smuzhiyun 			printk(KERN_ALERT DEV_LABEL "(itf %d): control memory "
1072*4882a593Smuzhiyun 			    "parity error at 0x%08x\n",dev->number,zin(ADDR));
1073*4882a593Smuzhiyun 		if (reason & uPD98401_INT_SBE) {
1074*4882a593Smuzhiyun 			printk(KERN_ALERT DEV_LABEL "(itf %d): system bus "
1075*4882a593Smuzhiyun 			    "error at 0x%08x\n",dev->number,zin(ADDR));
1076*4882a593Smuzhiyun 			event_dump();
1077*4882a593Smuzhiyun 		}
1078*4882a593Smuzhiyun 		/* don't handle IND */
1079*4882a593Smuzhiyun 		if (reason & uPD98401_INT_MF) {
1080*4882a593Smuzhiyun 			printk(KERN_CRIT DEV_LABEL "(itf %d): mailbox full "
1081*4882a593Smuzhiyun 			    "(0x%x)\n",dev->number,(reason & uPD98401_INT_MF)
1082*4882a593Smuzhiyun 			    >> uPD98401_INT_MF_SHIFT);
1083*4882a593Smuzhiyun 			event_dump();
1084*4882a593Smuzhiyun 			    /* @@@ should try to recover */
1085*4882a593Smuzhiyun 		}
1086*4882a593Smuzhiyun 		if (reason & uPD98401_INT_MM) {
1087*4882a593Smuzhiyun 			if (reason & 1) poll_rx(dev,0);
1088*4882a593Smuzhiyun 			if (reason & 2) poll_rx(dev,1);
1089*4882a593Smuzhiyun 			if (reason & 4) poll_tx(dev,2);
1090*4882a593Smuzhiyun 			if (reason & 8) poll_tx(dev,3);
1091*4882a593Smuzhiyun 		}
1092*4882a593Smuzhiyun 		/* @@@ handle RCRn */
1093*4882a593Smuzhiyun 	}
1094*4882a593Smuzhiyun 	return IRQ_RETVAL(handled);
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun /*----------------------------- (E)EPROM access -----------------------------*/
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 
eprom_set(struct zatm_dev * zatm_dev,unsigned long value,unsigned short cmd)1101*4882a593Smuzhiyun static void eprom_set(struct zatm_dev *zatm_dev, unsigned long value,
1102*4882a593Smuzhiyun 		      unsigned short cmd)
1103*4882a593Smuzhiyun {
1104*4882a593Smuzhiyun 	int error;
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	if ((error = pci_write_config_dword(zatm_dev->pci_dev,cmd,value)))
1107*4882a593Smuzhiyun 		printk(KERN_ERR DEV_LABEL ": PCI write failed (0x%02x)\n",
1108*4882a593Smuzhiyun 		    error);
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 
eprom_get(struct zatm_dev * zatm_dev,unsigned short cmd)1112*4882a593Smuzhiyun static unsigned long eprom_get(struct zatm_dev *zatm_dev, unsigned short cmd)
1113*4882a593Smuzhiyun {
1114*4882a593Smuzhiyun 	unsigned int value;
1115*4882a593Smuzhiyun 	int error;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	if ((error = pci_read_config_dword(zatm_dev->pci_dev,cmd,&value)))
1118*4882a593Smuzhiyun 		printk(KERN_ERR DEV_LABEL ": PCI read failed (0x%02x)\n",
1119*4882a593Smuzhiyun 		    error);
1120*4882a593Smuzhiyun 	return value;
1121*4882a593Smuzhiyun }
1122*4882a593Smuzhiyun 
1123*4882a593Smuzhiyun 
eprom_put_bits(struct zatm_dev * zatm_dev,unsigned long data,int bits,unsigned short cmd)1124*4882a593Smuzhiyun static void eprom_put_bits(struct zatm_dev *zatm_dev, unsigned long data,
1125*4882a593Smuzhiyun 			   int bits, unsigned short cmd)
1126*4882a593Smuzhiyun {
1127*4882a593Smuzhiyun 	unsigned long value;
1128*4882a593Smuzhiyun 	int i;
1129*4882a593Smuzhiyun 
1130*4882a593Smuzhiyun 	for (i = bits-1; i >= 0; i--) {
1131*4882a593Smuzhiyun 		value = ZEPROM_CS | (((data >> i) & 1) ? ZEPROM_DI : 0);
1132*4882a593Smuzhiyun 		eprom_set(zatm_dev,value,cmd);
1133*4882a593Smuzhiyun 		eprom_set(zatm_dev,value | ZEPROM_SK,cmd);
1134*4882a593Smuzhiyun 		eprom_set(zatm_dev,value,cmd);
1135*4882a593Smuzhiyun 	}
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 
eprom_get_byte(struct zatm_dev * zatm_dev,unsigned char * byte,unsigned short cmd)1139*4882a593Smuzhiyun static void eprom_get_byte(struct zatm_dev *zatm_dev, unsigned char *byte,
1140*4882a593Smuzhiyun 			   unsigned short cmd)
1141*4882a593Smuzhiyun {
1142*4882a593Smuzhiyun 	int i;
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	*byte = 0;
1145*4882a593Smuzhiyun 	for (i = 8; i; i--) {
1146*4882a593Smuzhiyun 		eprom_set(zatm_dev,ZEPROM_CS,cmd);
1147*4882a593Smuzhiyun 		eprom_set(zatm_dev,ZEPROM_CS | ZEPROM_SK,cmd);
1148*4882a593Smuzhiyun 		*byte <<= 1;
1149*4882a593Smuzhiyun 		if (eprom_get(zatm_dev,cmd) & ZEPROM_DO) *byte |= 1;
1150*4882a593Smuzhiyun 		eprom_set(zatm_dev,ZEPROM_CS,cmd);
1151*4882a593Smuzhiyun 	}
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 
eprom_try_esi(struct atm_dev * dev,unsigned short cmd,int offset,int swap)1155*4882a593Smuzhiyun static int eprom_try_esi(struct atm_dev *dev, unsigned short cmd, int offset,
1156*4882a593Smuzhiyun 			 int swap)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun 	unsigned char buf[ZEPROM_SIZE];
1159*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1160*4882a593Smuzhiyun 	int i;
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1163*4882a593Smuzhiyun 	for (i = 0; i < ZEPROM_SIZE; i += 2) {
1164*4882a593Smuzhiyun 		eprom_set(zatm_dev,ZEPROM_CS,cmd); /* select EPROM */
1165*4882a593Smuzhiyun 		eprom_put_bits(zatm_dev,ZEPROM_CMD_READ,ZEPROM_CMD_LEN,cmd);
1166*4882a593Smuzhiyun 		eprom_put_bits(zatm_dev,i >> 1,ZEPROM_ADDR_LEN,cmd);
1167*4882a593Smuzhiyun 		eprom_get_byte(zatm_dev,buf+i+swap,cmd);
1168*4882a593Smuzhiyun 		eprom_get_byte(zatm_dev,buf+i+1-swap,cmd);
1169*4882a593Smuzhiyun 		eprom_set(zatm_dev,0,cmd); /* deselect EPROM */
1170*4882a593Smuzhiyun 	}
1171*4882a593Smuzhiyun 	memcpy(dev->esi,buf+offset,ESI_LEN);
1172*4882a593Smuzhiyun 	return memcmp(dev->esi,"\0\0\0\0\0",ESI_LEN); /* assumes ESI_LEN == 6 */
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun 
1175*4882a593Smuzhiyun 
eprom_get_esi(struct atm_dev * dev)1176*4882a593Smuzhiyun static void eprom_get_esi(struct atm_dev *dev)
1177*4882a593Smuzhiyun {
1178*4882a593Smuzhiyun 	if (eprom_try_esi(dev,ZEPROM_V1_REG,ZEPROM_V1_ESI_OFF,1)) return;
1179*4882a593Smuzhiyun 	(void) eprom_try_esi(dev,ZEPROM_V2_REG,ZEPROM_V2_ESI_OFF,0);
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun 
1182*4882a593Smuzhiyun 
1183*4882a593Smuzhiyun /*--------------------------------- entries ---------------------------------*/
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 
zatm_init(struct atm_dev * dev)1186*4882a593Smuzhiyun static int zatm_init(struct atm_dev *dev)
1187*4882a593Smuzhiyun {
1188*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1189*4882a593Smuzhiyun 	struct pci_dev *pci_dev;
1190*4882a593Smuzhiyun 	unsigned short command;
1191*4882a593Smuzhiyun 	int error,i,last;
1192*4882a593Smuzhiyun 	unsigned long t0,t1,t2;
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun 	DPRINTK(">zatm_init\n");
1195*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1196*4882a593Smuzhiyun 	spin_lock_init(&zatm_dev->lock);
1197*4882a593Smuzhiyun 	pci_dev = zatm_dev->pci_dev;
1198*4882a593Smuzhiyun 	zatm_dev->base = pci_resource_start(pci_dev, 0);
1199*4882a593Smuzhiyun 	zatm_dev->irq = pci_dev->irq;
1200*4882a593Smuzhiyun 	if ((error = pci_read_config_word(pci_dev,PCI_COMMAND,&command))) {
1201*4882a593Smuzhiyun 		printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%02x\n",
1202*4882a593Smuzhiyun 		    dev->number,error);
1203*4882a593Smuzhiyun 		return -EINVAL;
1204*4882a593Smuzhiyun 	}
1205*4882a593Smuzhiyun 	if ((error = pci_write_config_word(pci_dev,PCI_COMMAND,
1206*4882a593Smuzhiyun 	    command | PCI_COMMAND_IO | PCI_COMMAND_MASTER))) {
1207*4882a593Smuzhiyun 		printk(KERN_ERR DEV_LABEL "(itf %d): can't enable IO (0x%02x)"
1208*4882a593Smuzhiyun 		    "\n",dev->number,error);
1209*4882a593Smuzhiyun 		return -EIO;
1210*4882a593Smuzhiyun 	}
1211*4882a593Smuzhiyun 	eprom_get_esi(dev);
1212*4882a593Smuzhiyun 	printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d,base=0x%x,irq=%d,",
1213*4882a593Smuzhiyun 	    dev->number,pci_dev->revision,zatm_dev->base,zatm_dev->irq);
1214*4882a593Smuzhiyun 	/* reset uPD98401 */
1215*4882a593Smuzhiyun 	zout(0,SWR);
1216*4882a593Smuzhiyun 	while (!(zin(GSR) & uPD98401_INT_IND));
1217*4882a593Smuzhiyun 	zout(uPD98401_GMR_ONE /*uPD98401_BURST4*/,GMR);
1218*4882a593Smuzhiyun 	last = MAX_CRAM_SIZE;
1219*4882a593Smuzhiyun 	for (i = last-RAM_INCREMENT; i >= 0; i -= RAM_INCREMENT) {
1220*4882a593Smuzhiyun 		zpokel(zatm_dev,0x55555555,i);
1221*4882a593Smuzhiyun 		if (zpeekl(zatm_dev,i) != 0x55555555) last = i;
1222*4882a593Smuzhiyun 		else {
1223*4882a593Smuzhiyun 			zpokel(zatm_dev,0xAAAAAAAA,i);
1224*4882a593Smuzhiyun 			if (zpeekl(zatm_dev,i) != 0xAAAAAAAA) last = i;
1225*4882a593Smuzhiyun 			else zpokel(zatm_dev,i,i);
1226*4882a593Smuzhiyun 		}
1227*4882a593Smuzhiyun 	}
1228*4882a593Smuzhiyun 	for (i = 0; i < last; i += RAM_INCREMENT)
1229*4882a593Smuzhiyun 		if (zpeekl(zatm_dev,i) != i) break;
1230*4882a593Smuzhiyun 	zatm_dev->mem = i << 2;
1231*4882a593Smuzhiyun 	while (i) zpokel(zatm_dev,0,--i);
1232*4882a593Smuzhiyun 	/* reset again to rebuild memory pointers */
1233*4882a593Smuzhiyun 	zout(0,SWR);
1234*4882a593Smuzhiyun 	while (!(zin(GSR) & uPD98401_INT_IND));
1235*4882a593Smuzhiyun 	zout(uPD98401_GMR_ONE | uPD98401_BURST8 | uPD98401_BURST4 |
1236*4882a593Smuzhiyun 	    uPD98401_BURST2 | uPD98401_GMR_PM | uPD98401_GMR_DR,GMR);
1237*4882a593Smuzhiyun 	/* TODO: should shrink allocation now */
1238*4882a593Smuzhiyun 	printk("mem=%dkB,%s (",zatm_dev->mem >> 10,zatm_dev->copper ? "UTP" :
1239*4882a593Smuzhiyun 	    "MMF");
1240*4882a593Smuzhiyun 	for (i = 0; i < ESI_LEN; i++)
1241*4882a593Smuzhiyun 		printk("%02X%s",dev->esi[i],i == ESI_LEN-1 ? ")\n" : "-");
1242*4882a593Smuzhiyun 	do {
1243*4882a593Smuzhiyun 		unsigned long flags;
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun 		spin_lock_irqsave(&zatm_dev->lock, flags);
1246*4882a593Smuzhiyun 		t0 = zpeekl(zatm_dev,uPD98401_TSR);
1247*4882a593Smuzhiyun 		udelay(10);
1248*4882a593Smuzhiyun 		t1 = zpeekl(zatm_dev,uPD98401_TSR);
1249*4882a593Smuzhiyun 		udelay(1010);
1250*4882a593Smuzhiyun 		t2 = zpeekl(zatm_dev,uPD98401_TSR);
1251*4882a593Smuzhiyun 		spin_unlock_irqrestore(&zatm_dev->lock, flags);
1252*4882a593Smuzhiyun 	}
1253*4882a593Smuzhiyun 	while (t0 > t1 || t1 > t2); /* loop if wrapping ... */
1254*4882a593Smuzhiyun 	zatm_dev->khz = t2-2*t1+t0;
1255*4882a593Smuzhiyun 	printk(KERN_NOTICE DEV_LABEL "(itf %d): uPD98401 %d.%d at %d.%03d "
1256*4882a593Smuzhiyun 	    "MHz\n",dev->number,
1257*4882a593Smuzhiyun 	    (zin(VER) & uPD98401_MAJOR) >> uPD98401_MAJOR_SHIFT,
1258*4882a593Smuzhiyun             zin(VER) & uPD98401_MINOR,zatm_dev->khz/1000,zatm_dev->khz % 1000);
1259*4882a593Smuzhiyun 	return uPD98402_init(dev);
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun 
1262*4882a593Smuzhiyun 
zatm_start(struct atm_dev * dev)1263*4882a593Smuzhiyun static int zatm_start(struct atm_dev *dev)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev = ZATM_DEV(dev);
1266*4882a593Smuzhiyun 	struct pci_dev *pdev = zatm_dev->pci_dev;
1267*4882a593Smuzhiyun 	unsigned long curr;
1268*4882a593Smuzhiyun 	int pools,vccs,rx;
1269*4882a593Smuzhiyun 	int error, i, ld;
1270*4882a593Smuzhiyun 
1271*4882a593Smuzhiyun 	DPRINTK("zatm_start\n");
1272*4882a593Smuzhiyun 	zatm_dev->rx_map = zatm_dev->tx_map = NULL;
1273*4882a593Smuzhiyun  	for (i = 0; i < NR_MBX; i++)
1274*4882a593Smuzhiyun  		zatm_dev->mbx_start[i] = 0;
1275*4882a593Smuzhiyun  	error = request_irq(zatm_dev->irq, zatm_int, IRQF_SHARED, DEV_LABEL, dev);
1276*4882a593Smuzhiyun 	if (error < 0) {
1277*4882a593Smuzhiyun  		printk(KERN_ERR DEV_LABEL "(itf %d): IRQ%d is already in use\n",
1278*4882a593Smuzhiyun  		    dev->number,zatm_dev->irq);
1279*4882a593Smuzhiyun 		goto done;
1280*4882a593Smuzhiyun 	}
1281*4882a593Smuzhiyun 	/* define memory regions */
1282*4882a593Smuzhiyun 	pools = NR_POOLS;
1283*4882a593Smuzhiyun 	if (NR_SHAPERS*SHAPER_SIZE > pools*POOL_SIZE)
1284*4882a593Smuzhiyun 		pools = NR_SHAPERS*SHAPER_SIZE/POOL_SIZE;
1285*4882a593Smuzhiyun 	vccs = (zatm_dev->mem-NR_SHAPERS*SHAPER_SIZE-pools*POOL_SIZE)/
1286*4882a593Smuzhiyun 	    (2*VC_SIZE+RX_SIZE);
1287*4882a593Smuzhiyun 	ld = -1;
1288*4882a593Smuzhiyun 	for (rx = 1; rx < vccs; rx <<= 1) ld++;
1289*4882a593Smuzhiyun 	dev->ci_range.vpi_bits = 0; /* @@@ no VPI for now */
1290*4882a593Smuzhiyun 	dev->ci_range.vci_bits = ld;
1291*4882a593Smuzhiyun 	dev->link_rate = ATM_OC3_PCR;
1292*4882a593Smuzhiyun 	zatm_dev->chans = vccs; /* ??? */
1293*4882a593Smuzhiyun 	curr = rx*RX_SIZE/4;
1294*4882a593Smuzhiyun 	DPRINTK("RX pool 0x%08lx\n",curr);
1295*4882a593Smuzhiyun 	zpokel(zatm_dev,curr,uPD98401_PMA); /* receive pool */
1296*4882a593Smuzhiyun 	zatm_dev->pool_base = curr;
1297*4882a593Smuzhiyun 	curr += pools*POOL_SIZE/4;
1298*4882a593Smuzhiyun 	DPRINTK("Shapers 0x%08lx\n",curr);
1299*4882a593Smuzhiyun 	zpokel(zatm_dev,curr,uPD98401_SMA); /* shapers */
1300*4882a593Smuzhiyun 	curr += NR_SHAPERS*SHAPER_SIZE/4;
1301*4882a593Smuzhiyun 	DPRINTK("Free    0x%08lx\n",curr);
1302*4882a593Smuzhiyun 	zpokel(zatm_dev,curr,uPD98401_TOS); /* free pool */
1303*4882a593Smuzhiyun 	printk(KERN_INFO DEV_LABEL "(itf %d): %d shapers, %d pools, %d RX, "
1304*4882a593Smuzhiyun 	    "%ld VCs\n",dev->number,NR_SHAPERS,pools,rx,
1305*4882a593Smuzhiyun 	    (zatm_dev->mem-curr*4)/VC_SIZE);
1306*4882a593Smuzhiyun 	/* create mailboxes */
1307*4882a593Smuzhiyun 	for (i = 0; i < NR_MBX; i++) {
1308*4882a593Smuzhiyun 		void *mbx;
1309*4882a593Smuzhiyun 		dma_addr_t mbx_dma;
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 		if (!mbx_entries[i])
1312*4882a593Smuzhiyun 			continue;
1313*4882a593Smuzhiyun 		mbx = dma_alloc_coherent(&pdev->dev,
1314*4882a593Smuzhiyun 					 2 * MBX_SIZE(i), &mbx_dma, GFP_KERNEL);
1315*4882a593Smuzhiyun 		if (!mbx) {
1316*4882a593Smuzhiyun 			error = -ENOMEM;
1317*4882a593Smuzhiyun 			goto out;
1318*4882a593Smuzhiyun 		}
1319*4882a593Smuzhiyun 		/*
1320*4882a593Smuzhiyun 		 * Alignment provided by dma_alloc_coherent() isn't enough
1321*4882a593Smuzhiyun 		 * for this device.
1322*4882a593Smuzhiyun 		 */
1323*4882a593Smuzhiyun 		if (((unsigned long)mbx ^ mbx_dma) & 0xffff) {
1324*4882a593Smuzhiyun 			printk(KERN_ERR DEV_LABEL "(itf %d): system "
1325*4882a593Smuzhiyun 			       "bus incompatible with driver\n", dev->number);
1326*4882a593Smuzhiyun 			dma_free_coherent(&pdev->dev, 2*MBX_SIZE(i), mbx, mbx_dma);
1327*4882a593Smuzhiyun 			error = -ENODEV;
1328*4882a593Smuzhiyun 			goto out;
1329*4882a593Smuzhiyun 		}
1330*4882a593Smuzhiyun 		DPRINTK("mbx@0x%08lx-0x%08lx\n", mbx, mbx + MBX_SIZE(i));
1331*4882a593Smuzhiyun 		zatm_dev->mbx_start[i] = (unsigned long)mbx;
1332*4882a593Smuzhiyun 		zatm_dev->mbx_dma[i] = mbx_dma;
1333*4882a593Smuzhiyun 		zatm_dev->mbx_end[i] = (zatm_dev->mbx_start[i] + MBX_SIZE(i)) &
1334*4882a593Smuzhiyun 					0xffff;
1335*4882a593Smuzhiyun 		zout(mbx_dma >> 16, MSH(i));
1336*4882a593Smuzhiyun 		zout(mbx_dma, MSL(i));
1337*4882a593Smuzhiyun 		zout(zatm_dev->mbx_end[i], MBA(i));
1338*4882a593Smuzhiyun 		zout((unsigned long)mbx & 0xffff, MTA(i));
1339*4882a593Smuzhiyun 		zout((unsigned long)mbx & 0xffff, MWA(i));
1340*4882a593Smuzhiyun 	}
1341*4882a593Smuzhiyun 	error = start_tx(dev);
1342*4882a593Smuzhiyun 	if (error)
1343*4882a593Smuzhiyun 		goto out;
1344*4882a593Smuzhiyun 	error = start_rx(dev);
1345*4882a593Smuzhiyun 	if (error)
1346*4882a593Smuzhiyun 		goto out_tx;
1347*4882a593Smuzhiyun 	error = dev->phy->start(dev);
1348*4882a593Smuzhiyun 	if (error)
1349*4882a593Smuzhiyun 		goto out_rx;
1350*4882a593Smuzhiyun 	zout(0xffffffff,IMR); /* enable interrupts */
1351*4882a593Smuzhiyun 	/* enable TX & RX */
1352*4882a593Smuzhiyun 	zout(zin(GMR) | uPD98401_GMR_SE | uPD98401_GMR_RE,GMR);
1353*4882a593Smuzhiyun done:
1354*4882a593Smuzhiyun 	return error;
1355*4882a593Smuzhiyun 
1356*4882a593Smuzhiyun out_rx:
1357*4882a593Smuzhiyun 	kfree(zatm_dev->rx_map);
1358*4882a593Smuzhiyun out_tx:
1359*4882a593Smuzhiyun 	kfree(zatm_dev->tx_map);
1360*4882a593Smuzhiyun out:
1361*4882a593Smuzhiyun 	while (i-- > 0) {
1362*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, 2 * MBX_SIZE(i),
1363*4882a593Smuzhiyun 				  (void *)zatm_dev->mbx_start[i],
1364*4882a593Smuzhiyun 				  zatm_dev->mbx_dma[i]);
1365*4882a593Smuzhiyun 	}
1366*4882a593Smuzhiyun 	free_irq(zatm_dev->irq, dev);
1367*4882a593Smuzhiyun 	goto done;
1368*4882a593Smuzhiyun }
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 
zatm_close(struct atm_vcc * vcc)1371*4882a593Smuzhiyun static void zatm_close(struct atm_vcc *vcc)
1372*4882a593Smuzhiyun {
1373*4882a593Smuzhiyun         DPRINTK(">zatm_close\n");
1374*4882a593Smuzhiyun         if (!ZATM_VCC(vcc)) return;
1375*4882a593Smuzhiyun 	clear_bit(ATM_VF_READY,&vcc->flags);
1376*4882a593Smuzhiyun         close_rx(vcc);
1377*4882a593Smuzhiyun 	EVENT("close_tx\n",0,0);
1378*4882a593Smuzhiyun         close_tx(vcc);
1379*4882a593Smuzhiyun         DPRINTK("zatm_close: done waiting\n");
1380*4882a593Smuzhiyun         /* deallocate memory */
1381*4882a593Smuzhiyun         kfree(ZATM_VCC(vcc));
1382*4882a593Smuzhiyun 	vcc->dev_data = NULL;
1383*4882a593Smuzhiyun 	clear_bit(ATM_VF_ADDR,&vcc->flags);
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun 
1386*4882a593Smuzhiyun 
zatm_open(struct atm_vcc * vcc)1387*4882a593Smuzhiyun static int zatm_open(struct atm_vcc *vcc)
1388*4882a593Smuzhiyun {
1389*4882a593Smuzhiyun 	struct zatm_vcc *zatm_vcc;
1390*4882a593Smuzhiyun 	short vpi = vcc->vpi;
1391*4882a593Smuzhiyun 	int vci = vcc->vci;
1392*4882a593Smuzhiyun 	int error;
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	DPRINTK(">zatm_open\n");
1395*4882a593Smuzhiyun 	if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
1396*4882a593Smuzhiyun 		vcc->dev_data = NULL;
1397*4882a593Smuzhiyun 	if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
1398*4882a593Smuzhiyun 		set_bit(ATM_VF_ADDR,&vcc->flags);
1399*4882a593Smuzhiyun 	if (vcc->qos.aal != ATM_AAL5) return -EINVAL; /* @@@ AAL0 */
1400*4882a593Smuzhiyun 	DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n",vcc->dev->number,vcc->vpi,
1401*4882a593Smuzhiyun 	    vcc->vci);
1402*4882a593Smuzhiyun 	if (!test_bit(ATM_VF_PARTIAL,&vcc->flags)) {
1403*4882a593Smuzhiyun 		zatm_vcc = kmalloc(sizeof(*zatm_vcc), GFP_KERNEL);
1404*4882a593Smuzhiyun 		if (!zatm_vcc) {
1405*4882a593Smuzhiyun 			clear_bit(ATM_VF_ADDR,&vcc->flags);
1406*4882a593Smuzhiyun 			return -ENOMEM;
1407*4882a593Smuzhiyun 		}
1408*4882a593Smuzhiyun 		vcc->dev_data = zatm_vcc;
1409*4882a593Smuzhiyun 		ZATM_VCC(vcc)->tx_chan = 0; /* for zatm_close after open_rx */
1410*4882a593Smuzhiyun 		if ((error = open_rx_first(vcc))) {
1411*4882a593Smuzhiyun 	                zatm_close(vcc);
1412*4882a593Smuzhiyun 	                return error;
1413*4882a593Smuzhiyun 	        }
1414*4882a593Smuzhiyun 		if ((error = open_tx_first(vcc))) {
1415*4882a593Smuzhiyun 			zatm_close(vcc);
1416*4882a593Smuzhiyun 			return error;
1417*4882a593Smuzhiyun 	        }
1418*4882a593Smuzhiyun 	}
1419*4882a593Smuzhiyun 	if (vci == ATM_VPI_UNSPEC || vpi == ATM_VCI_UNSPEC) return 0;
1420*4882a593Smuzhiyun 	if ((error = open_rx_second(vcc))) {
1421*4882a593Smuzhiyun 		zatm_close(vcc);
1422*4882a593Smuzhiyun 		return error;
1423*4882a593Smuzhiyun         }
1424*4882a593Smuzhiyun 	if ((error = open_tx_second(vcc))) {
1425*4882a593Smuzhiyun 		zatm_close(vcc);
1426*4882a593Smuzhiyun 		return error;
1427*4882a593Smuzhiyun         }
1428*4882a593Smuzhiyun 	set_bit(ATM_VF_READY,&vcc->flags);
1429*4882a593Smuzhiyun         return 0;
1430*4882a593Smuzhiyun }
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun 
zatm_change_qos(struct atm_vcc * vcc,struct atm_qos * qos,int flags)1433*4882a593Smuzhiyun static int zatm_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
1434*4882a593Smuzhiyun {
1435*4882a593Smuzhiyun 	printk("Not yet implemented\n");
1436*4882a593Smuzhiyun 	return -ENOSYS;
1437*4882a593Smuzhiyun 	/* @@@ */
1438*4882a593Smuzhiyun }
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 
zatm_ioctl(struct atm_dev * dev,unsigned int cmd,void __user * arg)1441*4882a593Smuzhiyun static int zatm_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
1442*4882a593Smuzhiyun {
1443*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1444*4882a593Smuzhiyun 	unsigned long flags;
1445*4882a593Smuzhiyun 
1446*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1447*4882a593Smuzhiyun 	switch (cmd) {
1448*4882a593Smuzhiyun 		case ZATM_GETPOOLZ:
1449*4882a593Smuzhiyun 			if (!capable(CAP_NET_ADMIN)) return -EPERM;
1450*4882a593Smuzhiyun 			fallthrough;
1451*4882a593Smuzhiyun 		case ZATM_GETPOOL:
1452*4882a593Smuzhiyun 			{
1453*4882a593Smuzhiyun 				struct zatm_pool_info info;
1454*4882a593Smuzhiyun 				int pool;
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 				if (get_user(pool,
1457*4882a593Smuzhiyun 				    &((struct zatm_pool_req __user *) arg)->pool_num))
1458*4882a593Smuzhiyun 					return -EFAULT;
1459*4882a593Smuzhiyun 				if (pool < 0 || pool > ZATM_LAST_POOL)
1460*4882a593Smuzhiyun 					return -EINVAL;
1461*4882a593Smuzhiyun 				pool = array_index_nospec(pool,
1462*4882a593Smuzhiyun 							  ZATM_LAST_POOL + 1);
1463*4882a593Smuzhiyun 				spin_lock_irqsave(&zatm_dev->lock, flags);
1464*4882a593Smuzhiyun 				info = zatm_dev->pool_info[pool];
1465*4882a593Smuzhiyun 				if (cmd == ZATM_GETPOOLZ) {
1466*4882a593Smuzhiyun 					zatm_dev->pool_info[pool].rqa_count = 0;
1467*4882a593Smuzhiyun 					zatm_dev->pool_info[pool].rqu_count = 0;
1468*4882a593Smuzhiyun 				}
1469*4882a593Smuzhiyun 				spin_unlock_irqrestore(&zatm_dev->lock, flags);
1470*4882a593Smuzhiyun 				return copy_to_user(
1471*4882a593Smuzhiyun 				    &((struct zatm_pool_req __user *) arg)->info,
1472*4882a593Smuzhiyun 				    &info,sizeof(info)) ? -EFAULT : 0;
1473*4882a593Smuzhiyun 			}
1474*4882a593Smuzhiyun 		case ZATM_SETPOOL:
1475*4882a593Smuzhiyun 			{
1476*4882a593Smuzhiyun 				struct zatm_pool_info info;
1477*4882a593Smuzhiyun 				int pool;
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 				if (!capable(CAP_NET_ADMIN)) return -EPERM;
1480*4882a593Smuzhiyun 				if (get_user(pool,
1481*4882a593Smuzhiyun 				    &((struct zatm_pool_req __user *) arg)->pool_num))
1482*4882a593Smuzhiyun 					return -EFAULT;
1483*4882a593Smuzhiyun 				if (pool < 0 || pool > ZATM_LAST_POOL)
1484*4882a593Smuzhiyun 					return -EINVAL;
1485*4882a593Smuzhiyun 				pool = array_index_nospec(pool,
1486*4882a593Smuzhiyun 							  ZATM_LAST_POOL + 1);
1487*4882a593Smuzhiyun 				if (copy_from_user(&info,
1488*4882a593Smuzhiyun 				    &((struct zatm_pool_req __user *) arg)->info,
1489*4882a593Smuzhiyun 				    sizeof(info))) return -EFAULT;
1490*4882a593Smuzhiyun 				if (!info.low_water)
1491*4882a593Smuzhiyun 					info.low_water = zatm_dev->
1492*4882a593Smuzhiyun 					    pool_info[pool].low_water;
1493*4882a593Smuzhiyun 				if (!info.high_water)
1494*4882a593Smuzhiyun 					info.high_water = zatm_dev->
1495*4882a593Smuzhiyun 					    pool_info[pool].high_water;
1496*4882a593Smuzhiyun 				if (!info.next_thres)
1497*4882a593Smuzhiyun 					info.next_thres = zatm_dev->
1498*4882a593Smuzhiyun 					    pool_info[pool].next_thres;
1499*4882a593Smuzhiyun 				if (info.low_water >= info.high_water ||
1500*4882a593Smuzhiyun 				    info.low_water < 0)
1501*4882a593Smuzhiyun 					return -EINVAL;
1502*4882a593Smuzhiyun 				spin_lock_irqsave(&zatm_dev->lock, flags);
1503*4882a593Smuzhiyun 				zatm_dev->pool_info[pool].low_water =
1504*4882a593Smuzhiyun 				    info.low_water;
1505*4882a593Smuzhiyun 				zatm_dev->pool_info[pool].high_water =
1506*4882a593Smuzhiyun 				    info.high_water;
1507*4882a593Smuzhiyun 				zatm_dev->pool_info[pool].next_thres =
1508*4882a593Smuzhiyun 				    info.next_thres;
1509*4882a593Smuzhiyun 				spin_unlock_irqrestore(&zatm_dev->lock, flags);
1510*4882a593Smuzhiyun 				return 0;
1511*4882a593Smuzhiyun 			}
1512*4882a593Smuzhiyun 		default:
1513*4882a593Smuzhiyun         		if (!dev->phy->ioctl) return -ENOIOCTLCMD;
1514*4882a593Smuzhiyun 		        return dev->phy->ioctl(dev,cmd,arg);
1515*4882a593Smuzhiyun 	}
1516*4882a593Smuzhiyun }
1517*4882a593Smuzhiyun 
zatm_send(struct atm_vcc * vcc,struct sk_buff * skb)1518*4882a593Smuzhiyun static int zatm_send(struct atm_vcc *vcc,struct sk_buff *skb)
1519*4882a593Smuzhiyun {
1520*4882a593Smuzhiyun 	int error;
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	EVENT(">zatm_send 0x%lx\n",(unsigned long) skb,0);
1523*4882a593Smuzhiyun 	if (!ZATM_VCC(vcc)->tx_chan || !test_bit(ATM_VF_READY,&vcc->flags)) {
1524*4882a593Smuzhiyun 		if (vcc->pop) vcc->pop(vcc,skb);
1525*4882a593Smuzhiyun 		else dev_kfree_skb(skb);
1526*4882a593Smuzhiyun 		return -EINVAL;
1527*4882a593Smuzhiyun 	}
1528*4882a593Smuzhiyun 	if (!skb) {
1529*4882a593Smuzhiyun 		printk(KERN_CRIT "!skb in zatm_send ?\n");
1530*4882a593Smuzhiyun 		if (vcc->pop) vcc->pop(vcc,skb);
1531*4882a593Smuzhiyun 		return -EINVAL;
1532*4882a593Smuzhiyun 	}
1533*4882a593Smuzhiyun 	ATM_SKB(skb)->vcc = vcc;
1534*4882a593Smuzhiyun 	error = do_tx(skb);
1535*4882a593Smuzhiyun 	if (error != RING_BUSY) return error;
1536*4882a593Smuzhiyun 	skb_queue_tail(&ZATM_VCC(vcc)->backlog,skb);
1537*4882a593Smuzhiyun 	return 0;
1538*4882a593Smuzhiyun }
1539*4882a593Smuzhiyun 
1540*4882a593Smuzhiyun 
zatm_phy_put(struct atm_dev * dev,unsigned char value,unsigned long addr)1541*4882a593Smuzhiyun static void zatm_phy_put(struct atm_dev *dev,unsigned char value,
1542*4882a593Smuzhiyun     unsigned long addr)
1543*4882a593Smuzhiyun {
1544*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1545*4882a593Smuzhiyun 
1546*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1547*4882a593Smuzhiyun 	zwait();
1548*4882a593Smuzhiyun 	zout(value,CER);
1549*4882a593Smuzhiyun 	zout(uPD98401_IND_ACC | uPD98401_IA_B0 |
1550*4882a593Smuzhiyun 	    (uPD98401_IA_TGT_PHY << uPD98401_IA_TGT_SHIFT) | addr,CMR);
1551*4882a593Smuzhiyun }
1552*4882a593Smuzhiyun 
1553*4882a593Smuzhiyun 
zatm_phy_get(struct atm_dev * dev,unsigned long addr)1554*4882a593Smuzhiyun static unsigned char zatm_phy_get(struct atm_dev *dev,unsigned long addr)
1555*4882a593Smuzhiyun {
1556*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1557*4882a593Smuzhiyun 
1558*4882a593Smuzhiyun 	zatm_dev = ZATM_DEV(dev);
1559*4882a593Smuzhiyun 	zwait();
1560*4882a593Smuzhiyun 	zout(uPD98401_IND_ACC | uPD98401_IA_B0 | uPD98401_IA_RW |
1561*4882a593Smuzhiyun 	  (uPD98401_IA_TGT_PHY << uPD98401_IA_TGT_SHIFT) | addr,CMR);
1562*4882a593Smuzhiyun 	zwait();
1563*4882a593Smuzhiyun 	return zin(CER) & 0xff;
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun static const struct atmdev_ops ops = {
1568*4882a593Smuzhiyun 	.open		= zatm_open,
1569*4882a593Smuzhiyun 	.close		= zatm_close,
1570*4882a593Smuzhiyun 	.ioctl		= zatm_ioctl,
1571*4882a593Smuzhiyun 	.send		= zatm_send,
1572*4882a593Smuzhiyun 	.phy_put	= zatm_phy_put,
1573*4882a593Smuzhiyun 	.phy_get	= zatm_phy_get,
1574*4882a593Smuzhiyun 	.change_qos	= zatm_change_qos,
1575*4882a593Smuzhiyun };
1576*4882a593Smuzhiyun 
zatm_init_one(struct pci_dev * pci_dev,const struct pci_device_id * ent)1577*4882a593Smuzhiyun static int zatm_init_one(struct pci_dev *pci_dev,
1578*4882a593Smuzhiyun 			 const struct pci_device_id *ent)
1579*4882a593Smuzhiyun {
1580*4882a593Smuzhiyun 	struct atm_dev *dev;
1581*4882a593Smuzhiyun 	struct zatm_dev *zatm_dev;
1582*4882a593Smuzhiyun 	int ret = -ENOMEM;
1583*4882a593Smuzhiyun 
1584*4882a593Smuzhiyun 	zatm_dev = kmalloc(sizeof(*zatm_dev), GFP_KERNEL);
1585*4882a593Smuzhiyun 	if (!zatm_dev) {
1586*4882a593Smuzhiyun 		printk(KERN_EMERG "%s: memory shortage\n", DEV_LABEL);
1587*4882a593Smuzhiyun 		goto out;
1588*4882a593Smuzhiyun 	}
1589*4882a593Smuzhiyun 
1590*4882a593Smuzhiyun 	dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &ops, -1, NULL);
1591*4882a593Smuzhiyun 	if (!dev)
1592*4882a593Smuzhiyun 		goto out_free;
1593*4882a593Smuzhiyun 
1594*4882a593Smuzhiyun 	ret = pci_enable_device(pci_dev);
1595*4882a593Smuzhiyun 	if (ret < 0)
1596*4882a593Smuzhiyun 		goto out_deregister;
1597*4882a593Smuzhiyun 
1598*4882a593Smuzhiyun 	ret = pci_request_regions(pci_dev, DEV_LABEL);
1599*4882a593Smuzhiyun 	if (ret < 0)
1600*4882a593Smuzhiyun 		goto out_disable;
1601*4882a593Smuzhiyun 
1602*4882a593Smuzhiyun 	ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));
1603*4882a593Smuzhiyun 	if (ret < 0)
1604*4882a593Smuzhiyun 		goto out_release;
1605*4882a593Smuzhiyun 
1606*4882a593Smuzhiyun 	zatm_dev->pci_dev = pci_dev;
1607*4882a593Smuzhiyun 	dev->dev_data = zatm_dev;
1608*4882a593Smuzhiyun 	zatm_dev->copper = (int)ent->driver_data;
1609*4882a593Smuzhiyun 	if ((ret = zatm_init(dev)) || (ret = zatm_start(dev)))
1610*4882a593Smuzhiyun 		goto out_release;
1611*4882a593Smuzhiyun 
1612*4882a593Smuzhiyun 	pci_set_drvdata(pci_dev, dev);
1613*4882a593Smuzhiyun 	zatm_dev->more = zatm_boards;
1614*4882a593Smuzhiyun 	zatm_boards = dev;
1615*4882a593Smuzhiyun 	ret = 0;
1616*4882a593Smuzhiyun out:
1617*4882a593Smuzhiyun 	return ret;
1618*4882a593Smuzhiyun 
1619*4882a593Smuzhiyun out_release:
1620*4882a593Smuzhiyun 	pci_release_regions(pci_dev);
1621*4882a593Smuzhiyun out_disable:
1622*4882a593Smuzhiyun 	pci_disable_device(pci_dev);
1623*4882a593Smuzhiyun out_deregister:
1624*4882a593Smuzhiyun 	atm_dev_deregister(dev);
1625*4882a593Smuzhiyun out_free:
1626*4882a593Smuzhiyun 	kfree(zatm_dev);
1627*4882a593Smuzhiyun 	goto out;
1628*4882a593Smuzhiyun }
1629*4882a593Smuzhiyun 
1630*4882a593Smuzhiyun 
1631*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1632*4882a593Smuzhiyun 
1633*4882a593Smuzhiyun static const struct pci_device_id zatm_pci_tbl[] = {
1634*4882a593Smuzhiyun 	{ PCI_VDEVICE(ZEITNET, PCI_DEVICE_ID_ZEITNET_1221), ZATM_COPPER },
1635*4882a593Smuzhiyun 	{ PCI_VDEVICE(ZEITNET, PCI_DEVICE_ID_ZEITNET_1225), 0 },
1636*4882a593Smuzhiyun 	{ 0, }
1637*4882a593Smuzhiyun };
1638*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, zatm_pci_tbl);
1639*4882a593Smuzhiyun 
1640*4882a593Smuzhiyun static struct pci_driver zatm_driver = {
1641*4882a593Smuzhiyun 	.name =		DEV_LABEL,
1642*4882a593Smuzhiyun 	.id_table =	zatm_pci_tbl,
1643*4882a593Smuzhiyun 	.probe =	zatm_init_one,
1644*4882a593Smuzhiyun };
1645*4882a593Smuzhiyun 
zatm_init_module(void)1646*4882a593Smuzhiyun static int __init zatm_init_module(void)
1647*4882a593Smuzhiyun {
1648*4882a593Smuzhiyun 	return pci_register_driver(&zatm_driver);
1649*4882a593Smuzhiyun }
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun module_init(zatm_init_module);
1652*4882a593Smuzhiyun /* module_exit not defined so not unloadable */
1653