1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* drivers/atm/uPD98402.h - NEC uPD98402 (PHY) declarations */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Written 1995 by Werner Almesberger, EPFL LRC */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef DRIVERS_ATM_uPD98402_H 8*4882a593Smuzhiyun #define DRIVERS_ATM_uPD98402_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Registers 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define uPD98402_CMR 0x00 /* Command Register */ 15*4882a593Smuzhiyun #define uPD98402_MDR 0x01 /* Mode Register */ 16*4882a593Smuzhiyun #define uPD98402_PICR 0x02 /* PHY Interrupt Cause Register */ 17*4882a593Smuzhiyun #define uPD98402_PIMR 0x03 /* PHY Interrupt Mask Register */ 18*4882a593Smuzhiyun #define uPD98402_ACR 0x04 /* Alarm Cause Register */ 19*4882a593Smuzhiyun #define uPD98402_ACMR 0x05 /* Alarm Cause Mask Register */ 20*4882a593Smuzhiyun #define uPD98402_PCR 0x06 /* Performance Cause Register */ 21*4882a593Smuzhiyun #define uPD98402_PCMR 0x07 /* Performance Cause Mask Register */ 22*4882a593Smuzhiyun #define uPD98402_IACM 0x08 /* Internal Alarm Cause Mask Register */ 23*4882a593Smuzhiyun #define uPD98402_B1ECT 0x09 /* B1 Error Count Register */ 24*4882a593Smuzhiyun #define uPD98402_B2ECT 0x0a /* B2 Error Count Register */ 25*4882a593Smuzhiyun #define uPD98402_B3ECT 0x0b /* B3 Error Count Regster */ 26*4882a593Smuzhiyun #define uPD98402_PFECB 0x0c /* Path FEBE Count Register */ 27*4882a593Smuzhiyun #define uPD98402_LECCT 0x0d /* Line FEBE Count Register */ 28*4882a593Smuzhiyun #define uPD98402_HECCT 0x0e /* HEC Error Count Register */ 29*4882a593Smuzhiyun #define uPD98402_FJCT 0x0f /* Frequence Justification Count Reg */ 30*4882a593Smuzhiyun #define uPD98402_PCOCR 0x10 /* Perf. Counter Overflow Cause Reg */ 31*4882a593Smuzhiyun #define uPD98402_PCOMR 0x11 /* Perf. Counter Overflow Mask Reg */ 32*4882a593Smuzhiyun #define uPD98402_C11T 0x20 /* C11T Data Register */ 33*4882a593Smuzhiyun #define uPD98402_C12T 0x21 /* C12T Data Register */ 34*4882a593Smuzhiyun #define uPD98402_C13T 0x22 /* C13T Data Register */ 35*4882a593Smuzhiyun #define uPD98402_F1T 0x23 /* F1T Data Register */ 36*4882a593Smuzhiyun #define uPD98402_K2T 0x25 /* K2T Data Register */ 37*4882a593Smuzhiyun #define uPD98402_C2T 0x26 /* C2T Data Register */ 38*4882a593Smuzhiyun #define uPD98402_F2T 0x27 /* F2T Data Register */ 39*4882a593Smuzhiyun #define uPD98402_C11R 0x30 /* C11T Data Register */ 40*4882a593Smuzhiyun #define uPD98402_C12R 0x31 /* C12T Data Register */ 41*4882a593Smuzhiyun #define uPD98402_C13R 0x32 /* C13T Data Register */ 42*4882a593Smuzhiyun #define uPD98402_F1R 0x33 /* F1T Data Register */ 43*4882a593Smuzhiyun #define uPD98402_K2R 0x35 /* K2T Data Register */ 44*4882a593Smuzhiyun #define uPD98402_C2R 0x36 /* C2T Data Register */ 45*4882a593Smuzhiyun #define uPD98402_F2R 0x37 /* F2T Data Register */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* CMR is at 0x00 */ 48*4882a593Smuzhiyun #define uPD98402_CMR_PFRF 0x01 /* Send path FERF */ 49*4882a593Smuzhiyun #define uPD98402_CMR_LFRF 0x02 /* Send line FERF */ 50*4882a593Smuzhiyun #define uPD98402_CMR_PAIS 0x04 /* Send path AIS */ 51*4882a593Smuzhiyun #define uPD98402_CMR_LAIS 0x08 /* Send line AIS */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* MDR is at 0x01 */ 54*4882a593Smuzhiyun #define uPD98402_MDR_ALP 0x01 /* ATM layer loopback */ 55*4882a593Smuzhiyun #define uPD98402_MDR_TPLP 0x02 /* PMD loopback, to host */ 56*4882a593Smuzhiyun #define uPD98402_MDR_RPLP 0x04 /* PMD loopback, to network */ 57*4882a593Smuzhiyun #define uPD98402_MDR_SS0 0x08 /* SS0 */ 58*4882a593Smuzhiyun #define uPD98402_MDR_SS1 0x10 /* SS1 */ 59*4882a593Smuzhiyun #define uPD98402_MDR_SS_MASK 0x18 /* mask */ 60*4882a593Smuzhiyun #define uPD98402_MDR_SS_SHIFT 3 /* shift */ 61*4882a593Smuzhiyun #define uPD98402_MDR_HEC 0x20 /* disable HEC inbound processing */ 62*4882a593Smuzhiyun #define uPD98402_MDR_FSR 0x40 /* disable frame scrambler */ 63*4882a593Smuzhiyun #define uPD98402_MDR_CSR 0x80 /* disable cell scrambler */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* PICR is at 0x02, PIMR is at 0x03 */ 66*4882a593Smuzhiyun #define uPD98402_INT_PFM 0x01 /* performance counter has changed */ 67*4882a593Smuzhiyun #define uPD98402_INT_ALM 0x02 /* line fault */ 68*4882a593Smuzhiyun #define uPD98402_INT_RFO 0x04 /* receive FIFO overflow */ 69*4882a593Smuzhiyun #define uPD98402_INT_PCO 0x08 /* performance counter overflow */ 70*4882a593Smuzhiyun #define uPD98402_INT_OTD 0x20 /* OTD has occurred */ 71*4882a593Smuzhiyun #define uPD98402_INT_LOS 0x40 /* Loss Of Signal */ 72*4882a593Smuzhiyun #define uPD98402_INT_LOF 0x80 /* Loss Of Frame */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* ACR is as 0x04, ACMR is at 0x05 */ 75*4882a593Smuzhiyun #define uPD98402_ALM_PFRF 0x01 /* path FERF */ 76*4882a593Smuzhiyun #define uPD98402_ALM_LFRF 0x02 /* line FERF */ 77*4882a593Smuzhiyun #define uPD98402_ALM_PAIS 0x04 /* path AIS */ 78*4882a593Smuzhiyun #define uPD98402_ALM_LAIS 0x08 /* line AIS */ 79*4882a593Smuzhiyun #define uPD98402_ALM_LOD 0x10 /* loss of delineation */ 80*4882a593Smuzhiyun #define uPD98402_ALM_LOP 0x20 /* loss of pointer */ 81*4882a593Smuzhiyun #define uPD98402_ALM_OOF 0x40 /* out of frame */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* PCR is at 0x06, PCMR is at 0x07 */ 84*4882a593Smuzhiyun #define uPD98402_PFM_PFEB 0x01 /* path FEBE */ 85*4882a593Smuzhiyun #define uPD98402_PFM_LFEB 0x02 /* line FEBE */ 86*4882a593Smuzhiyun #define uPD98402_PFM_B3E 0x04 /* B3 error */ 87*4882a593Smuzhiyun #define uPD98402_PFM_B2E 0x08 /* B2 error */ 88*4882a593Smuzhiyun #define uPD98402_PFM_B1E 0x10 /* B1 error */ 89*4882a593Smuzhiyun #define uPD98402_PFM_FJ 0x20 /* frequency justification */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* IACM is at 0x08 */ 92*4882a593Smuzhiyun #define uPD98402_IACM_PFRF 0x01 /* don't generate path FERF */ 93*4882a593Smuzhiyun #define uPD98402_IACM_LFRF 0x02 /* don't generate line FERF */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* PCOCR is at 0x010, PCOMR is at 0x11 */ 96*4882a593Smuzhiyun #define uPD98402_PCO_B1EC 0x01 /* B1ECT overflow */ 97*4882a593Smuzhiyun #define uPD98402_PCO_B2EC 0x02 /* B2ECT overflow */ 98*4882a593Smuzhiyun #define uPD98402_PCO_B3EC 0x04 /* B3ECT overflow */ 99*4882a593Smuzhiyun #define uPD98402_PCO_PFBC 0x08 /* PFEBC overflow */ 100*4882a593Smuzhiyun #define uPD98402_PCO_LFBC 0x10 /* LFEVC overflow */ 101*4882a593Smuzhiyun #define uPD98402_PCO_HECC 0x20 /* HECCT overflow */ 102*4882a593Smuzhiyun #define uPD98402_PCO_FJC 0x40 /* FJCT overflow */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun int uPD98402_init(struct atm_dev *dev); 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif 108