1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef DRIVER_ATM_ENI_H 8*4882a593Smuzhiyun #define DRIVER_ATM_ENI_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/atm.h> 11*4882a593Smuzhiyun #include <linux/atmdev.h> 12*4882a593Smuzhiyun #include <linux/interrupt.h> 13*4882a593Smuzhiyun #include <linux/sonet.h> 14*4882a593Smuzhiyun #include <linux/skbuff.h> 15*4882a593Smuzhiyun #include <linux/time.h> 16*4882a593Smuzhiyun #include <linux/pci.h> 17*4882a593Smuzhiyun #include <linux/spinlock.h> 18*4882a593Smuzhiyun #include <linux/atomic.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include "midway.h" 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define DEV_LABEL "eni" 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define UBR_BUFFER (128*1024) /* UBR buffer size */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define RX_DMA_BUF 8 /* burst and skip a few things */ 28*4882a593Smuzhiyun #define TX_DMA_BUF 100 /* should be enough for 64 kB */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define DEFAULT_RX_MULT 300 /* max_sdu*3 */ 31*4882a593Smuzhiyun #define DEFAULT_TX_MULT 300 /* max_sdu*3 */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define ENI_ZEROES_SIZE 4 /* need that many DMA-able zero bytes */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct eni_free { 37*4882a593Smuzhiyun void __iomem *start; /* counting in bytes */ 38*4882a593Smuzhiyun int order; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct eni_tx { 42*4882a593Smuzhiyun void __iomem *send; /* base, 0 if unused */ 43*4882a593Smuzhiyun int prescaler; /* shaping prescaler */ 44*4882a593Smuzhiyun int resolution; /* shaping divider */ 45*4882a593Smuzhiyun unsigned long tx_pos; /* current TX write position */ 46*4882a593Smuzhiyun unsigned long words; /* size of TX queue */ 47*4882a593Smuzhiyun int index; /* TX channel number */ 48*4882a593Smuzhiyun int reserved; /* reserved peak cell rate */ 49*4882a593Smuzhiyun int shaping; /* shaped peak cell rate */ 50*4882a593Smuzhiyun struct sk_buff_head backlog; /* queue of waiting TX buffers */ 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct eni_vcc { 54*4882a593Smuzhiyun int (*rx)(struct atm_vcc *vcc); /* RX function, NULL if none */ 55*4882a593Smuzhiyun void __iomem *recv; /* receive buffer */ 56*4882a593Smuzhiyun unsigned long words; /* its size in words */ 57*4882a593Smuzhiyun unsigned long descr; /* next descriptor (RX) */ 58*4882a593Smuzhiyun unsigned long rx_pos; /* current RX descriptor pos */ 59*4882a593Smuzhiyun struct eni_tx *tx; /* TXer, NULL if none */ 60*4882a593Smuzhiyun int rxing; /* number of pending PDUs */ 61*4882a593Smuzhiyun int servicing; /* number of waiting VCs (0 or 1) */ 62*4882a593Smuzhiyun int txing; /* number of pending TX bytes */ 63*4882a593Smuzhiyun ktime_t timestamp; /* for RX timing */ 64*4882a593Smuzhiyun struct atm_vcc *next; /* next pending RX */ 65*4882a593Smuzhiyun struct sk_buff *last; /* last PDU being DMAed (used to carry 66*4882a593Smuzhiyun discard information) */ 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct eni_dev { 70*4882a593Smuzhiyun /*-------------------------------- spinlock */ 71*4882a593Smuzhiyun spinlock_t lock; /* sync with interrupt */ 72*4882a593Smuzhiyun struct tasklet_struct task; /* tasklet for interrupt work */ 73*4882a593Smuzhiyun u32 events; /* pending events */ 74*4882a593Smuzhiyun /*-------------------------------- base pointers into Midway address 75*4882a593Smuzhiyun space */ 76*4882a593Smuzhiyun void __iomem *ioaddr; 77*4882a593Smuzhiyun void __iomem *phy; /* PHY interface chip registers */ 78*4882a593Smuzhiyun void __iomem *reg; /* register base */ 79*4882a593Smuzhiyun void __iomem *ram; /* RAM base */ 80*4882a593Smuzhiyun void __iomem *vci; /* VCI table */ 81*4882a593Smuzhiyun void __iomem *rx_dma; /* RX DMA queue */ 82*4882a593Smuzhiyun void __iomem *tx_dma; /* TX DMA queue */ 83*4882a593Smuzhiyun void __iomem *service; /* service list */ 84*4882a593Smuzhiyun /*-------------------------------- TX part */ 85*4882a593Smuzhiyun struct eni_tx tx[NR_CHAN]; /* TX channels */ 86*4882a593Smuzhiyun struct eni_tx *ubr; /* UBR channel */ 87*4882a593Smuzhiyun struct sk_buff_head tx_queue; /* PDUs currently being TX DMAed*/ 88*4882a593Smuzhiyun wait_queue_head_t tx_wait; /* for close */ 89*4882a593Smuzhiyun int tx_bw; /* remaining bandwidth */ 90*4882a593Smuzhiyun u32 dma[TX_DMA_BUF*2]; /* DMA request scratch area */ 91*4882a593Smuzhiyun struct eni_zero { /* aligned "magic" zeroes */ 92*4882a593Smuzhiyun u32 *addr; 93*4882a593Smuzhiyun dma_addr_t dma; 94*4882a593Smuzhiyun } zero; 95*4882a593Smuzhiyun int tx_mult; /* buffer size multiplier (percent) */ 96*4882a593Smuzhiyun /*-------------------------------- RX part */ 97*4882a593Smuzhiyun u32 serv_read; /* host service read index */ 98*4882a593Smuzhiyun struct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */ 99*4882a593Smuzhiyun struct atm_vcc *slow,*last_slow; 100*4882a593Smuzhiyun struct atm_vcc **rx_map; /* for fast lookups */ 101*4882a593Smuzhiyun struct sk_buff_head rx_queue; /* PDUs currently being RX-DMAed */ 102*4882a593Smuzhiyun wait_queue_head_t rx_wait; /* for close */ 103*4882a593Smuzhiyun int rx_mult; /* buffer size multiplier (percent) */ 104*4882a593Smuzhiyun /*-------------------------------- statistics */ 105*4882a593Smuzhiyun unsigned long lost; /* number of lost cells (RX) */ 106*4882a593Smuzhiyun /*-------------------------------- memory management */ 107*4882a593Smuzhiyun unsigned long base_diff; /* virtual-real base address */ 108*4882a593Smuzhiyun int free_len; /* free list length */ 109*4882a593Smuzhiyun struct eni_free *free_list; /* free list */ 110*4882a593Smuzhiyun int free_list_size; /* maximum size of free list */ 111*4882a593Smuzhiyun /*-------------------------------- ENI links */ 112*4882a593Smuzhiyun struct atm_dev *more; /* other ENI devices */ 113*4882a593Smuzhiyun /*-------------------------------- general information */ 114*4882a593Smuzhiyun int mem; /* RAM on board (in bytes) */ 115*4882a593Smuzhiyun int asic; /* PCI interface type, 0 for FPGA */ 116*4882a593Smuzhiyun unsigned int irq; /* IRQ */ 117*4882a593Smuzhiyun struct pci_dev *pci_dev; /* PCI stuff */ 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define ENI_DEV(d) ((struct eni_dev *) (d)->dev_data) 122*4882a593Smuzhiyun #define ENI_VCC(d) ((struct eni_vcc *) (d)->dev_data) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun struct eni_skb_prv { 126*4882a593Smuzhiyun struct atm_skb_data _; /* reserved */ 127*4882a593Smuzhiyun unsigned long pos; /* position of next descriptor */ 128*4882a593Smuzhiyun int size; /* PDU size in reassembly buffer */ 129*4882a593Smuzhiyun dma_addr_t paddr; /* DMA handle */ 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define ENI_PRV_SIZE(skb) (((struct eni_skb_prv *) (skb)->cb)->size) 133*4882a593Smuzhiyun #define ENI_PRV_POS(skb) (((struct eni_skb_prv *) (skb)->cb)->pos) 134*4882a593Smuzhiyun #define ENI_PRV_PADDR(skb) (((struct eni_skb_prv *) (skb)->cb)->paddr) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif 137