1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun Madge Ambassador ATM Adapter driver.
4*4882a593Smuzhiyun Copyright (C) 1995-1999 Madge Networks Ltd.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /* * dedicated to the memory of Graham Gordon 1971-1998 * */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/ioport.h>
16*4882a593Smuzhiyun #include <linux/atmdev.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/poison.h>
20*4882a593Smuzhiyun #include <linux/bitrev.h>
21*4882a593Smuzhiyun #include <linux/mutex.h>
22*4882a593Smuzhiyun #include <linux/firmware.h>
23*4882a593Smuzhiyun #include <linux/ihex.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/atomic.h>
27*4882a593Smuzhiyun #include <asm/io.h>
28*4882a593Smuzhiyun #include <asm/byteorder.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "ambassador.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
33*4882a593Smuzhiyun #define description_string "Madge ATM Ambassador driver"
34*4882a593Smuzhiyun #define version_string "1.2.4"
35*4882a593Smuzhiyun
show_version(void)36*4882a593Smuzhiyun static inline void __init show_version (void) {
37*4882a593Smuzhiyun printk ("%s version %s\n", description_string, version_string);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun Theory of Operation
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun I Hardware, detection, initialisation and shutdown.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun 1. Supported Hardware
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun This driver is for the PCI ATMizer-based Ambassador card (except
49*4882a593Smuzhiyun very early versions). It is not suitable for the similar EISA "TR7"
50*4882a593Smuzhiyun card. Commercially, both cards are known as Collage Server ATM
51*4882a593Smuzhiyun adapters.
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun The loader supports image transfer to the card, image start and few
54*4882a593Smuzhiyun other miscellaneous commands.
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun Only AAL5 is supported with vpi = 0 and vci in the range 0 to 1023.
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun The cards are big-endian.
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun 2. Detection
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun Standard PCI stuff, the early cards are detected and rejected.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun 3. Initialisation
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun The cards are reset and the self-test results are checked. The
67*4882a593Smuzhiyun microcode image is then transferred and started. This waits for a
68*4882a593Smuzhiyun pointer to a descriptor containing details of the host-based queues
69*4882a593Smuzhiyun and buffers and various parameters etc. Once they are processed
70*4882a593Smuzhiyun normal operations may begin. The BIA is read using a microcode
71*4882a593Smuzhiyun command.
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun 4. Shutdown
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun This may be accomplished either by a card reset or via the microcode
76*4882a593Smuzhiyun shutdown command. Further investigation required.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun 5. Persistent state
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun The card reset does not affect PCI configuration (good) or the
81*4882a593Smuzhiyun contents of several other "shared run-time registers" (bad) which
82*4882a593Smuzhiyun include doorbell and interrupt control as well as EEPROM and PCI
83*4882a593Smuzhiyun control. The driver must be careful when modifying these registers
84*4882a593Smuzhiyun not to touch bits it does not use and to undo any changes at exit.
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun II Driver software
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun 0. Generalities
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun The adapter is quite intelligent (fast) and has a simple interface
91*4882a593Smuzhiyun (few features). VPI is always zero, 1024 VCIs are supported. There
92*4882a593Smuzhiyun is limited cell rate support. UBR channels can be capped and ABR
93*4882a593Smuzhiyun (explicit rate, but not EFCI) is supported. There is no CBR or VBR
94*4882a593Smuzhiyun support.
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun 1. Driver <-> Adapter Communication
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun Apart from the basic loader commands, the driver communicates
99*4882a593Smuzhiyun through three entities: the command queue (CQ), the transmit queue
100*4882a593Smuzhiyun pair (TXQ) and the receive queue pairs (RXQ). These three entities
101*4882a593Smuzhiyun are set up by the host and passed to the microcode just after it has
102*4882a593Smuzhiyun been started.
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun All queues are host-based circular queues. They are contiguous and
105*4882a593Smuzhiyun (due to hardware limitations) have some restrictions as to their
106*4882a593Smuzhiyun locations in (bus) memory. They are of the "full means the same as
107*4882a593Smuzhiyun empty so don't do that" variety since the adapter uses pointers
108*4882a593Smuzhiyun internally.
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun The queue pairs work as follows: one queue is for supply to the
111*4882a593Smuzhiyun adapter, items in it are pending and are owned by the adapter; the
112*4882a593Smuzhiyun other is the queue for return from the adapter, items in it have
113*4882a593Smuzhiyun been dealt with by the adapter. The host adds items to the supply
114*4882a593Smuzhiyun (TX descriptors and free RX buffer descriptors) and removes items
115*4882a593Smuzhiyun from the return (TX and RX completions). The adapter deals with out
116*4882a593Smuzhiyun of order completions.
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun Interrupts (card to host) and the doorbell (host to card) are used
119*4882a593Smuzhiyun for signalling.
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun 1. CQ
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun This is to communicate "open VC", "close VC", "get stats" etc. to
124*4882a593Smuzhiyun the adapter. At most one command is retired every millisecond by the
125*4882a593Smuzhiyun card. There is no out of order completion or notification. The
126*4882a593Smuzhiyun driver needs to check the return code of the command, waiting as
127*4882a593Smuzhiyun appropriate.
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun 2. TXQ
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun TX supply items are of variable length (scatter gather support) and
132*4882a593Smuzhiyun so the queue items are (more or less) pointers to the real thing.
133*4882a593Smuzhiyun Each TX supply item contains a unique, host-supplied handle (the skb
134*4882a593Smuzhiyun bus address seems most sensible as this works for Alphas as well,
135*4882a593Smuzhiyun there is no need to do any endian conversions on the handles).
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun TX return items consist of just the handles above.
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun 3. RXQ (up to 4 of these with different lengths and buffer sizes)
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun RX supply items consist of a unique, host-supplied handle (the skb
142*4882a593Smuzhiyun bus address again) and a pointer to the buffer data area.
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun RX return items consist of the handle above, the VC, length and a
145*4882a593Smuzhiyun status word. This just screams "oh so easy" doesn't it?
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun Note on RX pool sizes:
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun Each pool should have enough buffers to handle a back-to-back stream
150*4882a593Smuzhiyun of minimum sized frames on a single VC. For example:
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun frame spacing = 3us (about right)
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun delay = IRQ lat + RX handling + RX buffer replenish = 20 (us) (a guess)
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun min number of buffers for one VC = 1 + delay/spacing (buffers)
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun delay/spacing = latency = (20+2)/3 = 7 (buffers) (rounding up)
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun The 20us delay assumes that there is no need to sleep; if we need to
161*4882a593Smuzhiyun sleep to get buffers we are going to drop frames anyway.
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun In fact, each pool should have enough buffers to support the
164*4882a593Smuzhiyun simultaneous reassembly of a separate frame on each VC and cope with
165*4882a593Smuzhiyun the case in which frames complete in round robin cell fashion on
166*4882a593Smuzhiyun each VC.
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun Only one frame can complete at each cell arrival, so if "n" VCs are
169*4882a593Smuzhiyun open, the worst case is to have them all complete frames together
170*4882a593Smuzhiyun followed by all starting new frames together.
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun desired number of buffers = n + delay/spacing
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun These are the extreme requirements, however, they are "n+k" for some
175*4882a593Smuzhiyun "k" so we have only the constant to choose. This is the argument
176*4882a593Smuzhiyun rx_lats which current defaults to 7.
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun Actually, "n ? n+k : 0" is better and this is what is implemented,
179*4882a593Smuzhiyun subject to the limit given by the pool size.
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun 4. Driver locking
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun Simple spinlocks are used around the TX and RX queue mechanisms.
184*4882a593Smuzhiyun Anyone with a faster, working method is welcome to implement it.
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun The adapter command queue is protected with a spinlock. We always
187*4882a593Smuzhiyun wait for commands to complete.
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun A more complex form of locking is used around parts of the VC open
190*4882a593Smuzhiyun and close functions. There are three reasons for a lock: 1. we need
191*4882a593Smuzhiyun to do atomic rate reservation and release (not used yet), 2. Opening
192*4882a593Smuzhiyun sometimes involves two adapter commands which must not be separated
193*4882a593Smuzhiyun by another command on the same VC, 3. the changes to RX pool size
194*4882a593Smuzhiyun must be atomic. The lock needs to work over context switches, so we
195*4882a593Smuzhiyun use a semaphore.
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun III Hardware Features and Microcode Bugs
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun 1. Byte Ordering
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun *%^"$&%^$*&^"$(%^$#&^%$(&#%$*(&^#%!"!"!*!
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun 2. Memory access
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun All structures that are not accessed using DMA must be 4-byte
206*4882a593Smuzhiyun aligned (not a problem) and must not cross 4MB boundaries.
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun There is a DMA memory hole at E0000000-E00000FF (groan).
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun TX fragments (DMA read) must not cross 4MB boundaries (would be 16MB
211*4882a593Smuzhiyun but for a hardware bug).
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun RX buffers (DMA write) must not cross 16MB boundaries and must
214*4882a593Smuzhiyun include spare trailing bytes up to the next 4-byte boundary; they
215*4882a593Smuzhiyun will be written with rubbish.
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun The PLX likes to prefetch; if reading up to 4 u32 past the end of
218*4882a593Smuzhiyun each TX fragment is not a problem, then TX can be made to go a
219*4882a593Smuzhiyun little faster by passing a flag at init that disables a prefetch
220*4882a593Smuzhiyun workaround. We do not pass this flag. (new microcode only)
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun Now we:
223*4882a593Smuzhiyun . Note that alloc_skb rounds up size to a 16byte boundary.
224*4882a593Smuzhiyun . Ensure all areas do not traverse 4MB boundaries.
225*4882a593Smuzhiyun . Ensure all areas do not start at a E00000xx bus address.
226*4882a593Smuzhiyun (I cannot be certain, but this may always hold with Linux)
227*4882a593Smuzhiyun . Make all failures cause a loud message.
228*4882a593Smuzhiyun . Discard non-conforming SKBs (causes TX failure or RX fill delay).
229*4882a593Smuzhiyun . Discard non-conforming TX fragment descriptors (the TX fails).
230*4882a593Smuzhiyun In the future we could:
231*4882a593Smuzhiyun . Allow RX areas that traverse 4MB (but not 16MB) boundaries.
232*4882a593Smuzhiyun . Segment TX areas into some/more fragments, when necessary.
233*4882a593Smuzhiyun . Relax checks for non-DMA items (ignore hole).
234*4882a593Smuzhiyun . Give scatter-gather (iovec) requirements using ???. (?)
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun 3. VC close is broken (only for new microcode)
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun The VC close adapter microcode command fails to do anything if any
239*4882a593Smuzhiyun frames have been received on the VC but none have been transmitted.
240*4882a593Smuzhiyun Frames continue to be reassembled and passed (with IRQ) to the
241*4882a593Smuzhiyun driver.
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun IV To Do List
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun . Fix bugs!
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun . Timer code may be broken.
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun . Deal with buggy VC close (somehow) in microcode 12.
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun . Handle interrupted and/or non-blocking writes - is this a job for
252*4882a593Smuzhiyun the protocol layer?
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun . Add code to break up TX fragments when they span 4MB boundaries.
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun . Add SUNI phy layer (need to know where SUNI lives on card).
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun . Implement a tx_alloc fn to (a) satisfy TX alignment etc. and (b)
259*4882a593Smuzhiyun leave extra headroom space for Ambassador TX descriptors.
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun . Understand these elements of struct atm_vcc: recvq (proto?),
262*4882a593Smuzhiyun sleep, callback, listenq, backlog_quota, reply and user_back.
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun . Adjust TX/RX skb allocation to favour IP with LANE/CLIP (configurable).
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun . Impose a TX-pending limit (2?) on each VC, help avoid TX q overflow.
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun . Decide whether RX buffer recycling is or can be made completely safe;
269*4882a593Smuzhiyun turn it back on. It looks like Werner is going to axe this.
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun . Implement QoS changes on open VCs (involves extracting parts of VC open
272*4882a593Smuzhiyun and close into separate functions and using them to make changes).
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun . Hack on command queue so that someone can issue multiple commands and wait
275*4882a593Smuzhiyun on the last one (OR only "no-op" or "wait" commands are waited for).
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun . Eliminate need for while-schedule around do_command.
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun */
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun static void do_housekeeping (struct timer_list *t);
282*4882a593Smuzhiyun /********** globals **********/
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun static unsigned short debug = 0;
285*4882a593Smuzhiyun static unsigned int cmds = 8;
286*4882a593Smuzhiyun static unsigned int txs = 32;
287*4882a593Smuzhiyun static unsigned int rxs[NUM_RX_POOLS] = { 64, 64, 64, 64 };
288*4882a593Smuzhiyun static unsigned int rxs_bs[NUM_RX_POOLS] = { 4080, 12240, 36720, 65535 };
289*4882a593Smuzhiyun static unsigned int rx_lats = 7;
290*4882a593Smuzhiyun static unsigned char pci_lat = 0;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static const unsigned long onegigmask = -1 << 30;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /********** access to adapter **********/
295*4882a593Smuzhiyun
wr_plain(const amb_dev * dev,size_t addr,u32 data)296*4882a593Smuzhiyun static inline void wr_plain (const amb_dev * dev, size_t addr, u32 data) {
297*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_REGS, "wr: %08zx <- %08x", addr, data);
298*4882a593Smuzhiyun #ifdef AMB_MMIO
299*4882a593Smuzhiyun dev->membase[addr / sizeof(u32)] = data;
300*4882a593Smuzhiyun #else
301*4882a593Smuzhiyun outl (data, dev->iobase + addr);
302*4882a593Smuzhiyun #endif
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
rd_plain(const amb_dev * dev,size_t addr)305*4882a593Smuzhiyun static inline u32 rd_plain (const amb_dev * dev, size_t addr) {
306*4882a593Smuzhiyun #ifdef AMB_MMIO
307*4882a593Smuzhiyun u32 data = dev->membase[addr / sizeof(u32)];
308*4882a593Smuzhiyun #else
309*4882a593Smuzhiyun u32 data = inl (dev->iobase + addr);
310*4882a593Smuzhiyun #endif
311*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_REGS, "rd: %08zx -> %08x", addr, data);
312*4882a593Smuzhiyun return data;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
wr_mem(const amb_dev * dev,size_t addr,u32 data)315*4882a593Smuzhiyun static inline void wr_mem (const amb_dev * dev, size_t addr, u32 data) {
316*4882a593Smuzhiyun __be32 be = cpu_to_be32 (data);
317*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_REGS, "wr: %08zx <- %08x b[%08x]", addr, data, be);
318*4882a593Smuzhiyun #ifdef AMB_MMIO
319*4882a593Smuzhiyun dev->membase[addr / sizeof(u32)] = be;
320*4882a593Smuzhiyun #else
321*4882a593Smuzhiyun outl (be, dev->iobase + addr);
322*4882a593Smuzhiyun #endif
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
rd_mem(const amb_dev * dev,size_t addr)325*4882a593Smuzhiyun static inline u32 rd_mem (const amb_dev * dev, size_t addr) {
326*4882a593Smuzhiyun #ifdef AMB_MMIO
327*4882a593Smuzhiyun __be32 be = dev->membase[addr / sizeof(u32)];
328*4882a593Smuzhiyun #else
329*4882a593Smuzhiyun __be32 be = inl (dev->iobase + addr);
330*4882a593Smuzhiyun #endif
331*4882a593Smuzhiyun u32 data = be32_to_cpu (be);
332*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_REGS, "rd: %08zx -> %08x b[%08x]", addr, data, be);
333*4882a593Smuzhiyun return data;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /********** dump routines **********/
337*4882a593Smuzhiyun
dump_registers(const amb_dev * dev)338*4882a593Smuzhiyun static inline void dump_registers (const amb_dev * dev) {
339*4882a593Smuzhiyun #ifdef DEBUG_AMBASSADOR
340*4882a593Smuzhiyun if (debug & DBG_REGS) {
341*4882a593Smuzhiyun size_t i;
342*4882a593Smuzhiyun PRINTD (DBG_REGS, "reading PLX control: ");
343*4882a593Smuzhiyun for (i = 0x00; i < 0x30; i += sizeof(u32))
344*4882a593Smuzhiyun rd_mem (dev, i);
345*4882a593Smuzhiyun PRINTD (DBG_REGS, "reading mailboxes: ");
346*4882a593Smuzhiyun for (i = 0x40; i < 0x60; i += sizeof(u32))
347*4882a593Smuzhiyun rd_mem (dev, i);
348*4882a593Smuzhiyun PRINTD (DBG_REGS, "reading doorb irqev irqen reset:");
349*4882a593Smuzhiyun for (i = 0x60; i < 0x70; i += sizeof(u32))
350*4882a593Smuzhiyun rd_mem (dev, i);
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun #else
353*4882a593Smuzhiyun (void) dev;
354*4882a593Smuzhiyun #endif
355*4882a593Smuzhiyun return;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
dump_loader_block(volatile loader_block * lb)358*4882a593Smuzhiyun static inline void dump_loader_block (volatile loader_block * lb) {
359*4882a593Smuzhiyun #ifdef DEBUG_AMBASSADOR
360*4882a593Smuzhiyun unsigned int i;
361*4882a593Smuzhiyun PRINTDB (DBG_LOAD, "lb @ %p; res: %d, cmd: %d, pay:",
362*4882a593Smuzhiyun lb, be32_to_cpu (lb->result), be32_to_cpu (lb->command));
363*4882a593Smuzhiyun for (i = 0; i < MAX_COMMAND_DATA; ++i)
364*4882a593Smuzhiyun PRINTDM (DBG_LOAD, " %08x", be32_to_cpu (lb->payload.data[i]));
365*4882a593Smuzhiyun PRINTDE (DBG_LOAD, ", vld: %08x", be32_to_cpu (lb->valid));
366*4882a593Smuzhiyun #else
367*4882a593Smuzhiyun (void) lb;
368*4882a593Smuzhiyun #endif
369*4882a593Smuzhiyun return;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
dump_command(command * cmd)372*4882a593Smuzhiyun static inline void dump_command (command * cmd) {
373*4882a593Smuzhiyun #ifdef DEBUG_AMBASSADOR
374*4882a593Smuzhiyun unsigned int i;
375*4882a593Smuzhiyun PRINTDB (DBG_CMD, "cmd @ %p, req: %08x, pars:",
376*4882a593Smuzhiyun cmd, /*be32_to_cpu*/ (cmd->request));
377*4882a593Smuzhiyun for (i = 0; i < 3; ++i)
378*4882a593Smuzhiyun PRINTDM (DBG_CMD, " %08x", /*be32_to_cpu*/ (cmd->args.par[i]));
379*4882a593Smuzhiyun PRINTDE (DBG_CMD, "");
380*4882a593Smuzhiyun #else
381*4882a593Smuzhiyun (void) cmd;
382*4882a593Smuzhiyun #endif
383*4882a593Smuzhiyun return;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
dump_skb(char * prefix,unsigned int vc,struct sk_buff * skb)386*4882a593Smuzhiyun static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
387*4882a593Smuzhiyun #ifdef DEBUG_AMBASSADOR
388*4882a593Smuzhiyun unsigned int i;
389*4882a593Smuzhiyun unsigned char * data = skb->data;
390*4882a593Smuzhiyun PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
391*4882a593Smuzhiyun for (i=0; i<skb->len && i < 256;i++)
392*4882a593Smuzhiyun PRINTDM (DBG_DATA, "%02x ", data[i]);
393*4882a593Smuzhiyun PRINTDE (DBG_DATA,"");
394*4882a593Smuzhiyun #else
395*4882a593Smuzhiyun (void) prefix;
396*4882a593Smuzhiyun (void) vc;
397*4882a593Smuzhiyun (void) skb;
398*4882a593Smuzhiyun #endif
399*4882a593Smuzhiyun return;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /********** check memory areas for use by Ambassador **********/
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun /* see limitations under Hardware Features */
405*4882a593Smuzhiyun
check_area(void * start,size_t length)406*4882a593Smuzhiyun static int check_area (void * start, size_t length) {
407*4882a593Smuzhiyun // assumes length > 0
408*4882a593Smuzhiyun const u32 fourmegmask = -1 << 22;
409*4882a593Smuzhiyun const u32 twofivesixmask = -1 << 8;
410*4882a593Smuzhiyun const u32 starthole = 0xE0000000;
411*4882a593Smuzhiyun u32 startaddress = virt_to_bus (start);
412*4882a593Smuzhiyun u32 lastaddress = startaddress+length-1;
413*4882a593Smuzhiyun if ((startaddress ^ lastaddress) & fourmegmask ||
414*4882a593Smuzhiyun (startaddress & twofivesixmask) == starthole) {
415*4882a593Smuzhiyun PRINTK (KERN_ERR, "check_area failure: [%x,%x] - mail maintainer!",
416*4882a593Smuzhiyun startaddress, lastaddress);
417*4882a593Smuzhiyun return -1;
418*4882a593Smuzhiyun } else {
419*4882a593Smuzhiyun return 0;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /********** free an skb (as per ATM device driver documentation) **********/
424*4882a593Smuzhiyun
amb_kfree_skb(struct sk_buff * skb)425*4882a593Smuzhiyun static void amb_kfree_skb (struct sk_buff * skb) {
426*4882a593Smuzhiyun if (ATM_SKB(skb)->vcc->pop) {
427*4882a593Smuzhiyun ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
428*4882a593Smuzhiyun } else {
429*4882a593Smuzhiyun dev_kfree_skb_any (skb);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun /********** TX completion **********/
434*4882a593Smuzhiyun
tx_complete(amb_dev * dev,tx_out * tx)435*4882a593Smuzhiyun static void tx_complete (amb_dev * dev, tx_out * tx) {
436*4882a593Smuzhiyun tx_simple * tx_descr = bus_to_virt (tx->handle);
437*4882a593Smuzhiyun struct sk_buff * skb = tx_descr->skb;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_TX, "tx_complete %p %p", dev, tx);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun // VC layer stats
442*4882a593Smuzhiyun atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun // free the descriptor
445*4882a593Smuzhiyun kfree (tx_descr);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun // free the skb
448*4882a593Smuzhiyun amb_kfree_skb (skb);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun dev->stats.tx_ok++;
451*4882a593Smuzhiyun return;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /********** RX completion **********/
455*4882a593Smuzhiyun
rx_complete(amb_dev * dev,rx_out * rx)456*4882a593Smuzhiyun static void rx_complete (amb_dev * dev, rx_out * rx) {
457*4882a593Smuzhiyun struct sk_buff * skb = bus_to_virt (rx->handle);
458*4882a593Smuzhiyun u16 vc = be16_to_cpu (rx->vc);
459*4882a593Smuzhiyun // unused: u16 lec_id = be16_to_cpu (rx->lec_id);
460*4882a593Smuzhiyun u16 status = be16_to_cpu (rx->status);
461*4882a593Smuzhiyun u16 rx_len = be16_to_cpu (rx->length);
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_RX, "rx_complete %p %p (len=%hu)", dev, rx, rx_len);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun // XXX move this in and add to VC stats ???
466*4882a593Smuzhiyun if (!status) {
467*4882a593Smuzhiyun struct atm_vcc * atm_vcc = dev->rxer[vc];
468*4882a593Smuzhiyun dev->stats.rx.ok++;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun if (atm_vcc) {
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (atm_charge (atm_vcc, skb->truesize)) {
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun // prepare socket buffer
477*4882a593Smuzhiyun ATM_SKB(skb)->vcc = atm_vcc;
478*4882a593Smuzhiyun skb_put (skb, rx_len);
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun dump_skb ("<<<", vc, skb);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun // VC layer stats
483*4882a593Smuzhiyun atomic_inc(&atm_vcc->stats->rx);
484*4882a593Smuzhiyun __net_timestamp(skb);
485*4882a593Smuzhiyun // end of our responsibility
486*4882a593Smuzhiyun atm_vcc->push (atm_vcc, skb);
487*4882a593Smuzhiyun return;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun } else {
490*4882a593Smuzhiyun // someone fix this (message), please!
491*4882a593Smuzhiyun PRINTD (DBG_INFO|DBG_RX, "dropped thanks to atm_charge (vc %hu, truesize %u)", vc, skb->truesize);
492*4882a593Smuzhiyun // drop stats incremented in atm_charge
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun } else {
496*4882a593Smuzhiyun PRINTK (KERN_INFO, "dropped over-size frame");
497*4882a593Smuzhiyun // should we count this?
498*4882a593Smuzhiyun atomic_inc(&atm_vcc->stats->rx_drop);
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun } else {
502*4882a593Smuzhiyun PRINTD (DBG_WARN|DBG_RX, "got frame but RX closed for channel %hu", vc);
503*4882a593Smuzhiyun // this is an adapter bug, only in new version of microcode
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun } else {
507*4882a593Smuzhiyun dev->stats.rx.error++;
508*4882a593Smuzhiyun if (status & CRC_ERR)
509*4882a593Smuzhiyun dev->stats.rx.badcrc++;
510*4882a593Smuzhiyun if (status & LEN_ERR)
511*4882a593Smuzhiyun dev->stats.rx.toolong++;
512*4882a593Smuzhiyun if (status & ABORT_ERR)
513*4882a593Smuzhiyun dev->stats.rx.aborted++;
514*4882a593Smuzhiyun if (status & UNUSED_ERR)
515*4882a593Smuzhiyun dev->stats.rx.unused++;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun dev_kfree_skb_any (skb);
519*4882a593Smuzhiyun return;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun /*
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun Note on queue handling.
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun Here "give" and "take" refer to queue entries and a queue (pair)
527*4882a593Smuzhiyun rather than frames to or from the host or adapter. Empty frame
528*4882a593Smuzhiyun buffers are given to the RX queue pair and returned unused or
529*4882a593Smuzhiyun containing RX frames. TX frames (well, pointers to TX fragment
530*4882a593Smuzhiyun lists) are given to the TX queue pair, completions are returned.
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun */
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /********** command queue **********/
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun // I really don't like this, but it's the best I can do at the moment
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun // also, the callers are responsible for byte order as the microcode
539*4882a593Smuzhiyun // sometimes does 16-bit accesses (yuk yuk yuk)
540*4882a593Smuzhiyun
command_do(amb_dev * dev,command * cmd)541*4882a593Smuzhiyun static int command_do (amb_dev * dev, command * cmd) {
542*4882a593Smuzhiyun amb_cq * cq = &dev->cq;
543*4882a593Smuzhiyun volatile amb_cq_ptrs * ptrs = &cq->ptrs;
544*4882a593Smuzhiyun command * my_slot;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_CMD, "command_do %p", dev);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun if (test_bit (dead, &dev->flags))
549*4882a593Smuzhiyun return 0;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun spin_lock (&cq->lock);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun // if not full...
554*4882a593Smuzhiyun if (cq->pending < cq->maximum) {
555*4882a593Smuzhiyun // remember my slot for later
556*4882a593Smuzhiyun my_slot = ptrs->in;
557*4882a593Smuzhiyun PRINTD (DBG_CMD, "command in slot %p", my_slot);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun dump_command (cmd);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun // copy command in
562*4882a593Smuzhiyun *ptrs->in = *cmd;
563*4882a593Smuzhiyun cq->pending++;
564*4882a593Smuzhiyun ptrs->in = NEXTQ (ptrs->in, ptrs->start, ptrs->limit);
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun // mail the command
567*4882a593Smuzhiyun wr_mem (dev, offsetof(amb_mem, mb.adapter.cmd_address), virt_to_bus (ptrs->in));
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun if (cq->pending > cq->high)
570*4882a593Smuzhiyun cq->high = cq->pending;
571*4882a593Smuzhiyun spin_unlock (&cq->lock);
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun // these comments were in a while-loop before, msleep removes the loop
574*4882a593Smuzhiyun // go to sleep
575*4882a593Smuzhiyun // PRINTD (DBG_CMD, "wait: sleeping %lu for command", timeout);
576*4882a593Smuzhiyun msleep(cq->pending);
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun // wait for my slot to be reached (all waiters are here or above, until...)
579*4882a593Smuzhiyun while (ptrs->out != my_slot) {
580*4882a593Smuzhiyun PRINTD (DBG_CMD, "wait: command slot (now at %p)", ptrs->out);
581*4882a593Smuzhiyun set_current_state(TASK_UNINTERRUPTIBLE);
582*4882a593Smuzhiyun schedule();
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun // wait on my slot (... one gets to its slot, and... )
586*4882a593Smuzhiyun while (ptrs->out->request != cpu_to_be32 (SRB_COMPLETE)) {
587*4882a593Smuzhiyun PRINTD (DBG_CMD, "wait: command slot completion");
588*4882a593Smuzhiyun set_current_state(TASK_UNINTERRUPTIBLE);
589*4882a593Smuzhiyun schedule();
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun PRINTD (DBG_CMD, "command complete");
593*4882a593Smuzhiyun // update queue (... moves the queue along to the next slot)
594*4882a593Smuzhiyun spin_lock (&cq->lock);
595*4882a593Smuzhiyun cq->pending--;
596*4882a593Smuzhiyun // copy command out
597*4882a593Smuzhiyun *cmd = *ptrs->out;
598*4882a593Smuzhiyun ptrs->out = NEXTQ (ptrs->out, ptrs->start, ptrs->limit);
599*4882a593Smuzhiyun spin_unlock (&cq->lock);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun return 0;
602*4882a593Smuzhiyun } else {
603*4882a593Smuzhiyun cq->filled++;
604*4882a593Smuzhiyun spin_unlock (&cq->lock);
605*4882a593Smuzhiyun return -EAGAIN;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun /********** TX queue pair **********/
611*4882a593Smuzhiyun
tx_give(amb_dev * dev,tx_in * tx)612*4882a593Smuzhiyun static int tx_give (amb_dev * dev, tx_in * tx) {
613*4882a593Smuzhiyun amb_txq * txq = &dev->txq;
614*4882a593Smuzhiyun unsigned long flags;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_TX, "tx_give %p", dev);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun if (test_bit (dead, &dev->flags))
619*4882a593Smuzhiyun return 0;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun spin_lock_irqsave (&txq->lock, flags);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun if (txq->pending < txq->maximum) {
624*4882a593Smuzhiyun PRINTD (DBG_TX, "TX in slot %p", txq->in.ptr);
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun *txq->in.ptr = *tx;
627*4882a593Smuzhiyun txq->pending++;
628*4882a593Smuzhiyun txq->in.ptr = NEXTQ (txq->in.ptr, txq->in.start, txq->in.limit);
629*4882a593Smuzhiyun // hand over the TX and ring the bell
630*4882a593Smuzhiyun wr_mem (dev, offsetof(amb_mem, mb.adapter.tx_address), virt_to_bus (txq->in.ptr));
631*4882a593Smuzhiyun wr_mem (dev, offsetof(amb_mem, doorbell), TX_FRAME);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun if (txq->pending > txq->high)
634*4882a593Smuzhiyun txq->high = txq->pending;
635*4882a593Smuzhiyun spin_unlock_irqrestore (&txq->lock, flags);
636*4882a593Smuzhiyun return 0;
637*4882a593Smuzhiyun } else {
638*4882a593Smuzhiyun txq->filled++;
639*4882a593Smuzhiyun spin_unlock_irqrestore (&txq->lock, flags);
640*4882a593Smuzhiyun return -EAGAIN;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
tx_take(amb_dev * dev)644*4882a593Smuzhiyun static int tx_take (amb_dev * dev) {
645*4882a593Smuzhiyun amb_txq * txq = &dev->txq;
646*4882a593Smuzhiyun unsigned long flags;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_TX, "tx_take %p", dev);
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun spin_lock_irqsave (&txq->lock, flags);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun if (txq->pending && txq->out.ptr->handle) {
653*4882a593Smuzhiyun // deal with TX completion
654*4882a593Smuzhiyun tx_complete (dev, txq->out.ptr);
655*4882a593Smuzhiyun // mark unused again
656*4882a593Smuzhiyun txq->out.ptr->handle = 0;
657*4882a593Smuzhiyun // remove item
658*4882a593Smuzhiyun txq->pending--;
659*4882a593Smuzhiyun txq->out.ptr = NEXTQ (txq->out.ptr, txq->out.start, txq->out.limit);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun spin_unlock_irqrestore (&txq->lock, flags);
662*4882a593Smuzhiyun return 0;
663*4882a593Smuzhiyun } else {
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun spin_unlock_irqrestore (&txq->lock, flags);
666*4882a593Smuzhiyun return -1;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun /********** RX queue pairs **********/
671*4882a593Smuzhiyun
rx_give(amb_dev * dev,rx_in * rx,unsigned char pool)672*4882a593Smuzhiyun static int rx_give (amb_dev * dev, rx_in * rx, unsigned char pool) {
673*4882a593Smuzhiyun amb_rxq * rxq = &dev->rxq[pool];
674*4882a593Smuzhiyun unsigned long flags;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_RX, "rx_give %p[%hu]", dev, pool);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun spin_lock_irqsave (&rxq->lock, flags);
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun if (rxq->pending < rxq->maximum) {
681*4882a593Smuzhiyun PRINTD (DBG_RX, "RX in slot %p", rxq->in.ptr);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun *rxq->in.ptr = *rx;
684*4882a593Smuzhiyun rxq->pending++;
685*4882a593Smuzhiyun rxq->in.ptr = NEXTQ (rxq->in.ptr, rxq->in.start, rxq->in.limit);
686*4882a593Smuzhiyun // hand over the RX buffer
687*4882a593Smuzhiyun wr_mem (dev, offsetof(amb_mem, mb.adapter.rx_address[pool]), virt_to_bus (rxq->in.ptr));
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun spin_unlock_irqrestore (&rxq->lock, flags);
690*4882a593Smuzhiyun return 0;
691*4882a593Smuzhiyun } else {
692*4882a593Smuzhiyun spin_unlock_irqrestore (&rxq->lock, flags);
693*4882a593Smuzhiyun return -1;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun
rx_take(amb_dev * dev,unsigned char pool)697*4882a593Smuzhiyun static int rx_take (amb_dev * dev, unsigned char pool) {
698*4882a593Smuzhiyun amb_rxq * rxq = &dev->rxq[pool];
699*4882a593Smuzhiyun unsigned long flags;
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_RX, "rx_take %p[%hu]", dev, pool);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun spin_lock_irqsave (&rxq->lock, flags);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun if (rxq->pending && (rxq->out.ptr->status || rxq->out.ptr->length)) {
706*4882a593Smuzhiyun // deal with RX completion
707*4882a593Smuzhiyun rx_complete (dev, rxq->out.ptr);
708*4882a593Smuzhiyun // mark unused again
709*4882a593Smuzhiyun rxq->out.ptr->status = 0;
710*4882a593Smuzhiyun rxq->out.ptr->length = 0;
711*4882a593Smuzhiyun // remove item
712*4882a593Smuzhiyun rxq->pending--;
713*4882a593Smuzhiyun rxq->out.ptr = NEXTQ (rxq->out.ptr, rxq->out.start, rxq->out.limit);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun if (rxq->pending < rxq->low)
716*4882a593Smuzhiyun rxq->low = rxq->pending;
717*4882a593Smuzhiyun spin_unlock_irqrestore (&rxq->lock, flags);
718*4882a593Smuzhiyun return 0;
719*4882a593Smuzhiyun } else {
720*4882a593Smuzhiyun if (!rxq->pending && rxq->buffers_wanted)
721*4882a593Smuzhiyun rxq->emptied++;
722*4882a593Smuzhiyun spin_unlock_irqrestore (&rxq->lock, flags);
723*4882a593Smuzhiyun return -1;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun /********** RX Pool handling **********/
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /* pre: buffers_wanted = 0, post: pending = 0 */
drain_rx_pool(amb_dev * dev,unsigned char pool)730*4882a593Smuzhiyun static void drain_rx_pool (amb_dev * dev, unsigned char pool) {
731*4882a593Smuzhiyun amb_rxq * rxq = &dev->rxq[pool];
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_POOL, "drain_rx_pool %p %hu", dev, pool);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun if (test_bit (dead, &dev->flags))
736*4882a593Smuzhiyun return;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun /* we are not quite like the fill pool routines as we cannot just
739*4882a593Smuzhiyun remove one buffer, we have to remove all of them, but we might as
740*4882a593Smuzhiyun well pretend... */
741*4882a593Smuzhiyun if (rxq->pending > rxq->buffers_wanted) {
742*4882a593Smuzhiyun command cmd;
743*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_FLUSH_BUFFER_Q);
744*4882a593Smuzhiyun cmd.args.flush.flags = cpu_to_be32 (pool << SRB_POOL_SHIFT);
745*4882a593Smuzhiyun while (command_do (dev, &cmd))
746*4882a593Smuzhiyun schedule();
747*4882a593Smuzhiyun /* the pool may also be emptied via the interrupt handler */
748*4882a593Smuzhiyun while (rxq->pending > rxq->buffers_wanted)
749*4882a593Smuzhiyun if (rx_take (dev, pool))
750*4882a593Smuzhiyun schedule();
751*4882a593Smuzhiyun }
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun return;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
drain_rx_pools(amb_dev * dev)756*4882a593Smuzhiyun static void drain_rx_pools (amb_dev * dev) {
757*4882a593Smuzhiyun unsigned char pool;
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_POOL, "drain_rx_pools %p", dev);
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
762*4882a593Smuzhiyun drain_rx_pool (dev, pool);
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
fill_rx_pool(amb_dev * dev,unsigned char pool,gfp_t priority)765*4882a593Smuzhiyun static void fill_rx_pool (amb_dev * dev, unsigned char pool,
766*4882a593Smuzhiyun gfp_t priority)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun rx_in rx;
769*4882a593Smuzhiyun amb_rxq * rxq;
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_POOL, "fill_rx_pool %p %hu %x", dev, pool, priority);
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun if (test_bit (dead, &dev->flags))
774*4882a593Smuzhiyun return;
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun rxq = &dev->rxq[pool];
777*4882a593Smuzhiyun while (rxq->pending < rxq->maximum && rxq->pending < rxq->buffers_wanted) {
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun struct sk_buff * skb = alloc_skb (rxq->buffer_size, priority);
780*4882a593Smuzhiyun if (!skb) {
781*4882a593Smuzhiyun PRINTD (DBG_SKB|DBG_POOL, "failed to allocate skb for RX pool %hu", pool);
782*4882a593Smuzhiyun return;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun if (check_area (skb->data, skb->truesize)) {
785*4882a593Smuzhiyun dev_kfree_skb_any (skb);
786*4882a593Smuzhiyun return;
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun // cast needed as there is no %? for pointer differences
789*4882a593Smuzhiyun PRINTD (DBG_SKB, "allocated skb at %p, head %p, area %li",
790*4882a593Smuzhiyun skb, skb->head, (long) skb_end_offset(skb));
791*4882a593Smuzhiyun rx.handle = virt_to_bus (skb);
792*4882a593Smuzhiyun rx.host_address = cpu_to_be32 (virt_to_bus (skb->data));
793*4882a593Smuzhiyun if (rx_give (dev, &rx, pool))
794*4882a593Smuzhiyun dev_kfree_skb_any (skb);
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun return;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun // top up all RX pools
fill_rx_pools(amb_dev * dev)802*4882a593Smuzhiyun static void fill_rx_pools (amb_dev * dev) {
803*4882a593Smuzhiyun unsigned char pool;
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_POOL, "fill_rx_pools %p", dev);
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
808*4882a593Smuzhiyun fill_rx_pool (dev, pool, GFP_ATOMIC);
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun return;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun /********** enable host interrupts **********/
814*4882a593Smuzhiyun
interrupts_on(amb_dev * dev)815*4882a593Smuzhiyun static void interrupts_on (amb_dev * dev) {
816*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, interrupt_control),
817*4882a593Smuzhiyun rd_plain (dev, offsetof(amb_mem, interrupt_control))
818*4882a593Smuzhiyun | AMB_INTERRUPT_BITS);
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun /********** disable host interrupts **********/
822*4882a593Smuzhiyun
interrupts_off(amb_dev * dev)823*4882a593Smuzhiyun static void interrupts_off (amb_dev * dev) {
824*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, interrupt_control),
825*4882a593Smuzhiyun rd_plain (dev, offsetof(amb_mem, interrupt_control))
826*4882a593Smuzhiyun &~ AMB_INTERRUPT_BITS);
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun /********** interrupt handling **********/
830*4882a593Smuzhiyun
interrupt_handler(int irq,void * dev_id)831*4882a593Smuzhiyun static irqreturn_t interrupt_handler(int irq, void *dev_id) {
832*4882a593Smuzhiyun amb_dev * dev = dev_id;
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler: %p", dev_id);
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun u32 interrupt = rd_plain (dev, offsetof(amb_mem, interrupt));
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun // for us or someone else sharing the same interrupt
840*4882a593Smuzhiyun if (!interrupt) {
841*4882a593Smuzhiyun PRINTD (DBG_IRQ, "irq not for me: %d", irq);
842*4882a593Smuzhiyun return IRQ_NONE;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun // definitely for us
846*4882a593Smuzhiyun PRINTD (DBG_IRQ, "FYI: interrupt was %08x", interrupt);
847*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, interrupt), -1);
848*4882a593Smuzhiyun }
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun {
851*4882a593Smuzhiyun unsigned int irq_work = 0;
852*4882a593Smuzhiyun unsigned char pool;
853*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
854*4882a593Smuzhiyun while (!rx_take (dev, pool))
855*4882a593Smuzhiyun ++irq_work;
856*4882a593Smuzhiyun while (!tx_take (dev))
857*4882a593Smuzhiyun ++irq_work;
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun if (irq_work) {
860*4882a593Smuzhiyun fill_rx_pools (dev);
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun PRINTD (DBG_IRQ, "work done: %u", irq_work);
863*4882a593Smuzhiyun } else {
864*4882a593Smuzhiyun PRINTD (DBG_IRQ|DBG_WARN, "no work done");
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
869*4882a593Smuzhiyun return IRQ_HANDLED;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun /********** make rate (not quite as much fun as Horizon) **********/
873*4882a593Smuzhiyun
make_rate(unsigned int rate,rounding r,u16 * bits,unsigned int * actual)874*4882a593Smuzhiyun static int make_rate (unsigned int rate, rounding r,
875*4882a593Smuzhiyun u16 * bits, unsigned int * actual) {
876*4882a593Smuzhiyun unsigned char exp = -1; // hush gcc
877*4882a593Smuzhiyun unsigned int man = -1; // hush gcc
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_QOS, "make_rate %u", rate);
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun // rates in cells per second, ITU format (nasty 16-bit floating-point)
882*4882a593Smuzhiyun // given 5-bit e and 9-bit m:
883*4882a593Smuzhiyun // rate = EITHER (1+m/2^9)*2^e OR 0
884*4882a593Smuzhiyun // bits = EITHER 1<<14 | e<<9 | m OR 0
885*4882a593Smuzhiyun // (bit 15 is "reserved", bit 14 "non-zero")
886*4882a593Smuzhiyun // smallest rate is 0 (special representation)
887*4882a593Smuzhiyun // largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
888*4882a593Smuzhiyun // smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
889*4882a593Smuzhiyun // simple algorithm:
890*4882a593Smuzhiyun // find position of top bit, this gives e
891*4882a593Smuzhiyun // remove top bit and shift (rounding if feeling clever) by 9-e
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun // ucode bug: please don't set bit 14! so 0 rate not representable
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun if (rate > 0xffc00000U) {
896*4882a593Smuzhiyun // larger than largest representable rate
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun if (r == round_up) {
899*4882a593Smuzhiyun return -EINVAL;
900*4882a593Smuzhiyun } else {
901*4882a593Smuzhiyun exp = 31;
902*4882a593Smuzhiyun man = 511;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun } else if (rate) {
906*4882a593Smuzhiyun // representable rate
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun exp = 31;
909*4882a593Smuzhiyun man = rate;
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun // invariant: rate = man*2^(exp-31)
912*4882a593Smuzhiyun while (!(man & (1<<31))) {
913*4882a593Smuzhiyun exp = exp - 1;
914*4882a593Smuzhiyun man = man<<1;
915*4882a593Smuzhiyun }
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun // man has top bit set
918*4882a593Smuzhiyun // rate = (2^31+(man-2^31))*2^(exp-31)
919*4882a593Smuzhiyun // rate = (1+(man-2^31)/2^31)*2^exp
920*4882a593Smuzhiyun man = man<<1;
921*4882a593Smuzhiyun man &= 0xffffffffU; // a nop on 32-bit systems
922*4882a593Smuzhiyun // rate = (1+man/2^32)*2^exp
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun // exp is in the range 0 to 31, man is in the range 0 to 2^32-1
925*4882a593Smuzhiyun // time to lose significance... we want m in the range 0 to 2^9-1
926*4882a593Smuzhiyun // rounding presents a minor problem... we first decide which way
927*4882a593Smuzhiyun // we are rounding (based on given rounding direction and possibly
928*4882a593Smuzhiyun // the bits of the mantissa that are to be discarded).
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun switch (r) {
931*4882a593Smuzhiyun case round_down: {
932*4882a593Smuzhiyun // just truncate
933*4882a593Smuzhiyun man = man>>(32-9);
934*4882a593Smuzhiyun break;
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun case round_up: {
937*4882a593Smuzhiyun // check all bits that we are discarding
938*4882a593Smuzhiyun if (man & (~0U>>9)) {
939*4882a593Smuzhiyun man = (man>>(32-9)) + 1;
940*4882a593Smuzhiyun if (man == (1<<9)) {
941*4882a593Smuzhiyun // no need to check for round up outside of range
942*4882a593Smuzhiyun man = 0;
943*4882a593Smuzhiyun exp += 1;
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun } else {
946*4882a593Smuzhiyun man = (man>>(32-9));
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun break;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun case round_nearest: {
951*4882a593Smuzhiyun // check msb that we are discarding
952*4882a593Smuzhiyun if (man & (1<<(32-9-1))) {
953*4882a593Smuzhiyun man = (man>>(32-9)) + 1;
954*4882a593Smuzhiyun if (man == (1<<9)) {
955*4882a593Smuzhiyun // no need to check for round up outside of range
956*4882a593Smuzhiyun man = 0;
957*4882a593Smuzhiyun exp += 1;
958*4882a593Smuzhiyun }
959*4882a593Smuzhiyun } else {
960*4882a593Smuzhiyun man = (man>>(32-9));
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun break;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun } else {
967*4882a593Smuzhiyun // zero rate - not representable
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun if (r == round_down) {
970*4882a593Smuzhiyun return -EINVAL;
971*4882a593Smuzhiyun } else {
972*4882a593Smuzhiyun exp = 0;
973*4882a593Smuzhiyun man = 0;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun PRINTD (DBG_QOS, "rate: man=%u, exp=%hu", man, exp);
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun if (bits)
981*4882a593Smuzhiyun *bits = /* (1<<14) | */ (exp<<9) | man;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (actual)
984*4882a593Smuzhiyun *actual = (exp >= 9)
985*4882a593Smuzhiyun ? (1 << exp) + (man << (exp-9))
986*4882a593Smuzhiyun : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun return 0;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun /********** Linux ATM Operations **********/
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun // some are not yet implemented while others do not make sense for
994*4882a593Smuzhiyun // this device
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun /********** Open a VC **********/
997*4882a593Smuzhiyun
amb_open(struct atm_vcc * atm_vcc)998*4882a593Smuzhiyun static int amb_open (struct atm_vcc * atm_vcc)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun int error;
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun struct atm_qos * qos;
1003*4882a593Smuzhiyun struct atm_trafprm * txtp;
1004*4882a593Smuzhiyun struct atm_trafprm * rxtp;
1005*4882a593Smuzhiyun u16 tx_rate_bits = -1; // hush gcc
1006*4882a593Smuzhiyun u16 tx_vc_bits = -1; // hush gcc
1007*4882a593Smuzhiyun u16 tx_frame_bits = -1; // hush gcc
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun amb_dev * dev = AMB_DEV(atm_vcc->dev);
1010*4882a593Smuzhiyun amb_vcc * vcc;
1011*4882a593Smuzhiyun unsigned char pool = -1; // hush gcc
1012*4882a593Smuzhiyun short vpi = atm_vcc->vpi;
1013*4882a593Smuzhiyun int vci = atm_vcc->vci;
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_VCC, "amb_open %x %x", vpi, vci);
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun #ifdef ATM_VPI_UNSPEC
1018*4882a593Smuzhiyun // UNSPEC is deprecated, remove this code eventually
1019*4882a593Smuzhiyun if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
1020*4882a593Smuzhiyun PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
1021*4882a593Smuzhiyun return -EINVAL;
1022*4882a593Smuzhiyun }
1023*4882a593Smuzhiyun #endif
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun if (!(0 <= vpi && vpi < (1<<NUM_VPI_BITS) &&
1026*4882a593Smuzhiyun 0 <= vci && vci < (1<<NUM_VCI_BITS))) {
1027*4882a593Smuzhiyun PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
1028*4882a593Smuzhiyun return -EINVAL;
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun qos = &atm_vcc->qos;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun if (qos->aal != ATM_AAL5) {
1034*4882a593Smuzhiyun PRINTD (DBG_QOS, "AAL not supported");
1035*4882a593Smuzhiyun return -EINVAL;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun // traffic parameters
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun PRINTD (DBG_QOS, "TX:");
1041*4882a593Smuzhiyun txtp = &qos->txtp;
1042*4882a593Smuzhiyun if (txtp->traffic_class != ATM_NONE) {
1043*4882a593Smuzhiyun switch (txtp->traffic_class) {
1044*4882a593Smuzhiyun case ATM_UBR: {
1045*4882a593Smuzhiyun // we take "the PCR" as a rate-cap
1046*4882a593Smuzhiyun int pcr = atm_pcr_goal (txtp);
1047*4882a593Smuzhiyun if (!pcr) {
1048*4882a593Smuzhiyun // no rate cap
1049*4882a593Smuzhiyun tx_rate_bits = 0;
1050*4882a593Smuzhiyun tx_vc_bits = TX_UBR;
1051*4882a593Smuzhiyun tx_frame_bits = TX_FRAME_NOTCAP;
1052*4882a593Smuzhiyun } else {
1053*4882a593Smuzhiyun rounding r;
1054*4882a593Smuzhiyun if (pcr < 0) {
1055*4882a593Smuzhiyun r = round_down;
1056*4882a593Smuzhiyun pcr = -pcr;
1057*4882a593Smuzhiyun } else {
1058*4882a593Smuzhiyun r = round_up;
1059*4882a593Smuzhiyun }
1060*4882a593Smuzhiyun error = make_rate (pcr, r, &tx_rate_bits, NULL);
1061*4882a593Smuzhiyun if (error)
1062*4882a593Smuzhiyun return error;
1063*4882a593Smuzhiyun tx_vc_bits = TX_UBR_CAPPED;
1064*4882a593Smuzhiyun tx_frame_bits = TX_FRAME_CAPPED;
1065*4882a593Smuzhiyun }
1066*4882a593Smuzhiyun break;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun #if 0
1069*4882a593Smuzhiyun case ATM_ABR: {
1070*4882a593Smuzhiyun pcr = atm_pcr_goal (txtp);
1071*4882a593Smuzhiyun PRINTD (DBG_QOS, "pcr goal = %d", pcr);
1072*4882a593Smuzhiyun break;
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun #endif
1075*4882a593Smuzhiyun default: {
1076*4882a593Smuzhiyun // PRINTD (DBG_QOS, "request for non-UBR/ABR denied");
1077*4882a593Smuzhiyun PRINTD (DBG_QOS, "request for non-UBR denied");
1078*4882a593Smuzhiyun return -EINVAL;
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun PRINTD (DBG_QOS, "tx_rate_bits=%hx, tx_vc_bits=%hx",
1082*4882a593Smuzhiyun tx_rate_bits, tx_vc_bits);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun PRINTD (DBG_QOS, "RX:");
1086*4882a593Smuzhiyun rxtp = &qos->rxtp;
1087*4882a593Smuzhiyun if (rxtp->traffic_class == ATM_NONE) {
1088*4882a593Smuzhiyun // do nothing
1089*4882a593Smuzhiyun } else {
1090*4882a593Smuzhiyun // choose an RX pool (arranged in increasing size)
1091*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
1092*4882a593Smuzhiyun if ((unsigned int) rxtp->max_sdu <= dev->rxq[pool].buffer_size) {
1093*4882a593Smuzhiyun PRINTD (DBG_VCC|DBG_QOS|DBG_POOL, "chose pool %hu (max_sdu %u <= %u)",
1094*4882a593Smuzhiyun pool, rxtp->max_sdu, dev->rxq[pool].buffer_size);
1095*4882a593Smuzhiyun break;
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun if (pool == NUM_RX_POOLS) {
1098*4882a593Smuzhiyun PRINTD (DBG_WARN|DBG_VCC|DBG_QOS|DBG_POOL,
1099*4882a593Smuzhiyun "no pool suitable for VC (RX max_sdu %d is too large)",
1100*4882a593Smuzhiyun rxtp->max_sdu);
1101*4882a593Smuzhiyun return -EINVAL;
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun switch (rxtp->traffic_class) {
1105*4882a593Smuzhiyun case ATM_UBR: {
1106*4882a593Smuzhiyun break;
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun #if 0
1109*4882a593Smuzhiyun case ATM_ABR: {
1110*4882a593Smuzhiyun pcr = atm_pcr_goal (rxtp);
1111*4882a593Smuzhiyun PRINTD (DBG_QOS, "pcr goal = %d", pcr);
1112*4882a593Smuzhiyun break;
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun #endif
1115*4882a593Smuzhiyun default: {
1116*4882a593Smuzhiyun // PRINTD (DBG_QOS, "request for non-UBR/ABR denied");
1117*4882a593Smuzhiyun PRINTD (DBG_QOS, "request for non-UBR denied");
1118*4882a593Smuzhiyun return -EINVAL;
1119*4882a593Smuzhiyun }
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun }
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun // get space for our vcc stuff
1124*4882a593Smuzhiyun vcc = kmalloc (sizeof(amb_vcc), GFP_KERNEL);
1125*4882a593Smuzhiyun if (!vcc) {
1126*4882a593Smuzhiyun PRINTK (KERN_ERR, "out of memory!");
1127*4882a593Smuzhiyun return -ENOMEM;
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun atm_vcc->dev_data = (void *) vcc;
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun // no failures beyond this point
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun // we are not really "immediately before allocating the connection
1134*4882a593Smuzhiyun // identifier in hardware", but it will just have to do!
1135*4882a593Smuzhiyun set_bit(ATM_VF_ADDR,&atm_vcc->flags);
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun if (txtp->traffic_class != ATM_NONE) {
1138*4882a593Smuzhiyun command cmd;
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun vcc->tx_frame_bits = tx_frame_bits;
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun mutex_lock(&dev->vcc_sf);
1143*4882a593Smuzhiyun if (dev->rxer[vci]) {
1144*4882a593Smuzhiyun // RXer on the channel already, just modify rate...
1145*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_MODIFY_VC_RATE);
1146*4882a593Smuzhiyun cmd.args.modify_rate.vc = cpu_to_be32 (vci); // vpi 0
1147*4882a593Smuzhiyun cmd.args.modify_rate.rate = cpu_to_be32 (tx_rate_bits << SRB_RATE_SHIFT);
1148*4882a593Smuzhiyun while (command_do (dev, &cmd))
1149*4882a593Smuzhiyun schedule();
1150*4882a593Smuzhiyun // ... and TX flags, preserving the RX pool
1151*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_MODIFY_VC_FLAGS);
1152*4882a593Smuzhiyun cmd.args.modify_flags.vc = cpu_to_be32 (vci); // vpi 0
1153*4882a593Smuzhiyun cmd.args.modify_flags.flags = cpu_to_be32
1154*4882a593Smuzhiyun ( (AMB_VCC(dev->rxer[vci])->rx_info.pool << SRB_POOL_SHIFT)
1155*4882a593Smuzhiyun | (tx_vc_bits << SRB_FLAGS_SHIFT) );
1156*4882a593Smuzhiyun while (command_do (dev, &cmd))
1157*4882a593Smuzhiyun schedule();
1158*4882a593Smuzhiyun } else {
1159*4882a593Smuzhiyun // no RXer on the channel, just open (with pool zero)
1160*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_OPEN_VC);
1161*4882a593Smuzhiyun cmd.args.open.vc = cpu_to_be32 (vci); // vpi 0
1162*4882a593Smuzhiyun cmd.args.open.flags = cpu_to_be32 (tx_vc_bits << SRB_FLAGS_SHIFT);
1163*4882a593Smuzhiyun cmd.args.open.rate = cpu_to_be32 (tx_rate_bits << SRB_RATE_SHIFT);
1164*4882a593Smuzhiyun while (command_do (dev, &cmd))
1165*4882a593Smuzhiyun schedule();
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun dev->txer[vci].tx_present = 1;
1168*4882a593Smuzhiyun mutex_unlock(&dev->vcc_sf);
1169*4882a593Smuzhiyun }
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun if (rxtp->traffic_class != ATM_NONE) {
1172*4882a593Smuzhiyun command cmd;
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun vcc->rx_info.pool = pool;
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun mutex_lock(&dev->vcc_sf);
1177*4882a593Smuzhiyun /* grow RX buffer pool */
1178*4882a593Smuzhiyun if (!dev->rxq[pool].buffers_wanted)
1179*4882a593Smuzhiyun dev->rxq[pool].buffers_wanted = rx_lats;
1180*4882a593Smuzhiyun dev->rxq[pool].buffers_wanted += 1;
1181*4882a593Smuzhiyun fill_rx_pool (dev, pool, GFP_KERNEL);
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun if (dev->txer[vci].tx_present) {
1184*4882a593Smuzhiyun // TXer on the channel already
1185*4882a593Smuzhiyun // switch (from pool zero) to this pool, preserving the TX bits
1186*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_MODIFY_VC_FLAGS);
1187*4882a593Smuzhiyun cmd.args.modify_flags.vc = cpu_to_be32 (vci); // vpi 0
1188*4882a593Smuzhiyun cmd.args.modify_flags.flags = cpu_to_be32
1189*4882a593Smuzhiyun ( (pool << SRB_POOL_SHIFT)
1190*4882a593Smuzhiyun | (dev->txer[vci].tx_vc_bits << SRB_FLAGS_SHIFT) );
1191*4882a593Smuzhiyun } else {
1192*4882a593Smuzhiyun // no TXer on the channel, open the VC (with no rate info)
1193*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_OPEN_VC);
1194*4882a593Smuzhiyun cmd.args.open.vc = cpu_to_be32 (vci); // vpi 0
1195*4882a593Smuzhiyun cmd.args.open.flags = cpu_to_be32 (pool << SRB_POOL_SHIFT);
1196*4882a593Smuzhiyun cmd.args.open.rate = cpu_to_be32 (0);
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun while (command_do (dev, &cmd))
1199*4882a593Smuzhiyun schedule();
1200*4882a593Smuzhiyun // this link allows RX frames through
1201*4882a593Smuzhiyun dev->rxer[vci] = atm_vcc;
1202*4882a593Smuzhiyun mutex_unlock(&dev->vcc_sf);
1203*4882a593Smuzhiyun }
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun // indicate readiness
1206*4882a593Smuzhiyun set_bit(ATM_VF_READY,&atm_vcc->flags);
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun return 0;
1209*4882a593Smuzhiyun }
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun /********** Close a VC **********/
1212*4882a593Smuzhiyun
amb_close(struct atm_vcc * atm_vcc)1213*4882a593Smuzhiyun static void amb_close (struct atm_vcc * atm_vcc) {
1214*4882a593Smuzhiyun amb_dev * dev = AMB_DEV (atm_vcc->dev);
1215*4882a593Smuzhiyun amb_vcc * vcc = AMB_VCC (atm_vcc);
1216*4882a593Smuzhiyun u16 vci = atm_vcc->vci;
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun PRINTD (DBG_VCC|DBG_FLOW, "amb_close");
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun // indicate unreadiness
1221*4882a593Smuzhiyun clear_bit(ATM_VF_READY,&atm_vcc->flags);
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun // disable TXing
1224*4882a593Smuzhiyun if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
1225*4882a593Smuzhiyun command cmd;
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun mutex_lock(&dev->vcc_sf);
1228*4882a593Smuzhiyun if (dev->rxer[vci]) {
1229*4882a593Smuzhiyun // RXer still on the channel, just modify rate... XXX not really needed
1230*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_MODIFY_VC_RATE);
1231*4882a593Smuzhiyun cmd.args.modify_rate.vc = cpu_to_be32 (vci); // vpi 0
1232*4882a593Smuzhiyun cmd.args.modify_rate.rate = cpu_to_be32 (0);
1233*4882a593Smuzhiyun // ... and clear TX rate flags (XXX to stop RM cell output?), preserving RX pool
1234*4882a593Smuzhiyun } else {
1235*4882a593Smuzhiyun // no RXer on the channel, close channel
1236*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_CLOSE_VC);
1237*4882a593Smuzhiyun cmd.args.close.vc = cpu_to_be32 (vci); // vpi 0
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun dev->txer[vci].tx_present = 0;
1240*4882a593Smuzhiyun while (command_do (dev, &cmd))
1241*4882a593Smuzhiyun schedule();
1242*4882a593Smuzhiyun mutex_unlock(&dev->vcc_sf);
1243*4882a593Smuzhiyun }
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun // disable RXing
1246*4882a593Smuzhiyun if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1247*4882a593Smuzhiyun command cmd;
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun // this is (the?) one reason why we need the amb_vcc struct
1250*4882a593Smuzhiyun unsigned char pool = vcc->rx_info.pool;
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun mutex_lock(&dev->vcc_sf);
1253*4882a593Smuzhiyun if (dev->txer[vci].tx_present) {
1254*4882a593Smuzhiyun // TXer still on the channel, just go to pool zero XXX not really needed
1255*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_MODIFY_VC_FLAGS);
1256*4882a593Smuzhiyun cmd.args.modify_flags.vc = cpu_to_be32 (vci); // vpi 0
1257*4882a593Smuzhiyun cmd.args.modify_flags.flags = cpu_to_be32
1258*4882a593Smuzhiyun (dev->txer[vci].tx_vc_bits << SRB_FLAGS_SHIFT);
1259*4882a593Smuzhiyun } else {
1260*4882a593Smuzhiyun // no TXer on the channel, close the VC
1261*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_CLOSE_VC);
1262*4882a593Smuzhiyun cmd.args.close.vc = cpu_to_be32 (vci); // vpi 0
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun // forget the rxer - no more skbs will be pushed
1265*4882a593Smuzhiyun if (atm_vcc != dev->rxer[vci])
1266*4882a593Smuzhiyun PRINTK (KERN_ERR, "%s vcc=%p rxer[vci]=%p",
1267*4882a593Smuzhiyun "arghhh! we're going to die!",
1268*4882a593Smuzhiyun vcc, dev->rxer[vci]);
1269*4882a593Smuzhiyun dev->rxer[vci] = NULL;
1270*4882a593Smuzhiyun while (command_do (dev, &cmd))
1271*4882a593Smuzhiyun schedule();
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun /* shrink RX buffer pool */
1274*4882a593Smuzhiyun dev->rxq[pool].buffers_wanted -= 1;
1275*4882a593Smuzhiyun if (dev->rxq[pool].buffers_wanted == rx_lats) {
1276*4882a593Smuzhiyun dev->rxq[pool].buffers_wanted = 0;
1277*4882a593Smuzhiyun drain_rx_pool (dev, pool);
1278*4882a593Smuzhiyun }
1279*4882a593Smuzhiyun mutex_unlock(&dev->vcc_sf);
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun // free our structure
1283*4882a593Smuzhiyun kfree (vcc);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun // say the VPI/VCI is free again
1286*4882a593Smuzhiyun clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun return;
1289*4882a593Smuzhiyun }
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun /********** Send **********/
1292*4882a593Smuzhiyun
amb_send(struct atm_vcc * atm_vcc,struct sk_buff * skb)1293*4882a593Smuzhiyun static int amb_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1294*4882a593Smuzhiyun amb_dev * dev = AMB_DEV(atm_vcc->dev);
1295*4882a593Smuzhiyun amb_vcc * vcc = AMB_VCC(atm_vcc);
1296*4882a593Smuzhiyun u16 vc = atm_vcc->vci;
1297*4882a593Smuzhiyun unsigned int tx_len = skb->len;
1298*4882a593Smuzhiyun unsigned char * tx_data = skb->data;
1299*4882a593Smuzhiyun tx_simple * tx_descr;
1300*4882a593Smuzhiyun tx_in tx;
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun if (test_bit (dead, &dev->flags))
1303*4882a593Smuzhiyun return -EIO;
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_TX, "amb_send vc %x data %p len %u",
1306*4882a593Smuzhiyun vc, tx_data, tx_len);
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun dump_skb (">>>", vc, skb);
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun if (!dev->txer[vc].tx_present) {
1311*4882a593Smuzhiyun PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", vc);
1312*4882a593Smuzhiyun return -EBADFD;
1313*4882a593Smuzhiyun }
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun // this is a driver private field so we have to set it ourselves,
1316*4882a593Smuzhiyun // despite the fact that we are _required_ to use it to check for a
1317*4882a593Smuzhiyun // pop function
1318*4882a593Smuzhiyun ATM_SKB(skb)->vcc = atm_vcc;
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun if (skb->len > (size_t) atm_vcc->qos.txtp.max_sdu) {
1321*4882a593Smuzhiyun PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1322*4882a593Smuzhiyun return -EIO;
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun if (check_area (skb->data, skb->len)) {
1326*4882a593Smuzhiyun atomic_inc(&atm_vcc->stats->tx_err);
1327*4882a593Smuzhiyun return -ENOMEM; // ?
1328*4882a593Smuzhiyun }
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun // allocate memory for fragments
1331*4882a593Smuzhiyun tx_descr = kmalloc (sizeof(tx_simple), GFP_KERNEL);
1332*4882a593Smuzhiyun if (!tx_descr) {
1333*4882a593Smuzhiyun PRINTK (KERN_ERR, "could not allocate TX descriptor");
1334*4882a593Smuzhiyun return -ENOMEM;
1335*4882a593Smuzhiyun }
1336*4882a593Smuzhiyun if (check_area (tx_descr, sizeof(tx_simple))) {
1337*4882a593Smuzhiyun kfree (tx_descr);
1338*4882a593Smuzhiyun return -ENOMEM;
1339*4882a593Smuzhiyun }
1340*4882a593Smuzhiyun PRINTD (DBG_TX, "fragment list allocated at %p", tx_descr);
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun tx_descr->skb = skb;
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun tx_descr->tx_frag.bytes = cpu_to_be32 (tx_len);
1345*4882a593Smuzhiyun tx_descr->tx_frag.address = cpu_to_be32 (virt_to_bus (tx_data));
1346*4882a593Smuzhiyun
1347*4882a593Smuzhiyun tx_descr->tx_frag_end.handle = virt_to_bus (tx_descr);
1348*4882a593Smuzhiyun tx_descr->tx_frag_end.vc = 0;
1349*4882a593Smuzhiyun tx_descr->tx_frag_end.next_descriptor_length = 0;
1350*4882a593Smuzhiyun tx_descr->tx_frag_end.next_descriptor = 0;
1351*4882a593Smuzhiyun #ifdef AMB_NEW_MICROCODE
1352*4882a593Smuzhiyun tx_descr->tx_frag_end.cpcs_uu = 0;
1353*4882a593Smuzhiyun tx_descr->tx_frag_end.cpi = 0;
1354*4882a593Smuzhiyun tx_descr->tx_frag_end.pad = 0;
1355*4882a593Smuzhiyun #endif
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun tx.vc = cpu_to_be16 (vcc->tx_frame_bits | vc);
1358*4882a593Smuzhiyun tx.tx_descr_length = cpu_to_be16 (sizeof(tx_frag)+sizeof(tx_frag_end));
1359*4882a593Smuzhiyun tx.tx_descr_addr = cpu_to_be32 (virt_to_bus (&tx_descr->tx_frag));
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun while (tx_give (dev, &tx))
1362*4882a593Smuzhiyun schedule();
1363*4882a593Smuzhiyun return 0;
1364*4882a593Smuzhiyun }
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun /********** Change QoS on a VC **********/
1367*4882a593Smuzhiyun
1368*4882a593Smuzhiyun // int amb_change_qos (struct atm_vcc * atm_vcc, struct atm_qos * qos, int flags);
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun /********** Free RX Socket Buffer **********/
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun #if 0
1373*4882a593Smuzhiyun static void amb_free_rx_skb (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1374*4882a593Smuzhiyun amb_dev * dev = AMB_DEV (atm_vcc->dev);
1375*4882a593Smuzhiyun amb_vcc * vcc = AMB_VCC (atm_vcc);
1376*4882a593Smuzhiyun unsigned char pool = vcc->rx_info.pool;
1377*4882a593Smuzhiyun rx_in rx;
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun // This may be unsafe for various reasons that I cannot really guess
1380*4882a593Smuzhiyun // at. However, I note that the ATM layer calls kfree_skb rather
1381*4882a593Smuzhiyun // than dev_kfree_skb at this point so we are least covered as far
1382*4882a593Smuzhiyun // as buffer locking goes. There may be bugs if pcap clones RX skbs.
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_SKB, "amb_rx_free skb %p (atm_vcc %p, vcc %p)",
1385*4882a593Smuzhiyun skb, atm_vcc, vcc);
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun rx.handle = virt_to_bus (skb);
1388*4882a593Smuzhiyun rx.host_address = cpu_to_be32 (virt_to_bus (skb->data));
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun skb->data = skb->head;
1391*4882a593Smuzhiyun skb_reset_tail_pointer(skb);
1392*4882a593Smuzhiyun skb->len = 0;
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun if (!rx_give (dev, &rx, pool)) {
1395*4882a593Smuzhiyun // success
1396*4882a593Smuzhiyun PRINTD (DBG_SKB|DBG_POOL, "recycled skb for pool %hu", pool);
1397*4882a593Smuzhiyun return;
1398*4882a593Smuzhiyun }
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun // just do what the ATM layer would have done
1401*4882a593Smuzhiyun dev_kfree_skb_any (skb);
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun return;
1404*4882a593Smuzhiyun }
1405*4882a593Smuzhiyun #endif
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun /********** Proc File Output **********/
1408*4882a593Smuzhiyun
amb_proc_read(struct atm_dev * atm_dev,loff_t * pos,char * page)1409*4882a593Smuzhiyun static int amb_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
1410*4882a593Smuzhiyun amb_dev * dev = AMB_DEV (atm_dev);
1411*4882a593Smuzhiyun int left = *pos;
1412*4882a593Smuzhiyun unsigned char pool;
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun PRINTD (DBG_FLOW, "amb_proc_read");
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun /* more diagnostics here? */
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun if (!left--) {
1419*4882a593Smuzhiyun amb_stats * s = &dev->stats;
1420*4882a593Smuzhiyun return sprintf (page,
1421*4882a593Smuzhiyun "frames: TX OK %lu, RX OK %lu, RX bad %lu "
1422*4882a593Smuzhiyun "(CRC %lu, long %lu, aborted %lu, unused %lu).\n",
1423*4882a593Smuzhiyun s->tx_ok, s->rx.ok, s->rx.error,
1424*4882a593Smuzhiyun s->rx.badcrc, s->rx.toolong,
1425*4882a593Smuzhiyun s->rx.aborted, s->rx.unused);
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun if (!left--) {
1429*4882a593Smuzhiyun amb_cq * c = &dev->cq;
1430*4882a593Smuzhiyun return sprintf (page, "cmd queue [cur/hi/max]: %u/%u/%u. ",
1431*4882a593Smuzhiyun c->pending, c->high, c->maximum);
1432*4882a593Smuzhiyun }
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun if (!left--) {
1435*4882a593Smuzhiyun amb_txq * t = &dev->txq;
1436*4882a593Smuzhiyun return sprintf (page, "TX queue [cur/max high full]: %u/%u %u %u.\n",
1437*4882a593Smuzhiyun t->pending, t->maximum, t->high, t->filled);
1438*4882a593Smuzhiyun }
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun if (!left--) {
1441*4882a593Smuzhiyun unsigned int count = sprintf (page, "RX queues [cur/max/req low empty]:");
1442*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
1443*4882a593Smuzhiyun amb_rxq * r = &dev->rxq[pool];
1444*4882a593Smuzhiyun count += sprintf (page+count, " %u/%u/%u %u %u",
1445*4882a593Smuzhiyun r->pending, r->maximum, r->buffers_wanted, r->low, r->emptied);
1446*4882a593Smuzhiyun }
1447*4882a593Smuzhiyun count += sprintf (page+count, ".\n");
1448*4882a593Smuzhiyun return count;
1449*4882a593Smuzhiyun }
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun if (!left--) {
1452*4882a593Smuzhiyun unsigned int count = sprintf (page, "RX buffer sizes:");
1453*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
1454*4882a593Smuzhiyun amb_rxq * r = &dev->rxq[pool];
1455*4882a593Smuzhiyun count += sprintf (page+count, " %u", r->buffer_size);
1456*4882a593Smuzhiyun }
1457*4882a593Smuzhiyun count += sprintf (page+count, ".\n");
1458*4882a593Smuzhiyun return count;
1459*4882a593Smuzhiyun }
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun #if 0
1462*4882a593Smuzhiyun if (!left--) {
1463*4882a593Smuzhiyun // suni block etc?
1464*4882a593Smuzhiyun }
1465*4882a593Smuzhiyun #endif
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun return 0;
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun /********** Operation Structure **********/
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun static const struct atmdev_ops amb_ops = {
1473*4882a593Smuzhiyun .open = amb_open,
1474*4882a593Smuzhiyun .close = amb_close,
1475*4882a593Smuzhiyun .send = amb_send,
1476*4882a593Smuzhiyun .proc_read = amb_proc_read,
1477*4882a593Smuzhiyun .owner = THIS_MODULE,
1478*4882a593Smuzhiyun };
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun /********** housekeeping **********/
do_housekeeping(struct timer_list * t)1481*4882a593Smuzhiyun static void do_housekeeping (struct timer_list *t) {
1482*4882a593Smuzhiyun amb_dev * dev = from_timer(dev, t, housekeeping);
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun // could collect device-specific (not driver/atm-linux) stats here
1485*4882a593Smuzhiyun
1486*4882a593Smuzhiyun // last resort refill once every ten seconds
1487*4882a593Smuzhiyun fill_rx_pools (dev);
1488*4882a593Smuzhiyun mod_timer(&dev->housekeeping, jiffies + 10*HZ);
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun return;
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun /********** creation of communication queues **********/
1494*4882a593Smuzhiyun
create_queues(amb_dev * dev,unsigned int cmds,unsigned int txs,unsigned int * rxs,unsigned int * rx_buffer_sizes)1495*4882a593Smuzhiyun static int create_queues(amb_dev *dev, unsigned int cmds, unsigned int txs,
1496*4882a593Smuzhiyun unsigned int *rxs, unsigned int *rx_buffer_sizes)
1497*4882a593Smuzhiyun {
1498*4882a593Smuzhiyun unsigned char pool;
1499*4882a593Smuzhiyun size_t total = 0;
1500*4882a593Smuzhiyun void * memory;
1501*4882a593Smuzhiyun void * limit;
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun PRINTD (DBG_FLOW, "create_queues %p", dev);
1504*4882a593Smuzhiyun
1505*4882a593Smuzhiyun total += cmds * sizeof(command);
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun total += txs * (sizeof(tx_in) + sizeof(tx_out));
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
1510*4882a593Smuzhiyun total += rxs[pool] * (sizeof(rx_in) + sizeof(rx_out));
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun memory = kmalloc (total, GFP_KERNEL);
1513*4882a593Smuzhiyun if (!memory) {
1514*4882a593Smuzhiyun PRINTK (KERN_ERR, "could not allocate queues");
1515*4882a593Smuzhiyun return -ENOMEM;
1516*4882a593Smuzhiyun }
1517*4882a593Smuzhiyun if (check_area (memory, total)) {
1518*4882a593Smuzhiyun PRINTK (KERN_ERR, "queues allocated in nasty area");
1519*4882a593Smuzhiyun kfree (memory);
1520*4882a593Smuzhiyun return -ENOMEM;
1521*4882a593Smuzhiyun }
1522*4882a593Smuzhiyun
1523*4882a593Smuzhiyun limit = memory + total;
1524*4882a593Smuzhiyun PRINTD (DBG_INIT, "queues from %p to %p", memory, limit);
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun PRINTD (DBG_CMD, "command queue at %p", memory);
1527*4882a593Smuzhiyun
1528*4882a593Smuzhiyun {
1529*4882a593Smuzhiyun command * cmd = memory;
1530*4882a593Smuzhiyun amb_cq * cq = &dev->cq;
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun cq->pending = 0;
1533*4882a593Smuzhiyun cq->high = 0;
1534*4882a593Smuzhiyun cq->maximum = cmds - 1;
1535*4882a593Smuzhiyun
1536*4882a593Smuzhiyun cq->ptrs.start = cmd;
1537*4882a593Smuzhiyun cq->ptrs.in = cmd;
1538*4882a593Smuzhiyun cq->ptrs.out = cmd;
1539*4882a593Smuzhiyun cq->ptrs.limit = cmd + cmds;
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun memory = cq->ptrs.limit;
1542*4882a593Smuzhiyun }
1543*4882a593Smuzhiyun
1544*4882a593Smuzhiyun PRINTD (DBG_TX, "TX queue pair at %p", memory);
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun {
1547*4882a593Smuzhiyun tx_in * in = memory;
1548*4882a593Smuzhiyun tx_out * out;
1549*4882a593Smuzhiyun amb_txq * txq = &dev->txq;
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun txq->pending = 0;
1552*4882a593Smuzhiyun txq->high = 0;
1553*4882a593Smuzhiyun txq->filled = 0;
1554*4882a593Smuzhiyun txq->maximum = txs - 1;
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun txq->in.start = in;
1557*4882a593Smuzhiyun txq->in.ptr = in;
1558*4882a593Smuzhiyun txq->in.limit = in + txs;
1559*4882a593Smuzhiyun
1560*4882a593Smuzhiyun memory = txq->in.limit;
1561*4882a593Smuzhiyun out = memory;
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun txq->out.start = out;
1564*4882a593Smuzhiyun txq->out.ptr = out;
1565*4882a593Smuzhiyun txq->out.limit = out + txs;
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun memory = txq->out.limit;
1568*4882a593Smuzhiyun }
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun PRINTD (DBG_RX, "RX queue pairs at %p", memory);
1571*4882a593Smuzhiyun
1572*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
1573*4882a593Smuzhiyun rx_in * in = memory;
1574*4882a593Smuzhiyun rx_out * out;
1575*4882a593Smuzhiyun amb_rxq * rxq = &dev->rxq[pool];
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun rxq->buffer_size = rx_buffer_sizes[pool];
1578*4882a593Smuzhiyun rxq->buffers_wanted = 0;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun rxq->pending = 0;
1581*4882a593Smuzhiyun rxq->low = rxs[pool] - 1;
1582*4882a593Smuzhiyun rxq->emptied = 0;
1583*4882a593Smuzhiyun rxq->maximum = rxs[pool] - 1;
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun rxq->in.start = in;
1586*4882a593Smuzhiyun rxq->in.ptr = in;
1587*4882a593Smuzhiyun rxq->in.limit = in + rxs[pool];
1588*4882a593Smuzhiyun
1589*4882a593Smuzhiyun memory = rxq->in.limit;
1590*4882a593Smuzhiyun out = memory;
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun rxq->out.start = out;
1593*4882a593Smuzhiyun rxq->out.ptr = out;
1594*4882a593Smuzhiyun rxq->out.limit = out + rxs[pool];
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun memory = rxq->out.limit;
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun
1599*4882a593Smuzhiyun if (memory == limit) {
1600*4882a593Smuzhiyun return 0;
1601*4882a593Smuzhiyun } else {
1602*4882a593Smuzhiyun PRINTK (KERN_ERR, "bad queue alloc %p != %p (tell maintainer)", memory, limit);
1603*4882a593Smuzhiyun kfree (limit - total);
1604*4882a593Smuzhiyun return -ENOMEM;
1605*4882a593Smuzhiyun }
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun }
1608*4882a593Smuzhiyun
1609*4882a593Smuzhiyun /********** destruction of communication queues **********/
1610*4882a593Smuzhiyun
destroy_queues(amb_dev * dev)1611*4882a593Smuzhiyun static void destroy_queues (amb_dev * dev) {
1612*4882a593Smuzhiyun // all queues assumed empty
1613*4882a593Smuzhiyun void * memory = dev->cq.ptrs.start;
1614*4882a593Smuzhiyun // includes txq.in, txq.out, rxq[].in and rxq[].out
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun PRINTD (DBG_FLOW, "destroy_queues %p", dev);
1617*4882a593Smuzhiyun
1618*4882a593Smuzhiyun PRINTD (DBG_INIT, "freeing queues at %p", memory);
1619*4882a593Smuzhiyun kfree (memory);
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun return;
1622*4882a593Smuzhiyun }
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun /********** basic loader commands and error handling **********/
1625*4882a593Smuzhiyun // centisecond timeouts - guessing away here
1626*4882a593Smuzhiyun static unsigned int command_timeouts [] = {
1627*4882a593Smuzhiyun [host_memory_test] = 15,
1628*4882a593Smuzhiyun [read_adapter_memory] = 2,
1629*4882a593Smuzhiyun [write_adapter_memory] = 2,
1630*4882a593Smuzhiyun [adapter_start] = 50,
1631*4882a593Smuzhiyun [get_version_number] = 10,
1632*4882a593Smuzhiyun [interrupt_host] = 1,
1633*4882a593Smuzhiyun [flash_erase_sector] = 1,
1634*4882a593Smuzhiyun [adap_download_block] = 1,
1635*4882a593Smuzhiyun [adap_erase_flash] = 1,
1636*4882a593Smuzhiyun [adap_run_in_iram] = 1,
1637*4882a593Smuzhiyun [adap_end_download] = 1
1638*4882a593Smuzhiyun };
1639*4882a593Smuzhiyun
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun static unsigned int command_successes [] = {
1642*4882a593Smuzhiyun [host_memory_test] = COMMAND_PASSED_TEST,
1643*4882a593Smuzhiyun [read_adapter_memory] = COMMAND_READ_DATA_OK,
1644*4882a593Smuzhiyun [write_adapter_memory] = COMMAND_WRITE_DATA_OK,
1645*4882a593Smuzhiyun [adapter_start] = COMMAND_COMPLETE,
1646*4882a593Smuzhiyun [get_version_number] = COMMAND_COMPLETE,
1647*4882a593Smuzhiyun [interrupt_host] = COMMAND_COMPLETE,
1648*4882a593Smuzhiyun [flash_erase_sector] = COMMAND_COMPLETE,
1649*4882a593Smuzhiyun [adap_download_block] = COMMAND_COMPLETE,
1650*4882a593Smuzhiyun [adap_erase_flash] = COMMAND_COMPLETE,
1651*4882a593Smuzhiyun [adap_run_in_iram] = COMMAND_COMPLETE,
1652*4882a593Smuzhiyun [adap_end_download] = COMMAND_COMPLETE
1653*4882a593Smuzhiyun };
1654*4882a593Smuzhiyun
decode_loader_result(loader_command cmd,u32 result)1655*4882a593Smuzhiyun static int decode_loader_result (loader_command cmd, u32 result)
1656*4882a593Smuzhiyun {
1657*4882a593Smuzhiyun int res;
1658*4882a593Smuzhiyun const char *msg;
1659*4882a593Smuzhiyun
1660*4882a593Smuzhiyun if (result == command_successes[cmd])
1661*4882a593Smuzhiyun return 0;
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun switch (result) {
1664*4882a593Smuzhiyun case BAD_COMMAND:
1665*4882a593Smuzhiyun res = -EINVAL;
1666*4882a593Smuzhiyun msg = "bad command";
1667*4882a593Smuzhiyun break;
1668*4882a593Smuzhiyun case COMMAND_IN_PROGRESS:
1669*4882a593Smuzhiyun res = -ETIMEDOUT;
1670*4882a593Smuzhiyun msg = "command in progress";
1671*4882a593Smuzhiyun break;
1672*4882a593Smuzhiyun case COMMAND_PASSED_TEST:
1673*4882a593Smuzhiyun res = 0;
1674*4882a593Smuzhiyun msg = "command passed test";
1675*4882a593Smuzhiyun break;
1676*4882a593Smuzhiyun case COMMAND_FAILED_TEST:
1677*4882a593Smuzhiyun res = -EIO;
1678*4882a593Smuzhiyun msg = "command failed test";
1679*4882a593Smuzhiyun break;
1680*4882a593Smuzhiyun case COMMAND_READ_DATA_OK:
1681*4882a593Smuzhiyun res = 0;
1682*4882a593Smuzhiyun msg = "command read data ok";
1683*4882a593Smuzhiyun break;
1684*4882a593Smuzhiyun case COMMAND_READ_BAD_ADDRESS:
1685*4882a593Smuzhiyun res = -EINVAL;
1686*4882a593Smuzhiyun msg = "command read bad address";
1687*4882a593Smuzhiyun break;
1688*4882a593Smuzhiyun case COMMAND_WRITE_DATA_OK:
1689*4882a593Smuzhiyun res = 0;
1690*4882a593Smuzhiyun msg = "command write data ok";
1691*4882a593Smuzhiyun break;
1692*4882a593Smuzhiyun case COMMAND_WRITE_BAD_ADDRESS:
1693*4882a593Smuzhiyun res = -EINVAL;
1694*4882a593Smuzhiyun msg = "command write bad address";
1695*4882a593Smuzhiyun break;
1696*4882a593Smuzhiyun case COMMAND_WRITE_FLASH_FAILURE:
1697*4882a593Smuzhiyun res = -EIO;
1698*4882a593Smuzhiyun msg = "command write flash failure";
1699*4882a593Smuzhiyun break;
1700*4882a593Smuzhiyun case COMMAND_COMPLETE:
1701*4882a593Smuzhiyun res = 0;
1702*4882a593Smuzhiyun msg = "command complete";
1703*4882a593Smuzhiyun break;
1704*4882a593Smuzhiyun case COMMAND_FLASH_ERASE_FAILURE:
1705*4882a593Smuzhiyun res = -EIO;
1706*4882a593Smuzhiyun msg = "command flash erase failure";
1707*4882a593Smuzhiyun break;
1708*4882a593Smuzhiyun case COMMAND_WRITE_BAD_DATA:
1709*4882a593Smuzhiyun res = -EINVAL;
1710*4882a593Smuzhiyun msg = "command write bad data";
1711*4882a593Smuzhiyun break;
1712*4882a593Smuzhiyun default:
1713*4882a593Smuzhiyun res = -EINVAL;
1714*4882a593Smuzhiyun msg = "unknown error";
1715*4882a593Smuzhiyun PRINTD (DBG_LOAD|DBG_ERR,
1716*4882a593Smuzhiyun "decode_loader_result got %d=%x !",
1717*4882a593Smuzhiyun result, result);
1718*4882a593Smuzhiyun break;
1719*4882a593Smuzhiyun }
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun PRINTK (KERN_ERR, "%s", msg);
1722*4882a593Smuzhiyun return res;
1723*4882a593Smuzhiyun }
1724*4882a593Smuzhiyun
do_loader_command(volatile loader_block * lb,const amb_dev * dev,loader_command cmd)1725*4882a593Smuzhiyun static int do_loader_command(volatile loader_block *lb, const amb_dev *dev,
1726*4882a593Smuzhiyun loader_command cmd)
1727*4882a593Smuzhiyun {
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun unsigned long timeout;
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "do_loader_command");
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun /* do a command
1734*4882a593Smuzhiyun
1735*4882a593Smuzhiyun Set the return value to zero, set the command type and set the
1736*4882a593Smuzhiyun valid entry to the right magic value. The payload is already
1737*4882a593Smuzhiyun correctly byte-ordered so we leave it alone. Hit the doorbell
1738*4882a593Smuzhiyun with the bus address of this structure.
1739*4882a593Smuzhiyun
1740*4882a593Smuzhiyun */
1741*4882a593Smuzhiyun
1742*4882a593Smuzhiyun lb->result = 0;
1743*4882a593Smuzhiyun lb->command = cpu_to_be32 (cmd);
1744*4882a593Smuzhiyun lb->valid = cpu_to_be32 (DMA_VALID);
1745*4882a593Smuzhiyun // dump_registers (dev);
1746*4882a593Smuzhiyun // dump_loader_block (lb);
1747*4882a593Smuzhiyun wr_mem (dev, offsetof(amb_mem, doorbell), virt_to_bus (lb) & ~onegigmask);
1748*4882a593Smuzhiyun
1749*4882a593Smuzhiyun timeout = command_timeouts[cmd] * 10;
1750*4882a593Smuzhiyun
1751*4882a593Smuzhiyun while (!lb->result || lb->result == cpu_to_be32 (COMMAND_IN_PROGRESS))
1752*4882a593Smuzhiyun if (timeout) {
1753*4882a593Smuzhiyun timeout = msleep_interruptible(timeout);
1754*4882a593Smuzhiyun } else {
1755*4882a593Smuzhiyun PRINTD (DBG_LOAD|DBG_ERR, "command %d timed out", cmd);
1756*4882a593Smuzhiyun dump_registers (dev);
1757*4882a593Smuzhiyun dump_loader_block (lb);
1758*4882a593Smuzhiyun return -ETIMEDOUT;
1759*4882a593Smuzhiyun }
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun if (cmd == adapter_start) {
1762*4882a593Smuzhiyun // wait for start command to acknowledge...
1763*4882a593Smuzhiyun timeout = 100;
1764*4882a593Smuzhiyun while (rd_plain (dev, offsetof(amb_mem, doorbell)))
1765*4882a593Smuzhiyun if (timeout) {
1766*4882a593Smuzhiyun timeout = msleep_interruptible(timeout);
1767*4882a593Smuzhiyun } else {
1768*4882a593Smuzhiyun PRINTD (DBG_LOAD|DBG_ERR, "start command did not clear doorbell, res=%08x",
1769*4882a593Smuzhiyun be32_to_cpu (lb->result));
1770*4882a593Smuzhiyun dump_registers (dev);
1771*4882a593Smuzhiyun return -ETIMEDOUT;
1772*4882a593Smuzhiyun }
1773*4882a593Smuzhiyun return 0;
1774*4882a593Smuzhiyun } else {
1775*4882a593Smuzhiyun return decode_loader_result (cmd, be32_to_cpu (lb->result));
1776*4882a593Smuzhiyun }
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun }
1779*4882a593Smuzhiyun
1780*4882a593Smuzhiyun /* loader: determine loader version */
1781*4882a593Smuzhiyun
get_loader_version(loader_block * lb,const amb_dev * dev,u32 * version)1782*4882a593Smuzhiyun static int get_loader_version(loader_block *lb, const amb_dev *dev,
1783*4882a593Smuzhiyun u32 *version)
1784*4882a593Smuzhiyun {
1785*4882a593Smuzhiyun int res;
1786*4882a593Smuzhiyun
1787*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "get_loader_version");
1788*4882a593Smuzhiyun
1789*4882a593Smuzhiyun res = do_loader_command (lb, dev, get_version_number);
1790*4882a593Smuzhiyun if (res)
1791*4882a593Smuzhiyun return res;
1792*4882a593Smuzhiyun if (version)
1793*4882a593Smuzhiyun *version = be32_to_cpu (lb->payload.version);
1794*4882a593Smuzhiyun return 0;
1795*4882a593Smuzhiyun }
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun /* loader: write memory data blocks */
1798*4882a593Smuzhiyun
loader_write(loader_block * lb,const amb_dev * dev,const struct ihex_binrec * rec)1799*4882a593Smuzhiyun static int loader_write(loader_block *lb, const amb_dev *dev,
1800*4882a593Smuzhiyun const struct ihex_binrec *rec)
1801*4882a593Smuzhiyun {
1802*4882a593Smuzhiyun transfer_block * tb = &lb->payload.transfer;
1803*4882a593Smuzhiyun
1804*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "loader_write");
1805*4882a593Smuzhiyun
1806*4882a593Smuzhiyun tb->address = rec->addr;
1807*4882a593Smuzhiyun tb->count = cpu_to_be32(be16_to_cpu(rec->len) / 4);
1808*4882a593Smuzhiyun memcpy(tb->data, rec->data, be16_to_cpu(rec->len));
1809*4882a593Smuzhiyun return do_loader_command (lb, dev, write_adapter_memory);
1810*4882a593Smuzhiyun }
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun /* loader: verify memory data blocks */
1813*4882a593Smuzhiyun
loader_verify(loader_block * lb,const amb_dev * dev,const struct ihex_binrec * rec)1814*4882a593Smuzhiyun static int loader_verify(loader_block *lb, const amb_dev *dev,
1815*4882a593Smuzhiyun const struct ihex_binrec *rec)
1816*4882a593Smuzhiyun {
1817*4882a593Smuzhiyun transfer_block * tb = &lb->payload.transfer;
1818*4882a593Smuzhiyun int res;
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "loader_verify");
1821*4882a593Smuzhiyun
1822*4882a593Smuzhiyun tb->address = rec->addr;
1823*4882a593Smuzhiyun tb->count = cpu_to_be32(be16_to_cpu(rec->len) / 4);
1824*4882a593Smuzhiyun res = do_loader_command (lb, dev, read_adapter_memory);
1825*4882a593Smuzhiyun if (!res && memcmp(tb->data, rec->data, be16_to_cpu(rec->len)))
1826*4882a593Smuzhiyun res = -EINVAL;
1827*4882a593Smuzhiyun return res;
1828*4882a593Smuzhiyun }
1829*4882a593Smuzhiyun
1830*4882a593Smuzhiyun /* loader: start microcode */
1831*4882a593Smuzhiyun
loader_start(loader_block * lb,const amb_dev * dev,u32 address)1832*4882a593Smuzhiyun static int loader_start(loader_block *lb, const amb_dev *dev, u32 address)
1833*4882a593Smuzhiyun {
1834*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "loader_start");
1835*4882a593Smuzhiyun
1836*4882a593Smuzhiyun lb->payload.start = cpu_to_be32 (address);
1837*4882a593Smuzhiyun return do_loader_command (lb, dev, adapter_start);
1838*4882a593Smuzhiyun }
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun /********** reset card **********/
1841*4882a593Smuzhiyun
sf(const char * msg)1842*4882a593Smuzhiyun static inline void sf (const char * msg)
1843*4882a593Smuzhiyun {
1844*4882a593Smuzhiyun PRINTK (KERN_ERR, "self-test failed: %s", msg);
1845*4882a593Smuzhiyun }
1846*4882a593Smuzhiyun
amb_reset(amb_dev * dev,int diags)1847*4882a593Smuzhiyun static int amb_reset (amb_dev * dev, int diags) {
1848*4882a593Smuzhiyun u32 word;
1849*4882a593Smuzhiyun
1850*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "amb_reset");
1851*4882a593Smuzhiyun
1852*4882a593Smuzhiyun word = rd_plain (dev, offsetof(amb_mem, reset_control));
1853*4882a593Smuzhiyun // put card into reset state
1854*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, reset_control), word | AMB_RESET_BITS);
1855*4882a593Smuzhiyun // wait a short while
1856*4882a593Smuzhiyun udelay (10);
1857*4882a593Smuzhiyun #if 1
1858*4882a593Smuzhiyun // put card into known good state
1859*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, interrupt_control), AMB_DOORBELL_BITS);
1860*4882a593Smuzhiyun // clear all interrupts just in case
1861*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, interrupt), -1);
1862*4882a593Smuzhiyun #endif
1863*4882a593Smuzhiyun // clear self-test done flag
1864*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, mb.loader.ready), 0);
1865*4882a593Smuzhiyun // take card out of reset state
1866*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, reset_control), word &~ AMB_RESET_BITS);
1867*4882a593Smuzhiyun
1868*4882a593Smuzhiyun if (diags) {
1869*4882a593Smuzhiyun unsigned long timeout;
1870*4882a593Smuzhiyun // 4.2 second wait
1871*4882a593Smuzhiyun msleep(4200);
1872*4882a593Smuzhiyun // half second time-out
1873*4882a593Smuzhiyun timeout = 500;
1874*4882a593Smuzhiyun while (!rd_plain (dev, offsetof(amb_mem, mb.loader.ready)))
1875*4882a593Smuzhiyun if (timeout) {
1876*4882a593Smuzhiyun timeout = msleep_interruptible(timeout);
1877*4882a593Smuzhiyun } else {
1878*4882a593Smuzhiyun PRINTD (DBG_LOAD|DBG_ERR, "reset timed out");
1879*4882a593Smuzhiyun return -ETIMEDOUT;
1880*4882a593Smuzhiyun }
1881*4882a593Smuzhiyun
1882*4882a593Smuzhiyun // get results of self-test
1883*4882a593Smuzhiyun // XXX double check byte-order
1884*4882a593Smuzhiyun word = rd_mem (dev, offsetof(amb_mem, mb.loader.result));
1885*4882a593Smuzhiyun if (word & SELF_TEST_FAILURE) {
1886*4882a593Smuzhiyun if (word & GPINT_TST_FAILURE)
1887*4882a593Smuzhiyun sf ("interrupt");
1888*4882a593Smuzhiyun if (word & SUNI_DATA_PATTERN_FAILURE)
1889*4882a593Smuzhiyun sf ("SUNI data pattern");
1890*4882a593Smuzhiyun if (word & SUNI_DATA_BITS_FAILURE)
1891*4882a593Smuzhiyun sf ("SUNI data bits");
1892*4882a593Smuzhiyun if (word & SUNI_UTOPIA_FAILURE)
1893*4882a593Smuzhiyun sf ("SUNI UTOPIA interface");
1894*4882a593Smuzhiyun if (word & SUNI_FIFO_FAILURE)
1895*4882a593Smuzhiyun sf ("SUNI cell buffer FIFO");
1896*4882a593Smuzhiyun if (word & SRAM_FAILURE)
1897*4882a593Smuzhiyun sf ("bad SRAM");
1898*4882a593Smuzhiyun // better return value?
1899*4882a593Smuzhiyun return -EIO;
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun
1902*4882a593Smuzhiyun }
1903*4882a593Smuzhiyun return 0;
1904*4882a593Smuzhiyun }
1905*4882a593Smuzhiyun
1906*4882a593Smuzhiyun /********** transfer and start the microcode **********/
1907*4882a593Smuzhiyun
ucode_init(loader_block * lb,amb_dev * dev)1908*4882a593Smuzhiyun static int ucode_init(loader_block *lb, amb_dev *dev)
1909*4882a593Smuzhiyun {
1910*4882a593Smuzhiyun const struct firmware *fw;
1911*4882a593Smuzhiyun unsigned long start_address;
1912*4882a593Smuzhiyun const struct ihex_binrec *rec;
1913*4882a593Smuzhiyun const char *errmsg = NULL;
1914*4882a593Smuzhiyun int res;
1915*4882a593Smuzhiyun
1916*4882a593Smuzhiyun res = request_ihex_firmware(&fw, "atmsar11.fw", &dev->pci_dev->dev);
1917*4882a593Smuzhiyun if (res) {
1918*4882a593Smuzhiyun PRINTK (KERN_ERR, "Cannot load microcode data");
1919*4882a593Smuzhiyun return res;
1920*4882a593Smuzhiyun }
1921*4882a593Smuzhiyun
1922*4882a593Smuzhiyun /* First record contains just the start address */
1923*4882a593Smuzhiyun rec = (const struct ihex_binrec *)fw->data;
1924*4882a593Smuzhiyun if (be16_to_cpu(rec->len) != sizeof(__be32) || be32_to_cpu(rec->addr)) {
1925*4882a593Smuzhiyun errmsg = "no start record";
1926*4882a593Smuzhiyun goto fail;
1927*4882a593Smuzhiyun }
1928*4882a593Smuzhiyun start_address = be32_to_cpup((__be32 *)rec->data);
1929*4882a593Smuzhiyun
1930*4882a593Smuzhiyun rec = ihex_next_binrec(rec);
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_LOAD, "ucode_init");
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun while (rec) {
1935*4882a593Smuzhiyun PRINTD (DBG_LOAD, "starting region (%x, %u)", be32_to_cpu(rec->addr),
1936*4882a593Smuzhiyun be16_to_cpu(rec->len));
1937*4882a593Smuzhiyun if (be16_to_cpu(rec->len) > 4 * MAX_TRANSFER_DATA) {
1938*4882a593Smuzhiyun errmsg = "record too long";
1939*4882a593Smuzhiyun goto fail;
1940*4882a593Smuzhiyun }
1941*4882a593Smuzhiyun if (be16_to_cpu(rec->len) & 3) {
1942*4882a593Smuzhiyun errmsg = "odd number of bytes";
1943*4882a593Smuzhiyun goto fail;
1944*4882a593Smuzhiyun }
1945*4882a593Smuzhiyun res = loader_write(lb, dev, rec);
1946*4882a593Smuzhiyun if (res)
1947*4882a593Smuzhiyun break;
1948*4882a593Smuzhiyun
1949*4882a593Smuzhiyun res = loader_verify(lb, dev, rec);
1950*4882a593Smuzhiyun if (res)
1951*4882a593Smuzhiyun break;
1952*4882a593Smuzhiyun rec = ihex_next_binrec(rec);
1953*4882a593Smuzhiyun }
1954*4882a593Smuzhiyun release_firmware(fw);
1955*4882a593Smuzhiyun if (!res)
1956*4882a593Smuzhiyun res = loader_start(lb, dev, start_address);
1957*4882a593Smuzhiyun
1958*4882a593Smuzhiyun return res;
1959*4882a593Smuzhiyun fail:
1960*4882a593Smuzhiyun release_firmware(fw);
1961*4882a593Smuzhiyun PRINTK(KERN_ERR, "Bad microcode data (%s)", errmsg);
1962*4882a593Smuzhiyun return -EINVAL;
1963*4882a593Smuzhiyun }
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun /********** give adapter parameters **********/
1966*4882a593Smuzhiyun
bus_addr(void * addr)1967*4882a593Smuzhiyun static inline __be32 bus_addr(void * addr) {
1968*4882a593Smuzhiyun return cpu_to_be32 (virt_to_bus (addr));
1969*4882a593Smuzhiyun }
1970*4882a593Smuzhiyun
amb_talk(amb_dev * dev)1971*4882a593Smuzhiyun static int amb_talk(amb_dev *dev)
1972*4882a593Smuzhiyun {
1973*4882a593Smuzhiyun adap_talk_block a;
1974*4882a593Smuzhiyun unsigned char pool;
1975*4882a593Smuzhiyun unsigned long timeout;
1976*4882a593Smuzhiyun
1977*4882a593Smuzhiyun PRINTD (DBG_FLOW, "amb_talk %p", dev);
1978*4882a593Smuzhiyun
1979*4882a593Smuzhiyun a.command_start = bus_addr (dev->cq.ptrs.start);
1980*4882a593Smuzhiyun a.command_end = bus_addr (dev->cq.ptrs.limit);
1981*4882a593Smuzhiyun a.tx_start = bus_addr (dev->txq.in.start);
1982*4882a593Smuzhiyun a.tx_end = bus_addr (dev->txq.in.limit);
1983*4882a593Smuzhiyun a.txcom_start = bus_addr (dev->txq.out.start);
1984*4882a593Smuzhiyun a.txcom_end = bus_addr (dev->txq.out.limit);
1985*4882a593Smuzhiyun
1986*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
1987*4882a593Smuzhiyun // the other "a" items are set up by the adapter
1988*4882a593Smuzhiyun a.rec_struct[pool].buffer_start = bus_addr (dev->rxq[pool].in.start);
1989*4882a593Smuzhiyun a.rec_struct[pool].buffer_end = bus_addr (dev->rxq[pool].in.limit);
1990*4882a593Smuzhiyun a.rec_struct[pool].rx_start = bus_addr (dev->rxq[pool].out.start);
1991*4882a593Smuzhiyun a.rec_struct[pool].rx_end = bus_addr (dev->rxq[pool].out.limit);
1992*4882a593Smuzhiyun a.rec_struct[pool].buffer_size = cpu_to_be32 (dev->rxq[pool].buffer_size);
1993*4882a593Smuzhiyun }
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun #ifdef AMB_NEW_MICROCODE
1996*4882a593Smuzhiyun // disable fast PLX prefetching
1997*4882a593Smuzhiyun a.init_flags = 0;
1998*4882a593Smuzhiyun #endif
1999*4882a593Smuzhiyun
2000*4882a593Smuzhiyun // pass the structure
2001*4882a593Smuzhiyun wr_mem (dev, offsetof(amb_mem, doorbell), virt_to_bus (&a));
2002*4882a593Smuzhiyun
2003*4882a593Smuzhiyun // 2.2 second wait (must not touch doorbell during 2 second DMA test)
2004*4882a593Smuzhiyun msleep(2200);
2005*4882a593Smuzhiyun // give the adapter another half second?
2006*4882a593Smuzhiyun timeout = 500;
2007*4882a593Smuzhiyun while (rd_plain (dev, offsetof(amb_mem, doorbell)))
2008*4882a593Smuzhiyun if (timeout) {
2009*4882a593Smuzhiyun timeout = msleep_interruptible(timeout);
2010*4882a593Smuzhiyun } else {
2011*4882a593Smuzhiyun PRINTD (DBG_INIT|DBG_ERR, "adapter init timed out");
2012*4882a593Smuzhiyun return -ETIMEDOUT;
2013*4882a593Smuzhiyun }
2014*4882a593Smuzhiyun
2015*4882a593Smuzhiyun return 0;
2016*4882a593Smuzhiyun }
2017*4882a593Smuzhiyun
2018*4882a593Smuzhiyun // get microcode version
amb_ucode_version(amb_dev * dev)2019*4882a593Smuzhiyun static void amb_ucode_version(amb_dev *dev)
2020*4882a593Smuzhiyun {
2021*4882a593Smuzhiyun u32 major;
2022*4882a593Smuzhiyun u32 minor;
2023*4882a593Smuzhiyun command cmd;
2024*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_GET_VERSION);
2025*4882a593Smuzhiyun while (command_do (dev, &cmd)) {
2026*4882a593Smuzhiyun set_current_state(TASK_UNINTERRUPTIBLE);
2027*4882a593Smuzhiyun schedule();
2028*4882a593Smuzhiyun }
2029*4882a593Smuzhiyun major = be32_to_cpu (cmd.args.version.major);
2030*4882a593Smuzhiyun minor = be32_to_cpu (cmd.args.version.minor);
2031*4882a593Smuzhiyun PRINTK (KERN_INFO, "microcode version is %u.%u", major, minor);
2032*4882a593Smuzhiyun }
2033*4882a593Smuzhiyun
2034*4882a593Smuzhiyun // get end station address
amb_esi(amb_dev * dev,u8 * esi)2035*4882a593Smuzhiyun static void amb_esi(amb_dev *dev, u8 *esi)
2036*4882a593Smuzhiyun {
2037*4882a593Smuzhiyun u32 lower4;
2038*4882a593Smuzhiyun u16 upper2;
2039*4882a593Smuzhiyun command cmd;
2040*4882a593Smuzhiyun
2041*4882a593Smuzhiyun cmd.request = cpu_to_be32 (SRB_GET_BIA);
2042*4882a593Smuzhiyun while (command_do (dev, &cmd)) {
2043*4882a593Smuzhiyun set_current_state(TASK_UNINTERRUPTIBLE);
2044*4882a593Smuzhiyun schedule();
2045*4882a593Smuzhiyun }
2046*4882a593Smuzhiyun lower4 = be32_to_cpu (cmd.args.bia.lower4);
2047*4882a593Smuzhiyun upper2 = be32_to_cpu (cmd.args.bia.upper2);
2048*4882a593Smuzhiyun PRINTD (DBG_LOAD, "BIA: lower4: %08x, upper2 %04x", lower4, upper2);
2049*4882a593Smuzhiyun
2050*4882a593Smuzhiyun if (esi) {
2051*4882a593Smuzhiyun unsigned int i;
2052*4882a593Smuzhiyun
2053*4882a593Smuzhiyun PRINTDB (DBG_INIT, "ESI:");
2054*4882a593Smuzhiyun for (i = 0; i < ESI_LEN; ++i) {
2055*4882a593Smuzhiyun if (i < 4)
2056*4882a593Smuzhiyun esi[i] = bitrev8(lower4>>(8*i));
2057*4882a593Smuzhiyun else
2058*4882a593Smuzhiyun esi[i] = bitrev8(upper2>>(8*(i-4)));
2059*4882a593Smuzhiyun PRINTDM (DBG_INIT, " %02x", esi[i]);
2060*4882a593Smuzhiyun }
2061*4882a593Smuzhiyun
2062*4882a593Smuzhiyun PRINTDE (DBG_INIT, "");
2063*4882a593Smuzhiyun }
2064*4882a593Smuzhiyun
2065*4882a593Smuzhiyun return;
2066*4882a593Smuzhiyun }
2067*4882a593Smuzhiyun
fixup_plx_window(amb_dev * dev,loader_block * lb)2068*4882a593Smuzhiyun static void fixup_plx_window (amb_dev *dev, loader_block *lb)
2069*4882a593Smuzhiyun {
2070*4882a593Smuzhiyun // fix up the PLX-mapped window base address to match the block
2071*4882a593Smuzhiyun unsigned long blb;
2072*4882a593Smuzhiyun u32 mapreg;
2073*4882a593Smuzhiyun blb = virt_to_bus(lb);
2074*4882a593Smuzhiyun // the kernel stack had better not ever cross a 1Gb boundary!
2075*4882a593Smuzhiyun mapreg = rd_plain (dev, offsetof(amb_mem, stuff[10]));
2076*4882a593Smuzhiyun mapreg &= ~onegigmask;
2077*4882a593Smuzhiyun mapreg |= blb & onegigmask;
2078*4882a593Smuzhiyun wr_plain (dev, offsetof(amb_mem, stuff[10]), mapreg);
2079*4882a593Smuzhiyun return;
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun
amb_init(amb_dev * dev)2082*4882a593Smuzhiyun static int amb_init(amb_dev *dev)
2083*4882a593Smuzhiyun {
2084*4882a593Smuzhiyun loader_block lb;
2085*4882a593Smuzhiyun
2086*4882a593Smuzhiyun u32 version;
2087*4882a593Smuzhiyun
2088*4882a593Smuzhiyun if (amb_reset (dev, 1)) {
2089*4882a593Smuzhiyun PRINTK (KERN_ERR, "card reset failed!");
2090*4882a593Smuzhiyun } else {
2091*4882a593Smuzhiyun fixup_plx_window (dev, &lb);
2092*4882a593Smuzhiyun
2093*4882a593Smuzhiyun if (get_loader_version (&lb, dev, &version)) {
2094*4882a593Smuzhiyun PRINTK (KERN_INFO, "failed to get loader version");
2095*4882a593Smuzhiyun } else {
2096*4882a593Smuzhiyun PRINTK (KERN_INFO, "loader version is %08x", version);
2097*4882a593Smuzhiyun
2098*4882a593Smuzhiyun if (ucode_init (&lb, dev)) {
2099*4882a593Smuzhiyun PRINTK (KERN_ERR, "microcode failure");
2100*4882a593Smuzhiyun } else if (create_queues (dev, cmds, txs, rxs, rxs_bs)) {
2101*4882a593Smuzhiyun PRINTK (KERN_ERR, "failed to get memory for queues");
2102*4882a593Smuzhiyun } else {
2103*4882a593Smuzhiyun
2104*4882a593Smuzhiyun if (amb_talk (dev)) {
2105*4882a593Smuzhiyun PRINTK (KERN_ERR, "adapter did not accept queues");
2106*4882a593Smuzhiyun } else {
2107*4882a593Smuzhiyun
2108*4882a593Smuzhiyun amb_ucode_version (dev);
2109*4882a593Smuzhiyun return 0;
2110*4882a593Smuzhiyun
2111*4882a593Smuzhiyun } /* amb_talk */
2112*4882a593Smuzhiyun
2113*4882a593Smuzhiyun destroy_queues (dev);
2114*4882a593Smuzhiyun } /* create_queues, ucode_init */
2115*4882a593Smuzhiyun
2116*4882a593Smuzhiyun amb_reset (dev, 0);
2117*4882a593Smuzhiyun } /* get_loader_version */
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun } /* amb_reset */
2120*4882a593Smuzhiyun
2121*4882a593Smuzhiyun return -EINVAL;
2122*4882a593Smuzhiyun }
2123*4882a593Smuzhiyun
setup_dev(amb_dev * dev,struct pci_dev * pci_dev)2124*4882a593Smuzhiyun static void setup_dev(amb_dev *dev, struct pci_dev *pci_dev)
2125*4882a593Smuzhiyun {
2126*4882a593Smuzhiyun unsigned char pool;
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun // set up known dev items straight away
2129*4882a593Smuzhiyun dev->pci_dev = pci_dev;
2130*4882a593Smuzhiyun pci_set_drvdata(pci_dev, dev);
2131*4882a593Smuzhiyun
2132*4882a593Smuzhiyun dev->iobase = pci_resource_start (pci_dev, 1);
2133*4882a593Smuzhiyun dev->irq = pci_dev->irq;
2134*4882a593Smuzhiyun dev->membase = bus_to_virt(pci_resource_start(pci_dev, 0));
2135*4882a593Smuzhiyun
2136*4882a593Smuzhiyun // flags (currently only dead)
2137*4882a593Smuzhiyun dev->flags = 0;
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun // Allocate cell rates (fibre)
2140*4882a593Smuzhiyun // ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2141*4882a593Smuzhiyun // to be really pedantic, this should be ATM_OC3c_PCR
2142*4882a593Smuzhiyun dev->tx_avail = ATM_OC3_PCR;
2143*4882a593Smuzhiyun dev->rx_avail = ATM_OC3_PCR;
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun // semaphore for txer/rxer modifications - we cannot use a
2146*4882a593Smuzhiyun // spinlock as the critical region needs to switch processes
2147*4882a593Smuzhiyun mutex_init(&dev->vcc_sf);
2148*4882a593Smuzhiyun // queue manipulation spinlocks; we want atomic reads and
2149*4882a593Smuzhiyun // writes to the queue descriptors (handles IRQ and SMP)
2150*4882a593Smuzhiyun // consider replacing "int pending" -> "atomic_t available"
2151*4882a593Smuzhiyun // => problem related to who gets to move queue pointers
2152*4882a593Smuzhiyun spin_lock_init (&dev->cq.lock);
2153*4882a593Smuzhiyun spin_lock_init (&dev->txq.lock);
2154*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
2155*4882a593Smuzhiyun spin_lock_init (&dev->rxq[pool].lock);
2156*4882a593Smuzhiyun }
2157*4882a593Smuzhiyun
setup_pci_dev(struct pci_dev * pci_dev)2158*4882a593Smuzhiyun static void setup_pci_dev(struct pci_dev *pci_dev)
2159*4882a593Smuzhiyun {
2160*4882a593Smuzhiyun unsigned char lat;
2161*4882a593Smuzhiyun
2162*4882a593Smuzhiyun // enable bus master accesses
2163*4882a593Smuzhiyun pci_set_master(pci_dev);
2164*4882a593Smuzhiyun
2165*4882a593Smuzhiyun // frobnicate latency (upwards, usually)
2166*4882a593Smuzhiyun pci_read_config_byte (pci_dev, PCI_LATENCY_TIMER, &lat);
2167*4882a593Smuzhiyun
2168*4882a593Smuzhiyun if (!pci_lat)
2169*4882a593Smuzhiyun pci_lat = (lat < MIN_PCI_LATENCY) ? MIN_PCI_LATENCY : lat;
2170*4882a593Smuzhiyun
2171*4882a593Smuzhiyun if (lat != pci_lat) {
2172*4882a593Smuzhiyun PRINTK (KERN_INFO, "Changing PCI latency timer from %hu to %hu",
2173*4882a593Smuzhiyun lat, pci_lat);
2174*4882a593Smuzhiyun pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
2175*4882a593Smuzhiyun }
2176*4882a593Smuzhiyun }
2177*4882a593Smuzhiyun
amb_probe(struct pci_dev * pci_dev,const struct pci_device_id * pci_ent)2178*4882a593Smuzhiyun static int amb_probe(struct pci_dev *pci_dev,
2179*4882a593Smuzhiyun const struct pci_device_id *pci_ent)
2180*4882a593Smuzhiyun {
2181*4882a593Smuzhiyun amb_dev * dev;
2182*4882a593Smuzhiyun int err;
2183*4882a593Smuzhiyun unsigned int irq;
2184*4882a593Smuzhiyun
2185*4882a593Smuzhiyun err = pci_enable_device(pci_dev);
2186*4882a593Smuzhiyun if (err < 0) {
2187*4882a593Smuzhiyun PRINTK (KERN_ERR, "skipped broken (PLX rev 2) card");
2188*4882a593Smuzhiyun goto out;
2189*4882a593Smuzhiyun }
2190*4882a593Smuzhiyun
2191*4882a593Smuzhiyun // read resources from PCI configuration space
2192*4882a593Smuzhiyun irq = pci_dev->irq;
2193*4882a593Smuzhiyun
2194*4882a593Smuzhiyun if (pci_dev->device == PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD) {
2195*4882a593Smuzhiyun PRINTK (KERN_ERR, "skipped broken (PLX rev 2) card");
2196*4882a593Smuzhiyun err = -EINVAL;
2197*4882a593Smuzhiyun goto out_disable;
2198*4882a593Smuzhiyun }
2199*4882a593Smuzhiyun
2200*4882a593Smuzhiyun PRINTD (DBG_INFO, "found Madge ATM adapter (amb) at"
2201*4882a593Smuzhiyun " IO %llx, IRQ %u, MEM %p",
2202*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pci_dev, 1),
2203*4882a593Smuzhiyun irq, bus_to_virt(pci_resource_start(pci_dev, 0)));
2204*4882a593Smuzhiyun
2205*4882a593Smuzhiyun // check IO region
2206*4882a593Smuzhiyun err = pci_request_region(pci_dev, 1, DEV_LABEL);
2207*4882a593Smuzhiyun if (err < 0) {
2208*4882a593Smuzhiyun PRINTK (KERN_ERR, "IO range already in use!");
2209*4882a593Smuzhiyun goto out_disable;
2210*4882a593Smuzhiyun }
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun dev = kzalloc(sizeof(amb_dev), GFP_KERNEL);
2213*4882a593Smuzhiyun if (!dev) {
2214*4882a593Smuzhiyun PRINTK (KERN_ERR, "out of memory!");
2215*4882a593Smuzhiyun err = -ENOMEM;
2216*4882a593Smuzhiyun goto out_release;
2217*4882a593Smuzhiyun }
2218*4882a593Smuzhiyun
2219*4882a593Smuzhiyun setup_dev(dev, pci_dev);
2220*4882a593Smuzhiyun
2221*4882a593Smuzhiyun err = amb_init(dev);
2222*4882a593Smuzhiyun if (err < 0) {
2223*4882a593Smuzhiyun PRINTK (KERN_ERR, "adapter initialisation failure");
2224*4882a593Smuzhiyun goto out_free;
2225*4882a593Smuzhiyun }
2226*4882a593Smuzhiyun
2227*4882a593Smuzhiyun setup_pci_dev(pci_dev);
2228*4882a593Smuzhiyun
2229*4882a593Smuzhiyun // grab (but share) IRQ and install handler
2230*4882a593Smuzhiyun err = request_irq(irq, interrupt_handler, IRQF_SHARED, DEV_LABEL, dev);
2231*4882a593Smuzhiyun if (err < 0) {
2232*4882a593Smuzhiyun PRINTK (KERN_ERR, "request IRQ failed!");
2233*4882a593Smuzhiyun goto out_reset;
2234*4882a593Smuzhiyun }
2235*4882a593Smuzhiyun
2236*4882a593Smuzhiyun dev->atm_dev = atm_dev_register (DEV_LABEL, &pci_dev->dev, &amb_ops, -1,
2237*4882a593Smuzhiyun NULL);
2238*4882a593Smuzhiyun if (!dev->atm_dev) {
2239*4882a593Smuzhiyun PRINTD (DBG_ERR, "failed to register Madge ATM adapter");
2240*4882a593Smuzhiyun err = -EINVAL;
2241*4882a593Smuzhiyun goto out_free_irq;
2242*4882a593Smuzhiyun }
2243*4882a593Smuzhiyun
2244*4882a593Smuzhiyun PRINTD (DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2245*4882a593Smuzhiyun dev->atm_dev->number, dev, dev->atm_dev);
2246*4882a593Smuzhiyun dev->atm_dev->dev_data = (void *) dev;
2247*4882a593Smuzhiyun
2248*4882a593Smuzhiyun // register our address
2249*4882a593Smuzhiyun amb_esi (dev, dev->atm_dev->esi);
2250*4882a593Smuzhiyun
2251*4882a593Smuzhiyun // 0 bits for vpi, 10 bits for vci
2252*4882a593Smuzhiyun dev->atm_dev->ci_range.vpi_bits = NUM_VPI_BITS;
2253*4882a593Smuzhiyun dev->atm_dev->ci_range.vci_bits = NUM_VCI_BITS;
2254*4882a593Smuzhiyun
2255*4882a593Smuzhiyun timer_setup(&dev->housekeeping, do_housekeeping, 0);
2256*4882a593Smuzhiyun mod_timer(&dev->housekeeping, jiffies);
2257*4882a593Smuzhiyun
2258*4882a593Smuzhiyun // enable host interrupts
2259*4882a593Smuzhiyun interrupts_on (dev);
2260*4882a593Smuzhiyun
2261*4882a593Smuzhiyun out:
2262*4882a593Smuzhiyun return err;
2263*4882a593Smuzhiyun
2264*4882a593Smuzhiyun out_free_irq:
2265*4882a593Smuzhiyun free_irq(irq, dev);
2266*4882a593Smuzhiyun out_reset:
2267*4882a593Smuzhiyun amb_reset(dev, 0);
2268*4882a593Smuzhiyun out_free:
2269*4882a593Smuzhiyun kfree(dev);
2270*4882a593Smuzhiyun out_release:
2271*4882a593Smuzhiyun pci_release_region(pci_dev, 1);
2272*4882a593Smuzhiyun out_disable:
2273*4882a593Smuzhiyun pci_disable_device(pci_dev);
2274*4882a593Smuzhiyun goto out;
2275*4882a593Smuzhiyun }
2276*4882a593Smuzhiyun
2277*4882a593Smuzhiyun
amb_remove_one(struct pci_dev * pci_dev)2278*4882a593Smuzhiyun static void amb_remove_one(struct pci_dev *pci_dev)
2279*4882a593Smuzhiyun {
2280*4882a593Smuzhiyun struct amb_dev *dev;
2281*4882a593Smuzhiyun
2282*4882a593Smuzhiyun dev = pci_get_drvdata(pci_dev);
2283*4882a593Smuzhiyun
2284*4882a593Smuzhiyun PRINTD(DBG_INFO|DBG_INIT, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2285*4882a593Smuzhiyun del_timer_sync(&dev->housekeeping);
2286*4882a593Smuzhiyun // the drain should not be necessary
2287*4882a593Smuzhiyun drain_rx_pools(dev);
2288*4882a593Smuzhiyun interrupts_off(dev);
2289*4882a593Smuzhiyun amb_reset(dev, 0);
2290*4882a593Smuzhiyun free_irq(dev->irq, dev);
2291*4882a593Smuzhiyun pci_disable_device(pci_dev);
2292*4882a593Smuzhiyun destroy_queues(dev);
2293*4882a593Smuzhiyun atm_dev_deregister(dev->atm_dev);
2294*4882a593Smuzhiyun kfree(dev);
2295*4882a593Smuzhiyun pci_release_region(pci_dev, 1);
2296*4882a593Smuzhiyun }
2297*4882a593Smuzhiyun
amb_check_args(void)2298*4882a593Smuzhiyun static void __init amb_check_args (void) {
2299*4882a593Smuzhiyun unsigned char pool;
2300*4882a593Smuzhiyun unsigned int max_rx_size;
2301*4882a593Smuzhiyun
2302*4882a593Smuzhiyun #ifdef DEBUG_AMBASSADOR
2303*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2304*4882a593Smuzhiyun #else
2305*4882a593Smuzhiyun if (debug)
2306*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "no debugging support");
2307*4882a593Smuzhiyun #endif
2308*4882a593Smuzhiyun
2309*4882a593Smuzhiyun if (cmds < MIN_QUEUE_SIZE)
2310*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "cmds has been raised to %u",
2311*4882a593Smuzhiyun cmds = MIN_QUEUE_SIZE);
2312*4882a593Smuzhiyun
2313*4882a593Smuzhiyun if (txs < MIN_QUEUE_SIZE)
2314*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "txs has been raised to %u",
2315*4882a593Smuzhiyun txs = MIN_QUEUE_SIZE);
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
2318*4882a593Smuzhiyun if (rxs[pool] < MIN_QUEUE_SIZE)
2319*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "rxs[%hu] has been raised to %u",
2320*4882a593Smuzhiyun pool, rxs[pool] = MIN_QUEUE_SIZE);
2321*4882a593Smuzhiyun
2322*4882a593Smuzhiyun // buffers sizes should be greater than zero and strictly increasing
2323*4882a593Smuzhiyun max_rx_size = 0;
2324*4882a593Smuzhiyun for (pool = 0; pool < NUM_RX_POOLS; ++pool)
2325*4882a593Smuzhiyun if (rxs_bs[pool] <= max_rx_size)
2326*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "useless pool (rxs_bs[%hu] = %u)",
2327*4882a593Smuzhiyun pool, rxs_bs[pool]);
2328*4882a593Smuzhiyun else
2329*4882a593Smuzhiyun max_rx_size = rxs_bs[pool];
2330*4882a593Smuzhiyun
2331*4882a593Smuzhiyun if (rx_lats < MIN_RX_BUFFERS)
2332*4882a593Smuzhiyun PRINTK (KERN_NOTICE, "rx_lats has been raised to %u",
2333*4882a593Smuzhiyun rx_lats = MIN_RX_BUFFERS);
2334*4882a593Smuzhiyun
2335*4882a593Smuzhiyun return;
2336*4882a593Smuzhiyun }
2337*4882a593Smuzhiyun
2338*4882a593Smuzhiyun /********** module stuff **********/
2339*4882a593Smuzhiyun
2340*4882a593Smuzhiyun MODULE_AUTHOR(maintainer_string);
2341*4882a593Smuzhiyun MODULE_DESCRIPTION(description_string);
2342*4882a593Smuzhiyun MODULE_LICENSE("GPL");
2343*4882a593Smuzhiyun MODULE_FIRMWARE("atmsar11.fw");
2344*4882a593Smuzhiyun module_param(debug, ushort, 0644);
2345*4882a593Smuzhiyun module_param(cmds, uint, 0);
2346*4882a593Smuzhiyun module_param(txs, uint, 0);
2347*4882a593Smuzhiyun module_param_array(rxs, uint, NULL, 0);
2348*4882a593Smuzhiyun module_param_array(rxs_bs, uint, NULL, 0);
2349*4882a593Smuzhiyun module_param(rx_lats, uint, 0);
2350*4882a593Smuzhiyun module_param(pci_lat, byte, 0);
2351*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2352*4882a593Smuzhiyun MODULE_PARM_DESC(cmds, "number of command queue entries");
2353*4882a593Smuzhiyun MODULE_PARM_DESC(txs, "number of TX queue entries");
2354*4882a593Smuzhiyun MODULE_PARM_DESC(rxs, "number of RX queue entries [" __MODULE_STRING(NUM_RX_POOLS) "]");
2355*4882a593Smuzhiyun MODULE_PARM_DESC(rxs_bs, "size of RX buffers [" __MODULE_STRING(NUM_RX_POOLS) "]");
2356*4882a593Smuzhiyun MODULE_PARM_DESC(rx_lats, "number of extra buffers to cope with RX latencies");
2357*4882a593Smuzhiyun MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2358*4882a593Smuzhiyun
2359*4882a593Smuzhiyun /********** module entry **********/
2360*4882a593Smuzhiyun
2361*4882a593Smuzhiyun static const struct pci_device_id amb_pci_tbl[] = {
2362*4882a593Smuzhiyun { PCI_VDEVICE(MADGE, PCI_DEVICE_ID_MADGE_AMBASSADOR), 0 },
2363*4882a593Smuzhiyun { PCI_VDEVICE(MADGE, PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD), 0 },
2364*4882a593Smuzhiyun { 0, }
2365*4882a593Smuzhiyun };
2366*4882a593Smuzhiyun
2367*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, amb_pci_tbl);
2368*4882a593Smuzhiyun
2369*4882a593Smuzhiyun static struct pci_driver amb_driver = {
2370*4882a593Smuzhiyun .name = "amb",
2371*4882a593Smuzhiyun .probe = amb_probe,
2372*4882a593Smuzhiyun .remove = amb_remove_one,
2373*4882a593Smuzhiyun .id_table = amb_pci_tbl,
2374*4882a593Smuzhiyun };
2375*4882a593Smuzhiyun
amb_module_init(void)2376*4882a593Smuzhiyun static int __init amb_module_init (void)
2377*4882a593Smuzhiyun {
2378*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_INIT, "init_module");
2379*4882a593Smuzhiyun
2380*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(amb_mem) != 4*16 + 4*12);
2381*4882a593Smuzhiyun
2382*4882a593Smuzhiyun show_version();
2383*4882a593Smuzhiyun
2384*4882a593Smuzhiyun amb_check_args();
2385*4882a593Smuzhiyun
2386*4882a593Smuzhiyun // get the juice
2387*4882a593Smuzhiyun return pci_register_driver(&amb_driver);
2388*4882a593Smuzhiyun }
2389*4882a593Smuzhiyun
2390*4882a593Smuzhiyun /********** module exit **********/
2391*4882a593Smuzhiyun
amb_module_exit(void)2392*4882a593Smuzhiyun static void __exit amb_module_exit (void)
2393*4882a593Smuzhiyun {
2394*4882a593Smuzhiyun PRINTD (DBG_FLOW|DBG_INIT, "cleanup_module");
2395*4882a593Smuzhiyun
2396*4882a593Smuzhiyun pci_unregister_driver(&amb_driver);
2397*4882a593Smuzhiyun }
2398*4882a593Smuzhiyun
2399*4882a593Smuzhiyun module_init(amb_module_init);
2400*4882a593Smuzhiyun module_exit(amb_module_exit);
2401