1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * sata_uli.c - ULi Electronics SATA
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * libata documentation is available via 'make {ps|pdf}docs',
6*4882a593Smuzhiyun * as Documentation/driver-api/libata.rst
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Hardware documentation available under NDA.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/gfp.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/blkdev.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/device.h>
19*4882a593Smuzhiyun #include <scsi/scsi_host.h>
20*4882a593Smuzhiyun #include <linux/libata.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define DRV_NAME "sata_uli"
23*4882a593Smuzhiyun #define DRV_VERSION "1.3"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun enum {
26*4882a593Smuzhiyun uli_5289 = 0,
27*4882a593Smuzhiyun uli_5287 = 1,
28*4882a593Smuzhiyun uli_5281 = 2,
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun uli_max_ports = 4,
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* PCI configuration registers */
33*4882a593Smuzhiyun ULI5287_BASE = 0x90, /* sata0 phy SCR registers */
34*4882a593Smuzhiyun ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */
35*4882a593Smuzhiyun ULI5281_BASE = 0x60, /* sata0 phy SCR registers */
36*4882a593Smuzhiyun ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct uli_priv {
40*4882a593Smuzhiyun unsigned int scr_cfg_addr[uli_max_ports];
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
44*4882a593Smuzhiyun static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
45*4882a593Smuzhiyun static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct pci_device_id uli_pci_tbl[] = {
48*4882a593Smuzhiyun { PCI_VDEVICE(AL, 0x5289), uli_5289 },
49*4882a593Smuzhiyun { PCI_VDEVICE(AL, 0x5287), uli_5287 },
50*4882a593Smuzhiyun { PCI_VDEVICE(AL, 0x5281), uli_5281 },
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun { } /* terminate list */
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static struct pci_driver uli_pci_driver = {
56*4882a593Smuzhiyun .name = DRV_NAME,
57*4882a593Smuzhiyun .id_table = uli_pci_tbl,
58*4882a593Smuzhiyun .probe = uli_init_one,
59*4882a593Smuzhiyun .remove = ata_pci_remove_one,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static struct scsi_host_template uli_sht = {
63*4882a593Smuzhiyun ATA_BMDMA_SHT(DRV_NAME),
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static struct ata_port_operations uli_ops = {
67*4882a593Smuzhiyun .inherits = &ata_bmdma_port_ops,
68*4882a593Smuzhiyun .scr_read = uli_scr_read,
69*4882a593Smuzhiyun .scr_write = uli_scr_write,
70*4882a593Smuzhiyun .hardreset = ATA_OP_NULL,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const struct ata_port_info uli_port_info = {
74*4882a593Smuzhiyun .flags = ATA_FLAG_SATA | ATA_FLAG_IGN_SIMPLEX,
75*4882a593Smuzhiyun .pio_mask = ATA_PIO4,
76*4882a593Smuzhiyun .udma_mask = ATA_UDMA6,
77*4882a593Smuzhiyun .port_ops = &uli_ops,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun MODULE_AUTHOR("Peer Chen");
82*4882a593Smuzhiyun MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller");
83*4882a593Smuzhiyun MODULE_LICENSE("GPL");
84*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, uli_pci_tbl);
85*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
86*4882a593Smuzhiyun
get_scr_cfg_addr(struct ata_port * ap,unsigned int sc_reg)87*4882a593Smuzhiyun static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct uli_priv *hpriv = ap->host->private_data;
90*4882a593Smuzhiyun return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
uli_scr_cfg_read(struct ata_link * link,unsigned int sc_reg)93*4882a593Smuzhiyun static u32 uli_scr_cfg_read(struct ata_link *link, unsigned int sc_reg)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
96*4882a593Smuzhiyun unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
97*4882a593Smuzhiyun u32 val;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun pci_read_config_dword(pdev, cfg_addr, &val);
100*4882a593Smuzhiyun return val;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
uli_scr_cfg_write(struct ata_link * link,unsigned int scr,u32 val)103*4882a593Smuzhiyun static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
106*4882a593Smuzhiyun unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun pci_write_config_dword(pdev, cfg_addr, val);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
uli_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)111*4882a593Smuzhiyun static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun if (sc_reg > SCR_CONTROL)
114*4882a593Smuzhiyun return -EINVAL;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun *val = uli_scr_cfg_read(link, sc_reg);
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
uli_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)120*4882a593Smuzhiyun static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
123*4882a593Smuzhiyun return -EINVAL;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun uli_scr_cfg_write(link, sc_reg, val);
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
uli_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)129*4882a593Smuzhiyun static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun const struct ata_port_info *ppi[] = { &uli_port_info, NULL };
132*4882a593Smuzhiyun unsigned int board_idx = (unsigned int) ent->driver_data;
133*4882a593Smuzhiyun struct ata_host *host;
134*4882a593Smuzhiyun struct uli_priv *hpriv;
135*4882a593Smuzhiyun void __iomem * const *iomap;
136*4882a593Smuzhiyun struct ata_ioports *ioaddr;
137*4882a593Smuzhiyun int n_ports, rc;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun ata_print_version_once(&pdev->dev, DRV_VERSION);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun rc = pcim_enable_device(pdev);
142*4882a593Smuzhiyun if (rc)
143*4882a593Smuzhiyun return rc;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun n_ports = 2;
146*4882a593Smuzhiyun if (board_idx == uli_5287)
147*4882a593Smuzhiyun n_ports = 4;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* allocate the host */
150*4882a593Smuzhiyun host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
151*4882a593Smuzhiyun if (!host)
152*4882a593Smuzhiyun return -ENOMEM;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
155*4882a593Smuzhiyun if (!hpriv)
156*4882a593Smuzhiyun return -ENOMEM;
157*4882a593Smuzhiyun host->private_data = hpriv;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* the first two ports are standard SFF */
160*4882a593Smuzhiyun rc = ata_pci_sff_init_host(host);
161*4882a593Smuzhiyun if (rc)
162*4882a593Smuzhiyun return rc;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ata_pci_bmdma_init(host);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun iomap = host->iomap;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun switch (board_idx) {
169*4882a593Smuzhiyun case uli_5287:
170*4882a593Smuzhiyun /* If there are four, the last two live right after
171*4882a593Smuzhiyun * the standard SFF ports.
172*4882a593Smuzhiyun */
173*4882a593Smuzhiyun hpriv->scr_cfg_addr[0] = ULI5287_BASE;
174*4882a593Smuzhiyun hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun ioaddr = &host->ports[2]->ioaddr;
177*4882a593Smuzhiyun ioaddr->cmd_addr = iomap[0] + 8;
178*4882a593Smuzhiyun ioaddr->altstatus_addr =
179*4882a593Smuzhiyun ioaddr->ctl_addr = (void __iomem *)
180*4882a593Smuzhiyun ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4;
181*4882a593Smuzhiyun ioaddr->bmdma_addr = iomap[4] + 16;
182*4882a593Smuzhiyun hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4;
183*4882a593Smuzhiyun ata_sff_std_ports(ioaddr);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ata_port_desc(host->ports[2],
186*4882a593Smuzhiyun "cmd 0x%llx ctl 0x%llx bmdma 0x%llx",
187*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pdev, 0) + 8,
188*4882a593Smuzhiyun ((unsigned long long)pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS) + 4,
189*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pdev, 4) + 16);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun ioaddr = &host->ports[3]->ioaddr;
192*4882a593Smuzhiyun ioaddr->cmd_addr = iomap[2] + 8;
193*4882a593Smuzhiyun ioaddr->altstatus_addr =
194*4882a593Smuzhiyun ioaddr->ctl_addr = (void __iomem *)
195*4882a593Smuzhiyun ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4;
196*4882a593Smuzhiyun ioaddr->bmdma_addr = iomap[4] + 24;
197*4882a593Smuzhiyun hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5;
198*4882a593Smuzhiyun ata_sff_std_ports(ioaddr);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun ata_port_desc(host->ports[2],
201*4882a593Smuzhiyun "cmd 0x%llx ctl 0x%llx bmdma 0x%llx",
202*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pdev, 2) + 9,
203*4882a593Smuzhiyun ((unsigned long long)pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS) + 4,
204*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pdev, 4) + 24);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun break;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun case uli_5289:
209*4882a593Smuzhiyun hpriv->scr_cfg_addr[0] = ULI5287_BASE;
210*4882a593Smuzhiyun hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun case uli_5281:
214*4882a593Smuzhiyun hpriv->scr_cfg_addr[0] = ULI5281_BASE;
215*4882a593Smuzhiyun hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS;
216*4882a593Smuzhiyun break;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun default:
219*4882a593Smuzhiyun BUG();
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun pci_set_master(pdev);
224*4882a593Smuzhiyun pci_intx(pdev, 1);
225*4882a593Smuzhiyun return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
226*4882a593Smuzhiyun IRQF_SHARED, &uli_sht);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun module_pci_driver(uli_pci_driver);
230