1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * pata_sch.c - Intel SCH PATA controllers
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2008 Alek Du <alek.du@intel.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * Supports:
10*4882a593Smuzhiyun * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
11*4882a593Smuzhiyun * http://download.intel.com/design/chipsets/embedded/datashts/319537.pdf
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/pci.h>
17*4882a593Smuzhiyun #include <linux/blkdev.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/device.h>
20*4882a593Smuzhiyun #include <scsi/scsi_host.h>
21*4882a593Smuzhiyun #include <linux/libata.h>
22*4882a593Smuzhiyun #include <linux/dmi.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define DRV_NAME "pata_sch"
25*4882a593Smuzhiyun #define DRV_VERSION "0.2"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* see SCH datasheet page 351 */
28*4882a593Smuzhiyun enum {
29*4882a593Smuzhiyun D0TIM = 0x80, /* Device 0 Timing Register */
30*4882a593Smuzhiyun D1TIM = 0x84, /* Device 1 Timing Register */
31*4882a593Smuzhiyun PM = 0x07, /* PIO Mode Bit Mask */
32*4882a593Smuzhiyun MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
33*4882a593Smuzhiyun UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
34*4882a593Smuzhiyun PPE = (1 << 30), /* Prefetch/Post Enable */
35*4882a593Smuzhiyun USD = (1 << 31), /* Use Synchronous DMA */
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static int sch_init_one(struct pci_dev *pdev,
39*4882a593Smuzhiyun const struct pci_device_id *ent);
40*4882a593Smuzhiyun static void sch_set_piomode(struct ata_port *ap, struct ata_device *adev);
41*4882a593Smuzhiyun static void sch_set_dmamode(struct ata_port *ap, struct ata_device *adev);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const struct pci_device_id sch_pci_tbl[] = {
44*4882a593Smuzhiyun /* Intel SCH PATA Controller */
45*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_IDE), 0 },
46*4882a593Smuzhiyun { } /* terminate list */
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static struct pci_driver sch_pci_driver = {
50*4882a593Smuzhiyun .name = DRV_NAME,
51*4882a593Smuzhiyun .id_table = sch_pci_tbl,
52*4882a593Smuzhiyun .probe = sch_init_one,
53*4882a593Smuzhiyun .remove = ata_pci_remove_one,
54*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
55*4882a593Smuzhiyun .suspend = ata_pci_device_suspend,
56*4882a593Smuzhiyun .resume = ata_pci_device_resume,
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct scsi_host_template sch_sht = {
61*4882a593Smuzhiyun ATA_BMDMA_SHT(DRV_NAME),
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static struct ata_port_operations sch_pata_ops = {
65*4882a593Smuzhiyun .inherits = &ata_bmdma_port_ops,
66*4882a593Smuzhiyun .cable_detect = ata_cable_unknown,
67*4882a593Smuzhiyun .set_piomode = sch_set_piomode,
68*4882a593Smuzhiyun .set_dmamode = sch_set_dmamode,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct ata_port_info sch_port_info = {
72*4882a593Smuzhiyun .flags = ATA_FLAG_SLAVE_POSS,
73*4882a593Smuzhiyun .pio_mask = ATA_PIO4,
74*4882a593Smuzhiyun .mwdma_mask = ATA_MWDMA2,
75*4882a593Smuzhiyun .udma_mask = ATA_UDMA5,
76*4882a593Smuzhiyun .port_ops = &sch_pata_ops,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
80*4882a593Smuzhiyun MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
81*4882a593Smuzhiyun MODULE_LICENSE("GPL");
82*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, sch_pci_tbl);
83*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /**
86*4882a593Smuzhiyun * sch_set_piomode - Initialize host controller PATA PIO timings
87*4882a593Smuzhiyun * @ap: Port whose timings we are configuring
88*4882a593Smuzhiyun * @adev: ATA device
89*4882a593Smuzhiyun *
90*4882a593Smuzhiyun * Set PIO mode for device, in host controller PCI config space.
91*4882a593Smuzhiyun *
92*4882a593Smuzhiyun * LOCKING:
93*4882a593Smuzhiyun * None (inherited from caller).
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun
sch_set_piomode(struct ata_port * ap,struct ata_device * adev)96*4882a593Smuzhiyun static void sch_set_piomode(struct ata_port *ap, struct ata_device *adev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun unsigned int pio = adev->pio_mode - XFER_PIO_0;
99*4882a593Smuzhiyun struct pci_dev *dev = to_pci_dev(ap->host->dev);
100*4882a593Smuzhiyun unsigned int port = adev->devno ? D1TIM : D0TIM;
101*4882a593Smuzhiyun unsigned int data;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun pci_read_config_dword(dev, port, &data);
104*4882a593Smuzhiyun /* see SCH datasheet page 351 */
105*4882a593Smuzhiyun /* set PIO mode */
106*4882a593Smuzhiyun data &= ~(PM | PPE);
107*4882a593Smuzhiyun data |= pio;
108*4882a593Smuzhiyun /* enable PPE for block device */
109*4882a593Smuzhiyun if (adev->class == ATA_DEV_ATA)
110*4882a593Smuzhiyun data |= PPE;
111*4882a593Smuzhiyun pci_write_config_dword(dev, port, data);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /**
115*4882a593Smuzhiyun * sch_set_dmamode - Initialize host controller PATA DMA timings
116*4882a593Smuzhiyun * @ap: Port whose timings we are configuring
117*4882a593Smuzhiyun * @adev: ATA device
118*4882a593Smuzhiyun *
119*4882a593Smuzhiyun * Set MW/UDMA mode for device, in host controller PCI config space.
120*4882a593Smuzhiyun *
121*4882a593Smuzhiyun * LOCKING:
122*4882a593Smuzhiyun * None (inherited from caller).
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun
sch_set_dmamode(struct ata_port * ap,struct ata_device * adev)125*4882a593Smuzhiyun static void sch_set_dmamode(struct ata_port *ap, struct ata_device *adev)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun unsigned int dma_mode = adev->dma_mode;
128*4882a593Smuzhiyun struct pci_dev *dev = to_pci_dev(ap->host->dev);
129*4882a593Smuzhiyun unsigned int port = adev->devno ? D1TIM : D0TIM;
130*4882a593Smuzhiyun unsigned int data;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun pci_read_config_dword(dev, port, &data);
133*4882a593Smuzhiyun /* see SCH datasheet page 351 */
134*4882a593Smuzhiyun if (dma_mode >= XFER_UDMA_0) {
135*4882a593Smuzhiyun /* enable Synchronous DMA mode */
136*4882a593Smuzhiyun data |= USD;
137*4882a593Smuzhiyun data &= ~UDM;
138*4882a593Smuzhiyun data |= (dma_mode - XFER_UDMA_0) << 16;
139*4882a593Smuzhiyun } else { /* must be MWDMA mode, since we masked SWDMA already */
140*4882a593Smuzhiyun data &= ~(USD | MDM);
141*4882a593Smuzhiyun data |= (dma_mode - XFER_MW_DMA_0) << 8;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun pci_write_config_dword(dev, port, data);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /**
147*4882a593Smuzhiyun * sch_init_one - Register SCH ATA PCI device with kernel services
148*4882a593Smuzhiyun * @pdev: PCI device to register
149*4882a593Smuzhiyun * @ent: Entry in sch_pci_tbl matching with @pdev
150*4882a593Smuzhiyun *
151*4882a593Smuzhiyun * LOCKING:
152*4882a593Smuzhiyun * Inherited from PCI layer (may sleep).
153*4882a593Smuzhiyun *
154*4882a593Smuzhiyun * RETURNS:
155*4882a593Smuzhiyun * Zero on success, or -ERRNO value.
156*4882a593Smuzhiyun */
157*4882a593Smuzhiyun
sch_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)158*4882a593Smuzhiyun static int sch_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun const struct ata_port_info *ppi[] = { &sch_port_info, NULL };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ata_print_version_once(&pdev->dev, DRV_VERSION);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return ata_pci_bmdma_init_one(pdev, ppi, &sch_sht, NULL, 0);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun module_pci_driver(sch_pci_driver);
168