1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
4*4882a593Smuzhiyun * PATA port of the controller. The SATA ports are
5*4882a593Smuzhiyun * driven by AHCI in the usual configuration although
6*4882a593Smuzhiyun * this driver can handle other setups if we need it.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (c) 2006 Red Hat
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/blkdev.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/device.h>
17*4882a593Smuzhiyun #include <scsi/scsi_host.h>
18*4882a593Smuzhiyun #include <linux/libata.h>
19*4882a593Smuzhiyun #include <linux/ata.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define DRV_NAME "pata_jmicron"
22*4882a593Smuzhiyun #define DRV_VERSION "0.1.5"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun typedef enum {
25*4882a593Smuzhiyun PORT_PATA0 = 0,
26*4882a593Smuzhiyun PORT_PATA1 = 1,
27*4882a593Smuzhiyun PORT_SATA = 2,
28*4882a593Smuzhiyun } port_type;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /**
31*4882a593Smuzhiyun * jmicron_pre_reset - check for 40/80 pin
32*4882a593Smuzhiyun * @link: ATA link
33*4882a593Smuzhiyun * @deadline: deadline jiffies for the operation
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * Perform the PATA port setup we need.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * On the Jmicron 361/363 there is a single PATA port that can be mapped
38*4882a593Smuzhiyun * either as primary or secondary (or neither). We don't do any policy
39*4882a593Smuzhiyun * and setup here. We assume that has been done by init_one and the
40*4882a593Smuzhiyun * BIOS.
41*4882a593Smuzhiyun */
jmicron_pre_reset(struct ata_link * link,unsigned long deadline)42*4882a593Smuzhiyun static int jmicron_pre_reset(struct ata_link *link, unsigned long deadline)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct ata_port *ap = link->ap;
45*4882a593Smuzhiyun struct pci_dev *pdev = to_pci_dev(ap->host->dev);
46*4882a593Smuzhiyun u32 control;
47*4882a593Smuzhiyun u32 control5;
48*4882a593Smuzhiyun int port_mask = 1<< (4 * ap->port_no);
49*4882a593Smuzhiyun int port = ap->port_no;
50*4882a593Smuzhiyun port_type port_map[2];
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Check if our port is enabled */
53*4882a593Smuzhiyun pci_read_config_dword(pdev, 0x40, &control);
54*4882a593Smuzhiyun if ((control & port_mask) == 0)
55*4882a593Smuzhiyun return -ENOENT;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* There are two basic mappings. One has the two SATA ports merged
58*4882a593Smuzhiyun as master/slave and the secondary as PATA, the other has only the
59*4882a593Smuzhiyun SATA port mapped */
60*4882a593Smuzhiyun if (control & (1 << 23)) {
61*4882a593Smuzhiyun port_map[0] = PORT_SATA;
62*4882a593Smuzhiyun port_map[1] = PORT_PATA0;
63*4882a593Smuzhiyun } else {
64*4882a593Smuzhiyun port_map[0] = PORT_SATA;
65*4882a593Smuzhiyun port_map[1] = PORT_SATA;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* The 365/366 may have this bit set to map the second PATA port
69*4882a593Smuzhiyun as the internal primary channel */
70*4882a593Smuzhiyun pci_read_config_dword(pdev, 0x80, &control5);
71*4882a593Smuzhiyun if (control5 & (1<<24))
72*4882a593Smuzhiyun port_map[0] = PORT_PATA1;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* The two ports may then be logically swapped by the firmware */
75*4882a593Smuzhiyun if (control & (1 << 22))
76*4882a593Smuzhiyun port = port ^ 1;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * Now we know which physical port we are talking about we can
80*4882a593Smuzhiyun * actually do our cable checking etc. Thankfully we don't need
81*4882a593Smuzhiyun * to do the plumbing for other cases.
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun switch (port_map[port]) {
84*4882a593Smuzhiyun case PORT_PATA0:
85*4882a593Smuzhiyun if ((control & (1 << 5)) == 0)
86*4882a593Smuzhiyun return -ENOENT;
87*4882a593Smuzhiyun if (control & (1 << 3)) /* 40/80 pin primary */
88*4882a593Smuzhiyun ap->cbl = ATA_CBL_PATA40;
89*4882a593Smuzhiyun else
90*4882a593Smuzhiyun ap->cbl = ATA_CBL_PATA80;
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun case PORT_PATA1:
93*4882a593Smuzhiyun /* Bit 21 is set if the port is enabled */
94*4882a593Smuzhiyun if ((control5 & (1 << 21)) == 0)
95*4882a593Smuzhiyun return -ENOENT;
96*4882a593Smuzhiyun if (control5 & (1 << 19)) /* 40/80 pin secondary */
97*4882a593Smuzhiyun ap->cbl = ATA_CBL_PATA40;
98*4882a593Smuzhiyun else
99*4882a593Smuzhiyun ap->cbl = ATA_CBL_PATA80;
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun case PORT_SATA:
102*4882a593Smuzhiyun ap->cbl = ATA_CBL_SATA;
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun return ata_sff_prereset(link, deadline);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* No PIO or DMA methods needed for this device */
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct scsi_host_template jmicron_sht = {
111*4882a593Smuzhiyun ATA_BMDMA_SHT(DRV_NAME),
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct ata_port_operations jmicron_ops = {
115*4882a593Smuzhiyun .inherits = &ata_bmdma_port_ops,
116*4882a593Smuzhiyun .prereset = jmicron_pre_reset,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /**
121*4882a593Smuzhiyun * jmicron_init_one - Register Jmicron ATA PCI device with kernel services
122*4882a593Smuzhiyun * @pdev: PCI device to register
123*4882a593Smuzhiyun * @ent: Entry in jmicron_pci_tbl matching with @pdev
124*4882a593Smuzhiyun *
125*4882a593Smuzhiyun * Called from kernel PCI layer.
126*4882a593Smuzhiyun *
127*4882a593Smuzhiyun * LOCKING:
128*4882a593Smuzhiyun * Inherited from PCI layer (may sleep).
129*4882a593Smuzhiyun *
130*4882a593Smuzhiyun * RETURNS:
131*4882a593Smuzhiyun * Zero on success, or -ERRNO value.
132*4882a593Smuzhiyun */
133*4882a593Smuzhiyun
jmicron_init_one(struct pci_dev * pdev,const struct pci_device_id * id)134*4882a593Smuzhiyun static int jmicron_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun static const struct ata_port_info info = {
137*4882a593Smuzhiyun .flags = ATA_FLAG_SLAVE_POSS,
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun .pio_mask = ATA_PIO4,
140*4882a593Smuzhiyun .mwdma_mask = ATA_MWDMA2,
141*4882a593Smuzhiyun .udma_mask = ATA_UDMA5,
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun .port_ops = &jmicron_ops,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun const struct ata_port_info *ppi[] = { &info, NULL };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return ata_pci_bmdma_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static const struct pci_device_id jmicron_pci_tbl[] = {
151*4882a593Smuzhiyun { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
152*4882a593Smuzhiyun PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 },
153*4882a593Smuzhiyun { } /* terminate list */
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun static struct pci_driver jmicron_pci_driver = {
157*4882a593Smuzhiyun .name = DRV_NAME,
158*4882a593Smuzhiyun .id_table = jmicron_pci_tbl,
159*4882a593Smuzhiyun .probe = jmicron_init_one,
160*4882a593Smuzhiyun .remove = ata_pci_remove_one,
161*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
162*4882a593Smuzhiyun .suspend = ata_pci_device_suspend,
163*4882a593Smuzhiyun .resume = ata_pci_device_resume,
164*4882a593Smuzhiyun #endif
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun module_pci_driver(jmicron_pci_driver);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun MODULE_AUTHOR("Alan Cox");
170*4882a593Smuzhiyun MODULE_DESCRIPTION("SCSI low-level driver for Jmicron PATA ports");
171*4882a593Smuzhiyun MODULE_LICENSE("GPL");
172*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
173*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
174*4882a593Smuzhiyun
175