1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * pata_cypress.c - Cypress PATA for new ATA layer
4*4882a593Smuzhiyun * (C) 2006 Red Hat Inc
5*4882a593Smuzhiyun * Alan Cox
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based heavily on
8*4882a593Smuzhiyun * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/blkdev.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <scsi/scsi_host.h>
18*4882a593Smuzhiyun #include <linux/libata.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DRV_NAME "pata_cypress"
21*4882a593Smuzhiyun #define DRV_VERSION "0.1.5"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* here are the offset definitions for the registers */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun enum {
26*4882a593Smuzhiyun CY82_IDE_CMDREG = 0x04,
27*4882a593Smuzhiyun CY82_IDE_ADDRSETUP = 0x48,
28*4882a593Smuzhiyun CY82_IDE_MASTER_IOR = 0x4C,
29*4882a593Smuzhiyun CY82_IDE_MASTER_IOW = 0x4D,
30*4882a593Smuzhiyun CY82_IDE_SLAVE_IOR = 0x4E,
31*4882a593Smuzhiyun CY82_IDE_SLAVE_IOW = 0x4F,
32*4882a593Smuzhiyun CY82_IDE_MASTER_8BIT = 0x50,
33*4882a593Smuzhiyun CY82_IDE_SLAVE_8BIT = 0x51,
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun CY82_INDEX_PORT = 0x22,
36*4882a593Smuzhiyun CY82_DATA_PORT = 0x23,
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun CY82_INDEX_CTRLREG1 = 0x01,
39*4882a593Smuzhiyun CY82_INDEX_CHANNEL0 = 0x30,
40*4882a593Smuzhiyun CY82_INDEX_CHANNEL1 = 0x31,
41*4882a593Smuzhiyun CY82_INDEX_TIMEOUT = 0x32
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /**
45*4882a593Smuzhiyun * cy82c693_set_piomode - set initial PIO mode data
46*4882a593Smuzhiyun * @ap: ATA interface
47*4882a593Smuzhiyun * @adev: ATA device
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * Called to do the PIO mode setup.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun
cy82c693_set_piomode(struct ata_port * ap,struct ata_device * adev)52*4882a593Smuzhiyun static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct pci_dev *pdev = to_pci_dev(ap->host->dev);
55*4882a593Smuzhiyun struct ata_timing t;
56*4882a593Smuzhiyun const unsigned long T = 1000000 / 33;
57*4882a593Smuzhiyun short time_16, time_8;
58*4882a593Smuzhiyun u32 addr;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) {
61*4882a593Smuzhiyun printk(KERN_ERR DRV_NAME ": mome computation failed.\n");
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun time_16 = clamp_val(t.recover - 1, 0, 15) |
66*4882a593Smuzhiyun (clamp_val(t.active - 1, 0, 15) << 4);
67*4882a593Smuzhiyun time_8 = clamp_val(t.act8b - 1, 0, 15) |
68*4882a593Smuzhiyun (clamp_val(t.rec8b - 1, 0, 15) << 4);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (adev->devno == 0) {
71*4882a593Smuzhiyun pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun addr &= ~0x0F; /* Mask bits */
74*4882a593Smuzhiyun addr |= clamp_val(t.setup - 1, 0, 15);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
77*4882a593Smuzhiyun pci_write_config_byte(pdev, CY82_IDE_MASTER_IOR, time_16);
78*4882a593Smuzhiyun pci_write_config_byte(pdev, CY82_IDE_MASTER_IOW, time_16);
79*4882a593Smuzhiyun pci_write_config_byte(pdev, CY82_IDE_MASTER_8BIT, time_8);
80*4882a593Smuzhiyun } else {
81*4882a593Smuzhiyun pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun addr &= ~0xF0; /* Mask bits */
84*4882a593Smuzhiyun addr |= (clamp_val(t.setup - 1, 0, 15) << 4);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
87*4882a593Smuzhiyun pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOR, time_16);
88*4882a593Smuzhiyun pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOW, time_16);
89*4882a593Smuzhiyun pci_write_config_byte(pdev, CY82_IDE_SLAVE_8BIT, time_8);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /**
94*4882a593Smuzhiyun * cy82c693_set_dmamode - set initial DMA mode data
95*4882a593Smuzhiyun * @ap: ATA interface
96*4882a593Smuzhiyun * @adev: ATA device
97*4882a593Smuzhiyun *
98*4882a593Smuzhiyun * Called to do the DMA mode setup.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun
cy82c693_set_dmamode(struct ata_port * ap,struct ata_device * adev)101*4882a593Smuzhiyun static void cy82c693_set_dmamode(struct ata_port *ap, struct ata_device *adev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun int reg = CY82_INDEX_CHANNEL0 + ap->port_no;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Be afraid, be very afraid. Magic registers in low I/O space */
106*4882a593Smuzhiyun outb(reg, 0x22);
107*4882a593Smuzhiyun outb(adev->dma_mode - XFER_MW_DMA_0, 0x23);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* 0x50 gives the best behaviour on the Alpha's using this chip */
110*4882a593Smuzhiyun outb(CY82_INDEX_TIMEOUT, 0x22);
111*4882a593Smuzhiyun outb(0x50, 0x23);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct scsi_host_template cy82c693_sht = {
115*4882a593Smuzhiyun ATA_BMDMA_SHT(DRV_NAME),
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct ata_port_operations cy82c693_port_ops = {
119*4882a593Smuzhiyun .inherits = &ata_bmdma_port_ops,
120*4882a593Smuzhiyun .cable_detect = ata_cable_40wire,
121*4882a593Smuzhiyun .set_piomode = cy82c693_set_piomode,
122*4882a593Smuzhiyun .set_dmamode = cy82c693_set_dmamode,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
cy82c693_init_one(struct pci_dev * pdev,const struct pci_device_id * id)125*4882a593Smuzhiyun static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun static const struct ata_port_info info = {
128*4882a593Smuzhiyun .flags = ATA_FLAG_SLAVE_POSS,
129*4882a593Smuzhiyun .pio_mask = ATA_PIO4,
130*4882a593Smuzhiyun .mwdma_mask = ATA_MWDMA2,
131*4882a593Smuzhiyun .port_ops = &cy82c693_port_ops
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* Devfn 1 is the ATA primary. The secondary is magic and on devfn2.
136*4882a593Smuzhiyun For the moment we don't handle the secondary. FIXME */
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (PCI_FUNC(pdev->devfn) != 1)
139*4882a593Smuzhiyun return -ENODEV;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return ata_pci_bmdma_init_one(pdev, ppi, &cy82c693_sht, NULL, 0);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static const struct pci_device_id cy82c693[] = {
145*4882a593Smuzhiyun { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), },
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun { },
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static struct pci_driver cy82c693_pci_driver = {
151*4882a593Smuzhiyun .name = DRV_NAME,
152*4882a593Smuzhiyun .id_table = cy82c693,
153*4882a593Smuzhiyun .probe = cy82c693_init_one,
154*4882a593Smuzhiyun .remove = ata_pci_remove_one,
155*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
156*4882a593Smuzhiyun .suspend = ata_pci_device_suspend,
157*4882a593Smuzhiyun .resume = ata_pci_device_resume,
158*4882a593Smuzhiyun #endif
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun module_pci_driver(cy82c693_pci_driver);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun MODULE_AUTHOR("Alan Cox");
164*4882a593Smuzhiyun MODULE_DESCRIPTION("low-level driver for the CY82C693 PATA controller");
165*4882a593Smuzhiyun MODULE_LICENSE("GPL");
166*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, cy82c693);
167*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
168