1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ata_generic.c - Generic PATA/SATA controller driver.
3*4882a593Smuzhiyun * Copyright 2005 Red Hat Inc, all rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Elements from ide/pci/generic.c
6*4882a593Smuzhiyun * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
7*4882a593Smuzhiyun * Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * May be copied or modified under the terms of the GNU General Public License
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Driver for PCI IDE interfaces implementing the standard bus mastering
12*4882a593Smuzhiyun * interface functionality. This assumes the BIOS did the drive set up and
13*4882a593Smuzhiyun * tuning for us. By default we do not grab all IDE class devices as they
14*4882a593Smuzhiyun * may have other drivers or need fixups to avoid problems. Instead we keep
15*4882a593Smuzhiyun * a default list of stuff without documentation/driver that appears to
16*4882a593Smuzhiyun * work.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/kernel.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/pci.h>
22*4882a593Smuzhiyun #include <linux/blkdev.h>
23*4882a593Smuzhiyun #include <linux/delay.h>
24*4882a593Smuzhiyun #include <scsi/scsi_host.h>
25*4882a593Smuzhiyun #include <linux/libata.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define DRV_NAME "ata_generic"
28*4882a593Smuzhiyun #define DRV_VERSION "0.2.15"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * A generic parallel ATA driver using libata
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun enum {
35*4882a593Smuzhiyun ATA_GEN_CLASS_MATCH = (1 << 0),
36*4882a593Smuzhiyun ATA_GEN_FORCE_DMA = (1 << 1),
37*4882a593Smuzhiyun ATA_GEN_INTEL_IDER = (1 << 2),
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /**
41*4882a593Smuzhiyun * generic_set_mode - mode setting
42*4882a593Smuzhiyun * @link: link to set up
43*4882a593Smuzhiyun * @unused: returned device on error
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * Use a non standard set_mode function. We don't want to be tuned.
46*4882a593Smuzhiyun * The BIOS configured everything. Our job is not to fiddle. We
47*4882a593Smuzhiyun * read the dma enabled bits from the PCI configuration of the device
48*4882a593Smuzhiyun * and respect them.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun
generic_set_mode(struct ata_link * link,struct ata_device ** unused)51*4882a593Smuzhiyun static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct ata_port *ap = link->ap;
54*4882a593Smuzhiyun const struct pci_device_id *id = ap->host->private_data;
55*4882a593Smuzhiyun int dma_enabled = 0;
56*4882a593Smuzhiyun struct ata_device *dev;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (id->driver_data & ATA_GEN_FORCE_DMA) {
59*4882a593Smuzhiyun dma_enabled = 0xff;
60*4882a593Smuzhiyun } else if (ap->ioaddr.bmdma_addr) {
61*4882a593Smuzhiyun /* Bits 5 and 6 indicate if DMA is active on master/slave */
62*4882a593Smuzhiyun dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun ata_for_each_dev(dev, link, ENABLED) {
66*4882a593Smuzhiyun /* We don't really care */
67*4882a593Smuzhiyun dev->pio_mode = XFER_PIO_0;
68*4882a593Smuzhiyun dev->dma_mode = XFER_MW_DMA_0;
69*4882a593Smuzhiyun /* We do need the right mode information for DMA or PIO
70*4882a593Smuzhiyun and this comes from the current configuration flags */
71*4882a593Smuzhiyun if (dma_enabled & (1 << (5 + dev->devno))) {
72*4882a593Smuzhiyun unsigned int xfer_mask = ata_id_xfermask(dev->id);
73*4882a593Smuzhiyun const char *name;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (xfer_mask & (ATA_MASK_MWDMA | ATA_MASK_UDMA))
76*4882a593Smuzhiyun name = ata_mode_string(xfer_mask);
77*4882a593Smuzhiyun else {
78*4882a593Smuzhiyun /* SWDMA perhaps? */
79*4882a593Smuzhiyun name = "DMA";
80*4882a593Smuzhiyun xfer_mask |= ata_xfer_mode2mask(XFER_MW_DMA_0);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun ata_dev_info(dev, "configured for %s\n", name);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun dev->xfer_mode = ata_xfer_mask2mode(xfer_mask);
86*4882a593Smuzhiyun dev->xfer_shift = ata_xfer_mode2shift(dev->xfer_mode);
87*4882a593Smuzhiyun dev->flags &= ~ATA_DFLAG_PIO;
88*4882a593Smuzhiyun } else {
89*4882a593Smuzhiyun ata_dev_info(dev, "configured for PIO\n");
90*4882a593Smuzhiyun dev->xfer_mode = XFER_PIO_0;
91*4882a593Smuzhiyun dev->xfer_shift = ATA_SHIFT_PIO;
92*4882a593Smuzhiyun dev->flags |= ATA_DFLAG_PIO;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct scsi_host_template generic_sht = {
99*4882a593Smuzhiyun ATA_BMDMA_SHT(DRV_NAME),
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static struct ata_port_operations generic_port_ops = {
103*4882a593Smuzhiyun .inherits = &ata_bmdma_port_ops,
104*4882a593Smuzhiyun .cable_detect = ata_cable_unknown,
105*4882a593Smuzhiyun .set_mode = generic_set_mode,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static int all_generic_ide; /* Set to claim all devices */
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /**
111*4882a593Smuzhiyun * is_intel_ider - identify intel IDE-R devices
112*4882a593Smuzhiyun * @dev: PCI device
113*4882a593Smuzhiyun *
114*4882a593Smuzhiyun * Distinguish Intel IDE-R controller devices from other Intel IDE
115*4882a593Smuzhiyun * devices. IDE-R devices have no timing registers and are in
116*4882a593Smuzhiyun * most respects virtual. They should be driven by the ata_generic
117*4882a593Smuzhiyun * driver.
118*4882a593Smuzhiyun *
119*4882a593Smuzhiyun * IDE-R devices have PCI offset 0xF8.L as zero, later Intel ATA has
120*4882a593Smuzhiyun * it non zero. All Intel ATA has 0x40 writable (timing), but it is
121*4882a593Smuzhiyun * not writable on IDE-R devices (this is guaranteed).
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun
is_intel_ider(struct pci_dev * dev)124*4882a593Smuzhiyun static int is_intel_ider(struct pci_dev *dev)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun /* For Intel IDE the value at 0xF8 is only zero on IDE-R
127*4882a593Smuzhiyun interfaces */
128*4882a593Smuzhiyun u32 r;
129*4882a593Smuzhiyun u16 t;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Check the manufacturing ID, it will be zero for IDE-R */
132*4882a593Smuzhiyun pci_read_config_dword(dev, 0xF8, &r);
133*4882a593Smuzhiyun /* Not IDE-R: punt so that ata_(old)piix gets it */
134*4882a593Smuzhiyun if (r != 0)
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun /* 0xF8 will also be zero on some early Intel IDE devices
137*4882a593Smuzhiyun but they will have a sane timing register */
138*4882a593Smuzhiyun pci_read_config_word(dev, 0x40, &t);
139*4882a593Smuzhiyun if (t != 0)
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun /* Finally check if the timing register is writable so that
142*4882a593Smuzhiyun we eliminate any early devices hot-docked in a docking
143*4882a593Smuzhiyun station */
144*4882a593Smuzhiyun pci_write_config_word(dev, 0x40, 1);
145*4882a593Smuzhiyun pci_read_config_word(dev, 0x40, &t);
146*4882a593Smuzhiyun if (t) {
147*4882a593Smuzhiyun pci_write_config_word(dev, 0x40, 0);
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun return 1;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /**
154*4882a593Smuzhiyun * ata_generic_init - attach generic IDE
155*4882a593Smuzhiyun * @dev: PCI device found
156*4882a593Smuzhiyun * @id: match entry
157*4882a593Smuzhiyun *
158*4882a593Smuzhiyun * Called each time a matching IDE interface is found. We check if the
159*4882a593Smuzhiyun * interface is one we wish to claim and if so we perform any chip
160*4882a593Smuzhiyun * specific hacks then let the ATA layer do the heavy lifting.
161*4882a593Smuzhiyun */
162*4882a593Smuzhiyun
ata_generic_init_one(struct pci_dev * dev,const struct pci_device_id * id)163*4882a593Smuzhiyun static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun u16 command;
166*4882a593Smuzhiyun static const struct ata_port_info info = {
167*4882a593Smuzhiyun .flags = ATA_FLAG_SLAVE_POSS,
168*4882a593Smuzhiyun .pio_mask = ATA_PIO4,
169*4882a593Smuzhiyun .mwdma_mask = ATA_MWDMA2,
170*4882a593Smuzhiyun .udma_mask = ATA_UDMA5,
171*4882a593Smuzhiyun .port_ops = &generic_port_ops
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun const struct ata_port_info *ppi[] = { &info, NULL };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* Don't use the generic entry unless instructed to do so */
176*4882a593Smuzhiyun if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0)
177*4882a593Smuzhiyun return -ENODEV;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if ((id->driver_data & ATA_GEN_INTEL_IDER) && !all_generic_ide)
180*4882a593Smuzhiyun if (!is_intel_ider(dev))
181*4882a593Smuzhiyun return -ENODEV;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* Devices that need care */
184*4882a593Smuzhiyun if (dev->vendor == PCI_VENDOR_ID_UMC &&
185*4882a593Smuzhiyun dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
186*4882a593Smuzhiyun (!(PCI_FUNC(dev->devfn) & 1)))
187*4882a593Smuzhiyun return -ENODEV;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun if (dev->vendor == PCI_VENDOR_ID_OPTI &&
190*4882a593Smuzhiyun dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
191*4882a593Smuzhiyun (!(PCI_FUNC(dev->devfn) & 1)))
192*4882a593Smuzhiyun return -ENODEV;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Don't re-enable devices in generic mode or we will break some
195*4882a593Smuzhiyun motherboards with disabled and unused IDE controllers */
196*4882a593Smuzhiyun pci_read_config_word(dev, PCI_COMMAND, &command);
197*4882a593Smuzhiyun if (!(command & PCI_COMMAND_IO))
198*4882a593Smuzhiyun return -ENODEV;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (dev->vendor == PCI_VENDOR_ID_AL)
201*4882a593Smuzhiyun ata_pci_bmdma_clear_simplex(dev);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (dev->vendor == PCI_VENDOR_ID_ATI) {
204*4882a593Smuzhiyun int rc = pcim_enable_device(dev);
205*4882a593Smuzhiyun if (rc < 0)
206*4882a593Smuzhiyun return rc;
207*4882a593Smuzhiyun pcim_pin_device(dev);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun static struct pci_device_id ata_generic[] = {
213*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
214*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
215*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), },
216*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A), },
217*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF), },
218*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), },
219*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561), },
220*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), },
221*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
222*4882a593Smuzhiyun .driver_data = ATA_GEN_FORCE_DMA },
223*4882a593Smuzhiyun #if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
224*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
225*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), },
226*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3), },
227*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5), },
228*4882a593Smuzhiyun #endif
229*4882a593Smuzhiyun /* Intel, IDE class device */
230*4882a593Smuzhiyun { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
231*4882a593Smuzhiyun PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL,
232*4882a593Smuzhiyun .driver_data = ATA_GEN_INTEL_IDER },
233*4882a593Smuzhiyun /* Must come last. If you add entries adjust this table appropriately */
234*4882a593Smuzhiyun { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL),
235*4882a593Smuzhiyun .driver_data = ATA_GEN_CLASS_MATCH },
236*4882a593Smuzhiyun { 0, },
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static struct pci_driver ata_generic_pci_driver = {
240*4882a593Smuzhiyun .name = DRV_NAME,
241*4882a593Smuzhiyun .id_table = ata_generic,
242*4882a593Smuzhiyun .probe = ata_generic_init_one,
243*4882a593Smuzhiyun .remove = ata_pci_remove_one,
244*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
245*4882a593Smuzhiyun .suspend = ata_pci_device_suspend,
246*4882a593Smuzhiyun .resume = ata_pci_device_resume,
247*4882a593Smuzhiyun #endif
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun module_pci_driver(ata_generic_pci_driver);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun MODULE_AUTHOR("Alan Cox");
253*4882a593Smuzhiyun MODULE_DESCRIPTION("low-level driver for generic ATA");
254*4882a593Smuzhiyun MODULE_LICENSE("GPL");
255*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, ata_generic);
256*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun module_param(all_generic_ide, int, 0);
259