1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun #include <linux/pci.h>
4*4882a593Smuzhiyun #include <linux/acpi.h>
5*4882a593Smuzhiyun #include <acpi/reboot.h>
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifdef CONFIG_PCI
acpi_pci_reboot(struct acpi_generic_address * rr,u8 reset_value)9*4882a593Smuzhiyun static void acpi_pci_reboot(struct acpi_generic_address *rr, u8 reset_value)
10*4882a593Smuzhiyun {
11*4882a593Smuzhiyun unsigned int devfn;
12*4882a593Smuzhiyun struct pci_bus *bus0;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* The reset register can only live on bus 0. */
15*4882a593Smuzhiyun bus0 = pci_find_bus(0, 0);
16*4882a593Smuzhiyun if (!bus0)
17*4882a593Smuzhiyun return;
18*4882a593Smuzhiyun /* Form PCI device/function pair. */
19*4882a593Smuzhiyun devfn = PCI_DEVFN((rr->address >> 32) & 0xffff,
20*4882a593Smuzhiyun (rr->address >> 16) & 0xffff);
21*4882a593Smuzhiyun pr_debug("Resetting with ACPI PCI RESET_REG.\n");
22*4882a593Smuzhiyun /* Write the value that resets us. */
23*4882a593Smuzhiyun pci_bus_write_config_byte(bus0, devfn,
24*4882a593Smuzhiyun (rr->address & 0xffff), reset_value);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun #else
acpi_pci_reboot(struct acpi_generic_address * rr,u8 reset_value)27*4882a593Smuzhiyun static inline void acpi_pci_reboot(struct acpi_generic_address *rr,
28*4882a593Smuzhiyun u8 reset_value)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun pr_warn_once("PCI configuration space access is not supported\n");
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
acpi_reboot(void)34*4882a593Smuzhiyun void acpi_reboot(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct acpi_generic_address *rr;
37*4882a593Smuzhiyun u8 reset_value;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (acpi_disabled)
40*4882a593Smuzhiyun return;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun rr = &acpi_gbl_FADT.reset_register;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* ACPI reset register was only introduced with v2 of the FADT */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (acpi_gbl_FADT.header.revision < 2)
47*4882a593Smuzhiyun return;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Is the reset register supported? The spec says we should be
50*4882a593Smuzhiyun * checking the bit width and bit offset, but Windows ignores
51*4882a593Smuzhiyun * these fields */
52*4882a593Smuzhiyun if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER))
53*4882a593Smuzhiyun return;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun reset_value = acpi_gbl_FADT.reset_value;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* The reset register can only exist in I/O, Memory or PCI config space
58*4882a593Smuzhiyun * on a device on bus 0. */
59*4882a593Smuzhiyun switch (rr->space_id) {
60*4882a593Smuzhiyun case ACPI_ADR_SPACE_PCI_CONFIG:
61*4882a593Smuzhiyun acpi_pci_reboot(rr, reset_value);
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun case ACPI_ADR_SPACE_SYSTEM_MEMORY:
65*4882a593Smuzhiyun case ACPI_ADR_SPACE_SYSTEM_IO:
66*4882a593Smuzhiyun printk(KERN_DEBUG "ACPI MEMORY or I/O RESET_REG.\n");
67*4882a593Smuzhiyun acpi_reset();
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * Some platforms do not shut down immediately after writing to the
73*4882a593Smuzhiyun * ACPI reset register, and this results in racing with the
74*4882a593Smuzhiyun * subsequent reboot mechanism.
75*4882a593Smuzhiyun *
76*4882a593Smuzhiyun * The 15ms delay has been found to be long enough for the system
77*4882a593Smuzhiyun * to reboot on the affected platforms.
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun mdelay(15);
80*4882a593Smuzhiyun }
81