1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright(c) 2018 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * Intel specific definitions for NVDIMM Firmware Interface Table - NFIT 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _NFIT_INTEL_H_ 7*4882a593Smuzhiyun #define _NFIT_INTEL_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ND_INTEL_SMART 1 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5) 12*4882a593Smuzhiyun #define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct nd_intel_smart { 15*4882a593Smuzhiyun u32 status; 16*4882a593Smuzhiyun union { 17*4882a593Smuzhiyun struct { 18*4882a593Smuzhiyun u32 flags; 19*4882a593Smuzhiyun u8 reserved0[4]; 20*4882a593Smuzhiyun u8 health; 21*4882a593Smuzhiyun u8 spares; 22*4882a593Smuzhiyun u8 life_used; 23*4882a593Smuzhiyun u8 alarm_flags; 24*4882a593Smuzhiyun u16 media_temperature; 25*4882a593Smuzhiyun u16 ctrl_temperature; 26*4882a593Smuzhiyun u32 shutdown_count; 27*4882a593Smuzhiyun u8 ait_status; 28*4882a593Smuzhiyun u16 pmic_temperature; 29*4882a593Smuzhiyun u8 reserved1[8]; 30*4882a593Smuzhiyun u8 shutdown_state; 31*4882a593Smuzhiyun u32 vendor_size; 32*4882a593Smuzhiyun u8 vendor_data[92]; 33*4882a593Smuzhiyun } __packed; 34*4882a593Smuzhiyun u8 data[128]; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun } __packed; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun extern const struct nvdimm_security_ops *intel_security_ops; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ND_INTEL_STATUS_SIZE 4 41*4882a593Smuzhiyun #define ND_INTEL_PASSPHRASE_SIZE 32 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define ND_INTEL_STATUS_NOT_SUPPORTED 1 44*4882a593Smuzhiyun #define ND_INTEL_STATUS_RETRY 5 45*4882a593Smuzhiyun #define ND_INTEL_STATUS_NOT_READY 9 46*4882a593Smuzhiyun #define ND_INTEL_STATUS_INVALID_STATE 10 47*4882a593Smuzhiyun #define ND_INTEL_STATUS_INVALID_PASS 11 48*4882a593Smuzhiyun #define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED 0x10007 49*4882a593Smuzhiyun #define ND_INTEL_STATUS_OQUERY_INPROGRESS 0x10007 50*4882a593Smuzhiyun #define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR 0x20007 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define ND_INTEL_SEC_STATE_ENABLED 0x02 53*4882a593Smuzhiyun #define ND_INTEL_SEC_STATE_LOCKED 0x04 54*4882a593Smuzhiyun #define ND_INTEL_SEC_STATE_FROZEN 0x08 55*4882a593Smuzhiyun #define ND_INTEL_SEC_STATE_PLIMIT 0x10 56*4882a593Smuzhiyun #define ND_INTEL_SEC_STATE_UNSUPPORTED 0x20 57*4882a593Smuzhiyun #define ND_INTEL_SEC_STATE_OVERWRITE 0x40 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define ND_INTEL_SEC_ESTATE_ENABLED 0x01 60*4882a593Smuzhiyun #define ND_INTEL_SEC_ESTATE_PLIMIT 0x02 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct nd_intel_get_security_state { 63*4882a593Smuzhiyun u32 status; 64*4882a593Smuzhiyun u8 extended_state; 65*4882a593Smuzhiyun u8 reserved[3]; 66*4882a593Smuzhiyun u8 state; 67*4882a593Smuzhiyun u8 reserved1[3]; 68*4882a593Smuzhiyun } __packed; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct nd_intel_set_passphrase { 71*4882a593Smuzhiyun u8 old_pass[ND_INTEL_PASSPHRASE_SIZE]; 72*4882a593Smuzhiyun u8 new_pass[ND_INTEL_PASSPHRASE_SIZE]; 73*4882a593Smuzhiyun u32 status; 74*4882a593Smuzhiyun } __packed; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct nd_intel_unlock_unit { 77*4882a593Smuzhiyun u8 passphrase[ND_INTEL_PASSPHRASE_SIZE]; 78*4882a593Smuzhiyun u32 status; 79*4882a593Smuzhiyun } __packed; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct nd_intel_disable_passphrase { 82*4882a593Smuzhiyun u8 passphrase[ND_INTEL_PASSPHRASE_SIZE]; 83*4882a593Smuzhiyun u32 status; 84*4882a593Smuzhiyun } __packed; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct nd_intel_freeze_lock { 87*4882a593Smuzhiyun u32 status; 88*4882a593Smuzhiyun } __packed; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct nd_intel_secure_erase { 91*4882a593Smuzhiyun u8 passphrase[ND_INTEL_PASSPHRASE_SIZE]; 92*4882a593Smuzhiyun u32 status; 93*4882a593Smuzhiyun } __packed; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct nd_intel_overwrite { 96*4882a593Smuzhiyun u8 passphrase[ND_INTEL_PASSPHRASE_SIZE]; 97*4882a593Smuzhiyun u32 status; 98*4882a593Smuzhiyun } __packed; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct nd_intel_query_overwrite { 101*4882a593Smuzhiyun u32 status; 102*4882a593Smuzhiyun } __packed; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct nd_intel_set_master_passphrase { 105*4882a593Smuzhiyun u8 old_pass[ND_INTEL_PASSPHRASE_SIZE]; 106*4882a593Smuzhiyun u8 new_pass[ND_INTEL_PASSPHRASE_SIZE]; 107*4882a593Smuzhiyun u32 status; 108*4882a593Smuzhiyun } __packed; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun struct nd_intel_master_secure_erase { 111*4882a593Smuzhiyun u8 passphrase[ND_INTEL_PASSPHRASE_SIZE]; 112*4882a593Smuzhiyun u32 status; 113*4882a593Smuzhiyun } __packed; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define ND_INTEL_FWA_IDLE 0 116*4882a593Smuzhiyun #define ND_INTEL_FWA_ARMED 1 117*4882a593Smuzhiyun #define ND_INTEL_FWA_BUSY 2 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_NONE 0 120*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_NOTSTAGED 1 121*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_SUCCESS 2 122*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_NEEDRESET 3 123*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_MEDIAFAILED 4 124*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_ABORT 5 125*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_NOTSUPP 6 126*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_ERROR 7 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun struct nd_intel_fw_activate_dimminfo { 129*4882a593Smuzhiyun u32 status; 130*4882a593Smuzhiyun u16 result; 131*4882a593Smuzhiyun u8 state; 132*4882a593Smuzhiyun u8 reserved[7]; 133*4882a593Smuzhiyun } __packed; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_ARM 1 136*4882a593Smuzhiyun #define ND_INTEL_DIMM_FWA_DISARM 0 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun struct nd_intel_fw_activate_arm { 139*4882a593Smuzhiyun u8 activate_arm; 140*4882a593Smuzhiyun u32 status; 141*4882a593Smuzhiyun } __packed; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* Root device command payloads */ 144*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0) 145*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1) 146*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_CAP_RESET (1 << 2) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun struct nd_intel_bus_fw_activate_businfo { 149*4882a593Smuzhiyun u32 status; 150*4882a593Smuzhiyun u16 reserved; 151*4882a593Smuzhiyun u8 state; 152*4882a593Smuzhiyun u8 capability; 153*4882a593Smuzhiyun u64 activate_tmo; 154*4882a593Smuzhiyun u64 cpu_quiesce_tmo; 155*4882a593Smuzhiyun u64 io_quiesce_tmo; 156*4882a593Smuzhiyun u64 max_quiesce_tmo; 157*4882a593Smuzhiyun } __packed; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_STATUS_NOARM (6 | 1 << 16) 160*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_STATUS_BUSY (6 | 2 << 16) 161*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_STATUS_NOFW (6 | 3 << 16) 162*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_STATUS_TMO (6 | 4 << 16) 163*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16) 164*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_STATUS_ABORT (6 | 6 << 16) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0) 167*4882a593Smuzhiyun #define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1) 168*4882a593Smuzhiyun struct nd_intel_bus_fw_activate { 169*4882a593Smuzhiyun u8 iodev_state; 170*4882a593Smuzhiyun u32 status; 171*4882a593Smuzhiyun } __packed; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun extern const struct nvdimm_fw_ops *intel_fw_ops; 174*4882a593Smuzhiyun extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops; 175*4882a593Smuzhiyun #endif 176