xref: /OK3568_Linux_fs/kernel/crypto/async_tx/async_tx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * core routines for the asynchronous memory transfer/transform api
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright © 2006, Intel Corporation.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *	Dan Williams <dan.j.williams@intel.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  *	with architecture considerations by:
10*4882a593Smuzhiyun  *	Neil Brown <neilb@suse.de>
11*4882a593Smuzhiyun  *	Jeff Garzik <jeff@garzik.org>
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun #include <linux/rculist.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/async_tx.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #ifdef CONFIG_DMA_ENGINE
async_tx_init(void)19*4882a593Smuzhiyun static int __init async_tx_init(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun 	async_dmaengine_get();
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	printk(KERN_INFO "async_tx: api initialized (async)\n");
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	return 0;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun 
async_tx_exit(void)28*4882a593Smuzhiyun static void __exit async_tx_exit(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	async_dmaengine_put();
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun module_init(async_tx_init);
34*4882a593Smuzhiyun module_exit(async_tx_exit);
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /**
37*4882a593Smuzhiyun  * __async_tx_find_channel - find a channel to carry out the operation or let
38*4882a593Smuzhiyun  *	the transaction execute synchronously
39*4882a593Smuzhiyun  * @submit: transaction dependency and submission modifiers
40*4882a593Smuzhiyun  * @tx_type: transaction type
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun struct dma_chan *
__async_tx_find_channel(struct async_submit_ctl * submit,enum dma_transaction_type tx_type)43*4882a593Smuzhiyun __async_tx_find_channel(struct async_submit_ctl *submit,
44*4882a593Smuzhiyun 			enum dma_transaction_type tx_type)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun 	struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	/* see if we can keep the chain on one channel */
49*4882a593Smuzhiyun 	if (depend_tx &&
50*4882a593Smuzhiyun 	    dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
51*4882a593Smuzhiyun 		return depend_tx->chan;
52*4882a593Smuzhiyun 	return async_dma_find_channel(tx_type);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__async_tx_find_channel);
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /**
59*4882a593Smuzhiyun  * async_tx_channel_switch - queue an interrupt descriptor with a dependency
60*4882a593Smuzhiyun  * 	pre-attached.
61*4882a593Smuzhiyun  * @depend_tx: the operation that must finish before the new operation runs
62*4882a593Smuzhiyun  * @tx: the new operation
63*4882a593Smuzhiyun  */
64*4882a593Smuzhiyun static void
async_tx_channel_switch(struct dma_async_tx_descriptor * depend_tx,struct dma_async_tx_descriptor * tx)65*4882a593Smuzhiyun async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
66*4882a593Smuzhiyun 			struct dma_async_tx_descriptor *tx)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	struct dma_chan *chan = depend_tx->chan;
69*4882a593Smuzhiyun 	struct dma_device *device = chan->device;
70*4882a593Smuzhiyun 	struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	/* first check to see if we can still append to depend_tx */
73*4882a593Smuzhiyun 	txd_lock(depend_tx);
74*4882a593Smuzhiyun 	if (txd_parent(depend_tx) && depend_tx->chan == tx->chan) {
75*4882a593Smuzhiyun 		txd_chain(depend_tx, tx);
76*4882a593Smuzhiyun 		intr_tx = NULL;
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun 	txd_unlock(depend_tx);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* attached dependency, flush the parent channel */
81*4882a593Smuzhiyun 	if (!intr_tx) {
82*4882a593Smuzhiyun 		device->device_issue_pending(chan);
83*4882a593Smuzhiyun 		return;
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	/* see if we can schedule an interrupt
87*4882a593Smuzhiyun 	 * otherwise poll for completion
88*4882a593Smuzhiyun 	 */
89*4882a593Smuzhiyun 	if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
90*4882a593Smuzhiyun 		intr_tx = device->device_prep_dma_interrupt(chan, 0);
91*4882a593Smuzhiyun 	else
92*4882a593Smuzhiyun 		intr_tx = NULL;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (intr_tx) {
95*4882a593Smuzhiyun 		intr_tx->callback = NULL;
96*4882a593Smuzhiyun 		intr_tx->callback_param = NULL;
97*4882a593Smuzhiyun 		/* safe to chain outside the lock since we know we are
98*4882a593Smuzhiyun 		 * not submitted yet
99*4882a593Smuzhiyun 		 */
100*4882a593Smuzhiyun 		txd_chain(intr_tx, tx);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 		/* check if we need to append */
103*4882a593Smuzhiyun 		txd_lock(depend_tx);
104*4882a593Smuzhiyun 		if (txd_parent(depend_tx)) {
105*4882a593Smuzhiyun 			txd_chain(depend_tx, intr_tx);
106*4882a593Smuzhiyun 			async_tx_ack(intr_tx);
107*4882a593Smuzhiyun 			intr_tx = NULL;
108*4882a593Smuzhiyun 		}
109*4882a593Smuzhiyun 		txd_unlock(depend_tx);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 		if (intr_tx) {
112*4882a593Smuzhiyun 			txd_clear_parent(intr_tx);
113*4882a593Smuzhiyun 			intr_tx->tx_submit(intr_tx);
114*4882a593Smuzhiyun 			async_tx_ack(intr_tx);
115*4882a593Smuzhiyun 		}
116*4882a593Smuzhiyun 		device->device_issue_pending(chan);
117*4882a593Smuzhiyun 	} else {
118*4882a593Smuzhiyun 		if (dma_wait_for_async_tx(depend_tx) != DMA_COMPLETE)
119*4882a593Smuzhiyun 			panic("%s: DMA error waiting for depend_tx\n",
120*4882a593Smuzhiyun 			      __func__);
121*4882a593Smuzhiyun 		tx->tx_submit(tx);
122*4882a593Smuzhiyun 	}
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /**
127*4882a593Smuzhiyun  * submit_disposition - flags for routing an incoming operation
128*4882a593Smuzhiyun  * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
129*4882a593Smuzhiyun  * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
130*4882a593Smuzhiyun  * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
131*4882a593Smuzhiyun  *
132*4882a593Smuzhiyun  * while holding depend_tx->lock we must avoid submitting new operations
133*4882a593Smuzhiyun  * to prevent a circular locking dependency with drivers that already
134*4882a593Smuzhiyun  * hold a channel lock when calling async_tx_run_dependencies.
135*4882a593Smuzhiyun  */
136*4882a593Smuzhiyun enum submit_disposition {
137*4882a593Smuzhiyun 	ASYNC_TX_SUBMITTED,
138*4882a593Smuzhiyun 	ASYNC_TX_CHANNEL_SWITCH,
139*4882a593Smuzhiyun 	ASYNC_TX_DIRECT_SUBMIT,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun void
async_tx_submit(struct dma_chan * chan,struct dma_async_tx_descriptor * tx,struct async_submit_ctl * submit)143*4882a593Smuzhiyun async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
144*4882a593Smuzhiyun 		struct async_submit_ctl *submit)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	tx->callback = submit->cb_fn;
149*4882a593Smuzhiyun 	tx->callback_param = submit->cb_param;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	if (depend_tx) {
152*4882a593Smuzhiyun 		enum submit_disposition s;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		/* sanity check the dependency chain:
155*4882a593Smuzhiyun 		 * 1/ if ack is already set then we cannot be sure
156*4882a593Smuzhiyun 		 * we are referring to the correct operation
157*4882a593Smuzhiyun 		 * 2/ dependencies are 1:1 i.e. two transactions can
158*4882a593Smuzhiyun 		 * not depend on the same parent
159*4882a593Smuzhiyun 		 */
160*4882a593Smuzhiyun 		BUG_ON(async_tx_test_ack(depend_tx) || txd_next(depend_tx) ||
161*4882a593Smuzhiyun 		       txd_parent(tx));
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 		/* the lock prevents async_tx_run_dependencies from missing
164*4882a593Smuzhiyun 		 * the setting of ->next when ->parent != NULL
165*4882a593Smuzhiyun 		 */
166*4882a593Smuzhiyun 		txd_lock(depend_tx);
167*4882a593Smuzhiyun 		if (txd_parent(depend_tx)) {
168*4882a593Smuzhiyun 			/* we have a parent so we can not submit directly
169*4882a593Smuzhiyun 			 * if we are staying on the same channel: append
170*4882a593Smuzhiyun 			 * else: channel switch
171*4882a593Smuzhiyun 			 */
172*4882a593Smuzhiyun 			if (depend_tx->chan == chan) {
173*4882a593Smuzhiyun 				txd_chain(depend_tx, tx);
174*4882a593Smuzhiyun 				s = ASYNC_TX_SUBMITTED;
175*4882a593Smuzhiyun 			} else
176*4882a593Smuzhiyun 				s = ASYNC_TX_CHANNEL_SWITCH;
177*4882a593Smuzhiyun 		} else {
178*4882a593Smuzhiyun 			/* we do not have a parent so we may be able to submit
179*4882a593Smuzhiyun 			 * directly if we are staying on the same channel
180*4882a593Smuzhiyun 			 */
181*4882a593Smuzhiyun 			if (depend_tx->chan == chan)
182*4882a593Smuzhiyun 				s = ASYNC_TX_DIRECT_SUBMIT;
183*4882a593Smuzhiyun 			else
184*4882a593Smuzhiyun 				s = ASYNC_TX_CHANNEL_SWITCH;
185*4882a593Smuzhiyun 		}
186*4882a593Smuzhiyun 		txd_unlock(depend_tx);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 		switch (s) {
189*4882a593Smuzhiyun 		case ASYNC_TX_SUBMITTED:
190*4882a593Smuzhiyun 			break;
191*4882a593Smuzhiyun 		case ASYNC_TX_CHANNEL_SWITCH:
192*4882a593Smuzhiyun 			async_tx_channel_switch(depend_tx, tx);
193*4882a593Smuzhiyun 			break;
194*4882a593Smuzhiyun 		case ASYNC_TX_DIRECT_SUBMIT:
195*4882a593Smuzhiyun 			txd_clear_parent(tx);
196*4882a593Smuzhiyun 			tx->tx_submit(tx);
197*4882a593Smuzhiyun 			break;
198*4882a593Smuzhiyun 		}
199*4882a593Smuzhiyun 	} else {
200*4882a593Smuzhiyun 		txd_clear_parent(tx);
201*4882a593Smuzhiyun 		tx->tx_submit(tx);
202*4882a593Smuzhiyun 	}
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	if (submit->flags & ASYNC_TX_ACK)
205*4882a593Smuzhiyun 		async_tx_ack(tx);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	if (depend_tx)
208*4882a593Smuzhiyun 		async_tx_ack(depend_tx);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(async_tx_submit);
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun /**
213*4882a593Smuzhiyun  * async_trigger_callback - schedules the callback function to be run
214*4882a593Smuzhiyun  * @submit: submission and completion parameters
215*4882a593Smuzhiyun  *
216*4882a593Smuzhiyun  * honored flags: ASYNC_TX_ACK
217*4882a593Smuzhiyun  *
218*4882a593Smuzhiyun  * The callback is run after any dependent operations have completed.
219*4882a593Smuzhiyun  */
220*4882a593Smuzhiyun struct dma_async_tx_descriptor *
async_trigger_callback(struct async_submit_ctl * submit)221*4882a593Smuzhiyun async_trigger_callback(struct async_submit_ctl *submit)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	struct dma_chan *chan;
224*4882a593Smuzhiyun 	struct dma_device *device;
225*4882a593Smuzhiyun 	struct dma_async_tx_descriptor *tx;
226*4882a593Smuzhiyun 	struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	if (depend_tx) {
229*4882a593Smuzhiyun 		chan = depend_tx->chan;
230*4882a593Smuzhiyun 		device = chan->device;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 		/* see if we can schedule an interrupt
233*4882a593Smuzhiyun 		 * otherwise poll for completion
234*4882a593Smuzhiyun 		 */
235*4882a593Smuzhiyun 		if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
236*4882a593Smuzhiyun 			device = NULL;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 		tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
239*4882a593Smuzhiyun 	} else
240*4882a593Smuzhiyun 		tx = NULL;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	if (tx) {
243*4882a593Smuzhiyun 		pr_debug("%s: (async)\n", __func__);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 		async_tx_submit(chan, tx, submit);
246*4882a593Smuzhiyun 	} else {
247*4882a593Smuzhiyun 		pr_debug("%s: (sync)\n", __func__);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 		/* wait for any prerequisite operations */
250*4882a593Smuzhiyun 		async_tx_quiesce(&submit->depend_tx);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 		async_tx_sync_epilog(submit);
253*4882a593Smuzhiyun 	}
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	return tx;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(async_trigger_callback);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun /**
260*4882a593Smuzhiyun  * async_tx_quiesce - ensure tx is complete and freeable upon return
261*4882a593Smuzhiyun  * @tx - transaction to quiesce
262*4882a593Smuzhiyun  */
async_tx_quiesce(struct dma_async_tx_descriptor ** tx)263*4882a593Smuzhiyun void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	if (*tx) {
266*4882a593Smuzhiyun 		/* if ack is already set then we cannot be sure
267*4882a593Smuzhiyun 		 * we are referring to the correct operation
268*4882a593Smuzhiyun 		 */
269*4882a593Smuzhiyun 		BUG_ON(async_tx_test_ack(*tx));
270*4882a593Smuzhiyun 		if (dma_wait_for_async_tx(*tx) != DMA_COMPLETE)
271*4882a593Smuzhiyun 			panic("%s: DMA error waiting for transaction\n",
272*4882a593Smuzhiyun 			      __func__);
273*4882a593Smuzhiyun 		async_tx_ack(*tx);
274*4882a593Smuzhiyun 		*tx = NULL;
275*4882a593Smuzhiyun 	}
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(async_tx_quiesce);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun MODULE_AUTHOR("Intel Corporation");
280*4882a593Smuzhiyun MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
281*4882a593Smuzhiyun MODULE_LICENSE("GPL");
282