1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header file describes this specific Xtensa processor's TIE extensions 3*4882a593Smuzhiyun * that extend basic Xtensa core functionality. It is customized to this 4*4882a593Smuzhiyun * Xtensa processor configuration. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 7*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 8*4882a593Smuzhiyun * for more details. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (C) 1999-2007 Tensilica Inc. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _XTENSA_CORE_TIE_H 14*4882a593Smuzhiyun #define _XTENSA_CORE_TIE_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define XCHAL_CP_NUM 0 /* number of coprocessors */ 17*4882a593Smuzhiyun #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ 18*4882a593Smuzhiyun #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 19*4882a593Smuzhiyun #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 22*4882a593Smuzhiyun #define XCHAL_NCP_SA_SIZE 0 23*4882a593Smuzhiyun #define XCHAL_NCP_SA_ALIGN 1 24*4882a593Smuzhiyun #define XCHAL_CP0_SA_SIZE 0 25*4882a593Smuzhiyun #define XCHAL_CP0_SA_ALIGN 1 26*4882a593Smuzhiyun #define XCHAL_CP1_SA_SIZE 0 27*4882a593Smuzhiyun #define XCHAL_CP1_SA_ALIGN 1 28*4882a593Smuzhiyun #define XCHAL_CP2_SA_SIZE 0 29*4882a593Smuzhiyun #define XCHAL_CP2_SA_ALIGN 1 30*4882a593Smuzhiyun #define XCHAL_CP3_SA_SIZE 0 31*4882a593Smuzhiyun #define XCHAL_CP3_SA_ALIGN 1 32*4882a593Smuzhiyun #define XCHAL_CP4_SA_SIZE 0 33*4882a593Smuzhiyun #define XCHAL_CP4_SA_ALIGN 1 34*4882a593Smuzhiyun #define XCHAL_CP5_SA_SIZE 0 35*4882a593Smuzhiyun #define XCHAL_CP5_SA_ALIGN 1 36*4882a593Smuzhiyun #define XCHAL_CP6_SA_SIZE 0 37*4882a593Smuzhiyun #define XCHAL_CP6_SA_ALIGN 1 38*4882a593Smuzhiyun #define XCHAL_CP7_SA_SIZE 0 39*4882a593Smuzhiyun #define XCHAL_CP7_SA_ALIGN 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Save area for non-coprocessor optional and custom (TIE) state: */ 42*4882a593Smuzhiyun #define XCHAL_NCP_SA_SIZE 0 43*4882a593Smuzhiyun #define XCHAL_NCP_SA_ALIGN 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Total save area for optional and custom state (NCP + CPn): */ 46*4882a593Smuzhiyun #define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */ 47*4882a593Smuzhiyun #define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define XCHAL_NCP_SA_NUM 0 50*4882a593Smuzhiyun #define XCHAL_NCP_SA_LIST(s) 51*4882a593Smuzhiyun #define XCHAL_CP0_SA_NUM 0 52*4882a593Smuzhiyun #define XCHAL_CP0_SA_LIST(s) 53*4882a593Smuzhiyun #define XCHAL_CP1_SA_NUM 0 54*4882a593Smuzhiyun #define XCHAL_CP1_SA_LIST(s) 55*4882a593Smuzhiyun #define XCHAL_CP2_SA_NUM 0 56*4882a593Smuzhiyun #define XCHAL_CP2_SA_LIST(s) 57*4882a593Smuzhiyun #define XCHAL_CP3_SA_NUM 0 58*4882a593Smuzhiyun #define XCHAL_CP3_SA_LIST(s) 59*4882a593Smuzhiyun #define XCHAL_CP4_SA_NUM 0 60*4882a593Smuzhiyun #define XCHAL_CP4_SA_LIST(s) 61*4882a593Smuzhiyun #define XCHAL_CP5_SA_NUM 0 62*4882a593Smuzhiyun #define XCHAL_CP5_SA_LIST(s) 63*4882a593Smuzhiyun #define XCHAL_CP6_SA_NUM 0 64*4882a593Smuzhiyun #define XCHAL_CP6_SA_LIST(s) 65*4882a593Smuzhiyun #define XCHAL_CP7_SA_NUM 0 66*4882a593Smuzhiyun #define XCHAL_CP7_SA_LIST(s) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 69*4882a593Smuzhiyun #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /*_XTENSA_CORE_TIE_H*/ 72*4882a593Smuzhiyun 73