1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header file contains assembly-language definitions (assembly 3*4882a593Smuzhiyun * macros, etc.) for this specific Xtensa processor's TIE extensions 4*4882a593Smuzhiyun * and options. It is customized to this Xtensa processor configuration. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 7*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 8*4882a593Smuzhiyun * for more details. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (C) 1999-2007 Tensilica Inc. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _XTENSA_CORE_TIE_ASM_H 14*4882a593Smuzhiyun #define _XTENSA_CORE_TIE_ASM_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Selection parameter values for save-area save/restore macros: */ 17*4882a593Smuzhiyun /* Option vs. TIE: */ 18*4882a593Smuzhiyun #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 19*4882a593Smuzhiyun #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 20*4882a593Smuzhiyun /* Whether used automatically by compiler: */ 21*4882a593Smuzhiyun #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 22*4882a593Smuzhiyun #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 23*4882a593Smuzhiyun /* ABI handling across function calls: */ 24*4882a593Smuzhiyun #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 25*4882a593Smuzhiyun #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 26*4882a593Smuzhiyun #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 27*4882a593Smuzhiyun /* Misc */ 28*4882a593Smuzhiyun #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Macro to save all non-coprocessor (extra) custom TIE and optional state 33*4882a593Smuzhiyun * (not including zero-overhead loop registers). 34*4882a593Smuzhiyun * Save area ptr (clobbered): ptr (1 byte aligned) 35*4882a593Smuzhiyun * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 38*4882a593Smuzhiyun xchal_sa_start \continue, \ofs 39*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 40*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-8, 4, 4 41*4882a593Smuzhiyun rsr \at1, ACCLO // MAC16 accumulator 42*4882a593Smuzhiyun rsr \at2, ACCHI 43*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 44*4882a593Smuzhiyun s32i \at2, \ptr, .Lxchal_ofs_ + 4 45*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 46*4882a593Smuzhiyun .endif 47*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 48*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-16, 4, 4 49*4882a593Smuzhiyun rsr \at1, M0 // MAC16 registers 50*4882a593Smuzhiyun rsr \at2, M1 51*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 52*4882a593Smuzhiyun s32i \at2, \ptr, .Lxchal_ofs_ + 4 53*4882a593Smuzhiyun rsr \at1, M2 54*4882a593Smuzhiyun rsr \at2, M3 55*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 8 56*4882a593Smuzhiyun s32i \at2, \ptr, .Lxchal_ofs_ + 12 57*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 58*4882a593Smuzhiyun .endif 59*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 60*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 61*4882a593Smuzhiyun rsr \at1, SCOMPARE1 // conditional store option 62*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 63*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 64*4882a593Smuzhiyun .endif 65*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 66*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 67*4882a593Smuzhiyun rur \at1, THREADPTR // threadptr option 68*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 69*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 70*4882a593Smuzhiyun .endif 71*4882a593Smuzhiyun .endm // xchal_ncp_store 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Macro to save all non-coprocessor (extra) custom TIE and optional state 74*4882a593Smuzhiyun * (not including zero-overhead loop registers). 75*4882a593Smuzhiyun * Save area ptr (clobbered): ptr (1 byte aligned) 76*4882a593Smuzhiyun * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 79*4882a593Smuzhiyun xchal_sa_start \continue, \ofs 80*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 81*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-8, 4, 4 82*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 83*4882a593Smuzhiyun l32i \at2, \ptr, .Lxchal_ofs_ + 4 84*4882a593Smuzhiyun wsr \at1, ACCLO // MAC16 accumulator 85*4882a593Smuzhiyun wsr \at2, ACCHI 86*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 87*4882a593Smuzhiyun .endif 88*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 89*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-16, 4, 4 90*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 91*4882a593Smuzhiyun l32i \at2, \ptr, .Lxchal_ofs_ + 4 92*4882a593Smuzhiyun wsr \at1, M0 // MAC16 registers 93*4882a593Smuzhiyun wsr \at2, M1 94*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 8 95*4882a593Smuzhiyun l32i \at2, \ptr, .Lxchal_ofs_ + 12 96*4882a593Smuzhiyun wsr \at1, M2 97*4882a593Smuzhiyun wsr \at2, M3 98*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 99*4882a593Smuzhiyun .endif 100*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 101*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 102*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 103*4882a593Smuzhiyun wsr \at1, SCOMPARE1 // conditional store option 104*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 105*4882a593Smuzhiyun .endif 106*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 107*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 108*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 109*4882a593Smuzhiyun wur \at1, THREADPTR // threadptr option 110*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 111*4882a593Smuzhiyun .endif 112*4882a593Smuzhiyun .endm // xchal_ncp_load 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define XCHAL_NCP_NUM_ATMPS 2 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define XCHAL_SA_NUM_ATMPS 2 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #endif /*_XTENSA_CORE_TIE_ASM_H*/ 122*4882a593Smuzhiyun 123