1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Driver for the LCD display on the Tensilica XTFPGA board family.
3*4882a593Smuzhiyun * http://www.mytechcorp.com/cfdata/productFile/File1/MOC-16216B-B-A0A04.pdf
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
6*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
7*4882a593Smuzhiyun * for more details.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 2001, 2006 Tensilica Inc.
10*4882a593Smuzhiyun * Copyright (C) 2015 Cadence Design Systems Inc.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <platform/hardware.h>
18*4882a593Smuzhiyun #include <platform/lcd.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* LCD instruction and data addresses. */
21*4882a593Smuzhiyun #define LCD_INSTR_ADDR ((char *)IOADDR(CONFIG_XTFPGA_LCD_BASE_ADDR))
22*4882a593Smuzhiyun #define LCD_DATA_ADDR (LCD_INSTR_ADDR + 4)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define LCD_CLEAR 0x1
25*4882a593Smuzhiyun #define LCD_DISPLAY_ON 0xc
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* 8bit and 2 lines display */
28*4882a593Smuzhiyun #define LCD_DISPLAY_MODE8BIT 0x38
29*4882a593Smuzhiyun #define LCD_DISPLAY_MODE4BIT 0x28
30*4882a593Smuzhiyun #define LCD_DISPLAY_POS 0x80
31*4882a593Smuzhiyun #define LCD_SHIFT_LEFT 0x18
32*4882a593Smuzhiyun #define LCD_SHIFT_RIGHT 0x1c
33*4882a593Smuzhiyun
lcd_put_byte(u8 * addr,u8 data)34*4882a593Smuzhiyun static void lcd_put_byte(u8 *addr, u8 data)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun #ifdef CONFIG_XTFPGA_LCD_8BIT_ACCESS
37*4882a593Smuzhiyun WRITE_ONCE(*addr, data);
38*4882a593Smuzhiyun #else
39*4882a593Smuzhiyun WRITE_ONCE(*addr, data & 0xf0);
40*4882a593Smuzhiyun WRITE_ONCE(*addr, (data << 4) & 0xf0);
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
lcd_init(void)44*4882a593Smuzhiyun static int __init lcd_init(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun WRITE_ONCE(*LCD_INSTR_ADDR, LCD_DISPLAY_MODE8BIT);
47*4882a593Smuzhiyun mdelay(5);
48*4882a593Smuzhiyun WRITE_ONCE(*LCD_INSTR_ADDR, LCD_DISPLAY_MODE8BIT);
49*4882a593Smuzhiyun udelay(200);
50*4882a593Smuzhiyun WRITE_ONCE(*LCD_INSTR_ADDR, LCD_DISPLAY_MODE8BIT);
51*4882a593Smuzhiyun udelay(50);
52*4882a593Smuzhiyun #ifndef CONFIG_XTFPGA_LCD_8BIT_ACCESS
53*4882a593Smuzhiyun WRITE_ONCE(*LCD_INSTR_ADDR, LCD_DISPLAY_MODE4BIT);
54*4882a593Smuzhiyun udelay(50);
55*4882a593Smuzhiyun lcd_put_byte(LCD_INSTR_ADDR, LCD_DISPLAY_MODE4BIT);
56*4882a593Smuzhiyun udelay(50);
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun lcd_put_byte(LCD_INSTR_ADDR, LCD_DISPLAY_ON);
59*4882a593Smuzhiyun udelay(50);
60*4882a593Smuzhiyun lcd_put_byte(LCD_INSTR_ADDR, LCD_CLEAR);
61*4882a593Smuzhiyun mdelay(10);
62*4882a593Smuzhiyun lcd_disp_at_pos("XTENSA LINUX", 0);
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
lcd_disp_at_pos(char * str,unsigned char pos)66*4882a593Smuzhiyun void lcd_disp_at_pos(char *str, unsigned char pos)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun lcd_put_byte(LCD_INSTR_ADDR, LCD_DISPLAY_POS | pos);
69*4882a593Smuzhiyun udelay(100);
70*4882a593Smuzhiyun while (*str != 0) {
71*4882a593Smuzhiyun lcd_put_byte(LCD_DATA_ADDR, *str);
72*4882a593Smuzhiyun udelay(200);
73*4882a593Smuzhiyun str++;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
lcd_shiftleft(void)77*4882a593Smuzhiyun void lcd_shiftleft(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun lcd_put_byte(LCD_INSTR_ADDR, LCD_SHIFT_LEFT);
80*4882a593Smuzhiyun udelay(50);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
lcd_shiftright(void)83*4882a593Smuzhiyun void lcd_shiftright(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun lcd_put_byte(LCD_INSTR_ADDR, LCD_SHIFT_RIGHT);
86*4882a593Smuzhiyun udelay(50);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun arch_initcall(lcd_init);
90