1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * include/asm-xtensa/swab.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
6*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
7*4882a593Smuzhiyun * for more details.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 2001 - 2005 Tensilica Inc.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef _XTENSA_SWAB_H
13*4882a593Smuzhiyun #define _XTENSA_SWAB_H
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun #include <linux/compiler.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define __SWAB_64_THRU_32__
19*4882a593Smuzhiyun
__arch_swab32(__u32 x)20*4882a593Smuzhiyun static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun __u32 res;
23*4882a593Smuzhiyun /* instruction sequence from Xtensa ISA release 2/2000 */
24*4882a593Smuzhiyun __asm__("ssai 8 \n\t"
25*4882a593Smuzhiyun "srli %0, %1, 16 \n\t"
26*4882a593Smuzhiyun "src %0, %0, %1 \n\t"
27*4882a593Smuzhiyun "src %0, %0, %0 \n\t"
28*4882a593Smuzhiyun "src %0, %1, %0 \n"
29*4882a593Smuzhiyun : "=&a" (res)
30*4882a593Smuzhiyun : "a" (x)
31*4882a593Smuzhiyun );
32*4882a593Smuzhiyun return res;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun #define __arch_swab32 __arch_swab32
35*4882a593Smuzhiyun
__arch_swab16(__u16 x)36*4882a593Smuzhiyun static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun /* Given that 'short' values are signed (i.e., can be negative),
39*4882a593Smuzhiyun * we cannot assume that the upper 16-bits of the register are
40*4882a593Smuzhiyun * zero. We are careful to mask values after shifting.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
44*4882a593Smuzhiyun * inserts an extui instruction after putting this function inline
45*4882a593Smuzhiyun * to ensure that it uses only the least-significant 16 bits of
46*4882a593Smuzhiyun * the result. xt-xcc doesn't use an extui, but assumes the
47*4882a593Smuzhiyun * __asm__ macro follows convention that the upper 16 bits of an
48*4882a593Smuzhiyun * 'unsigned short' result are still zero. This macro doesn't
49*4882a593Smuzhiyun * follow convention; indeed, it leaves garbage in the upport 16
50*4882a593Smuzhiyun * bits of the register.
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
53*4882a593Smuzhiyun * types while the return type of the function is a 16-bit type
54*4882a593Smuzhiyun * forces both compilers to insert exactly one extui instruction
55*4882a593Smuzhiyun * (or equivalent) to mask off the upper 16 bits. */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun __u32 res;
58*4882a593Smuzhiyun __u32 tmp;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun __asm__("extui %1, %2, 8, 8\n\t"
61*4882a593Smuzhiyun "slli %0, %2, 8 \n\t"
62*4882a593Smuzhiyun "or %0, %0, %1 \n"
63*4882a593Smuzhiyun : "=&a" (res), "=&a" (tmp)
64*4882a593Smuzhiyun : "a" (x)
65*4882a593Smuzhiyun );
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return res;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun #define __arch_swab16 __arch_swab16
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #endif /* _XTENSA_SWAB_H */
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