1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of version 2.1 of the GNU Lesser General Public 6*4882a593Smuzhiyun * License as published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is distributed in the hope that it would be useful, but 9*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of 10*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Further, this software is distributed without any warranty that it is 13*4882a593Smuzhiyun * free of the rightful claim of any third person regarding infringement 14*4882a593Smuzhiyun * or the like. Any license provided herein, whether implied or 15*4882a593Smuzhiyun * otherwise, applies only to this software file. Patent licenses, if 16*4882a593Smuzhiyun * any, provided herein do not apply to combinations of this program with 17*4882a593Smuzhiyun * other software, or any other product whatsoever. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * You should have received a copy of the GNU Lesser General Public 20*4882a593Smuzhiyun * License along with this program; if not, write the Free Software 21*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, 22*4882a593Smuzhiyun * USA. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifndef _XTENSA_REGS_H 26*4882a593Smuzhiyun #define _XTENSA_REGS_H 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Special registers. */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SREG_MR 32 31*4882a593Smuzhiyun #define SREG_IBREAKENABLE 96 32*4882a593Smuzhiyun #define SREG_IBREAKA 128 33*4882a593Smuzhiyun #define SREG_DBREAKA 144 34*4882a593Smuzhiyun #define SREG_DBREAKC 160 35*4882a593Smuzhiyun #define SREG_EPC 176 36*4882a593Smuzhiyun #define SREG_EPS 192 37*4882a593Smuzhiyun #define SREG_EXCSAVE 208 38*4882a593Smuzhiyun #define SREG_CCOMPARE 240 39*4882a593Smuzhiyun #define SREG_MISC 244 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* EXCCAUSE register fields */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define EXCCAUSE_EXCCAUSE_SHIFT 0 44*4882a593Smuzhiyun #define EXCCAUSE_EXCCAUSE_MASK 0x3F 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define EXCCAUSE_ILLEGAL_INSTRUCTION 0 47*4882a593Smuzhiyun #define EXCCAUSE_SYSTEM_CALL 1 48*4882a593Smuzhiyun #define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 49*4882a593Smuzhiyun #define EXCCAUSE_LOAD_STORE_ERROR 3 50*4882a593Smuzhiyun #define EXCCAUSE_LEVEL1_INTERRUPT 4 51*4882a593Smuzhiyun #define EXCCAUSE_ALLOCA 5 52*4882a593Smuzhiyun #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 53*4882a593Smuzhiyun #define EXCCAUSE_SPECULATION 7 54*4882a593Smuzhiyun #define EXCCAUSE_PRIVILEGED 8 55*4882a593Smuzhiyun #define EXCCAUSE_UNALIGNED 9 56*4882a593Smuzhiyun #define EXCCAUSE_INSTR_DATA_ERROR 12 57*4882a593Smuzhiyun #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 58*4882a593Smuzhiyun #define EXCCAUSE_INSTR_ADDR_ERROR 14 59*4882a593Smuzhiyun #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 60*4882a593Smuzhiyun #define EXCCAUSE_ITLB_MISS 16 61*4882a593Smuzhiyun #define EXCCAUSE_ITLB_MULTIHIT 17 62*4882a593Smuzhiyun #define EXCCAUSE_ITLB_PRIVILEGE 18 63*4882a593Smuzhiyun #define EXCCAUSE_ITLB_SIZE_RESTRICTION 19 64*4882a593Smuzhiyun #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 65*4882a593Smuzhiyun #define EXCCAUSE_DTLB_MISS 24 66*4882a593Smuzhiyun #define EXCCAUSE_DTLB_MULTIHIT 25 67*4882a593Smuzhiyun #define EXCCAUSE_DTLB_PRIVILEGE 26 68*4882a593Smuzhiyun #define EXCCAUSE_DTLB_SIZE_RESTRICTION 27 69*4882a593Smuzhiyun #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 70*4882a593Smuzhiyun #define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 71*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR0_DISABLED 32 72*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR1_DISABLED 33 73*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR2_DISABLED 34 74*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR3_DISABLED 35 75*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR4_DISABLED 36 76*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR5_DISABLED 37 77*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR6_DISABLED 38 78*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR7_DISABLED 39 79*4882a593Smuzhiyun #define EXCCAUSE_N 64 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* PS register fields. */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define PS_WOE_BIT 18 84*4882a593Smuzhiyun #define PS_WOE_MASK 0x00040000 85*4882a593Smuzhiyun #define PS_CALLINC_SHIFT 16 86*4882a593Smuzhiyun #define PS_CALLINC_MASK 0x00030000 87*4882a593Smuzhiyun #define PS_OWB_SHIFT 8 88*4882a593Smuzhiyun #define PS_OWB_WIDTH 4 89*4882a593Smuzhiyun #define PS_OWB_MASK 0x00000F00 90*4882a593Smuzhiyun #define PS_RING_SHIFT 6 91*4882a593Smuzhiyun #define PS_RING_MASK 0x000000C0 92*4882a593Smuzhiyun #define PS_UM_BIT 5 93*4882a593Smuzhiyun #define PS_EXCM_BIT 4 94*4882a593Smuzhiyun #define PS_INTLEVEL_SHIFT 0 95*4882a593Smuzhiyun #define PS_INTLEVEL_WIDTH 4 96*4882a593Smuzhiyun #define PS_INTLEVEL_MASK 0x0000000F 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* DBREAKCn register fields. */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define DBREAKC_MASK_BIT 0 101*4882a593Smuzhiyun #define DBREAKC_MASK_MASK 0x0000003F 102*4882a593Smuzhiyun #define DBREAKC_LOAD_BIT 30 103*4882a593Smuzhiyun #define DBREAKC_LOAD_MASK 0x40000000 104*4882a593Smuzhiyun #define DBREAKC_STOR_BIT 31 105*4882a593Smuzhiyun #define DBREAKC_STOR_MASK 0x80000000 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* DEBUGCAUSE register fields. */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define DEBUGCAUSE_DBNUM_MASK 0xf00 110*4882a593Smuzhiyun #define DEBUGCAUSE_DBNUM_SHIFT 8 /* First bit of DBNUM field */ 111*4882a593Smuzhiyun #define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */ 112*4882a593Smuzhiyun #define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */ 113*4882a593Smuzhiyun #define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */ 114*4882a593Smuzhiyun #define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */ 115*4882a593Smuzhiyun #define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */ 116*4882a593Smuzhiyun #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* _XTENSA_SPECREG_H */ 119