1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Xtensa MX interrupt distributor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 5*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 6*4882a593Smuzhiyun * for more details. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2008 - 2013 Tensilica Inc. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _XTENSA_MXREGS_H 12*4882a593Smuzhiyun #define _XTENSA_MXREGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * RER/WER at, as Read/write external register 16*4882a593Smuzhiyun * at: value 17*4882a593Smuzhiyun * as: address 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Address Value 20*4882a593Smuzhiyun * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p 21*4882a593Smuzhiyun * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p 22*4882a593Smuzhiyun * 0180 0...0m..m Clear enable specified by mask (m) 23*4882a593Smuzhiyun * 0184 0...0m..m Set enable specified by mask (m) 24*4882a593Smuzhiyun * 0190 0...0x..x 8-bit IPI partition register 25*4882a593Smuzhiyun * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU 26*4882a593Smuzhiyun * V (10-bit) Release/Version 27*4882a593Smuzhiyun * P ( 4-bit) Number of cores - 1 28*4882a593Smuzhiyun * U (18-bit) ID 29*4882a593Smuzhiyun * 01a0 i.......i 32-bit ConfigID 30*4882a593Smuzhiyun * 0200 0...0m..m RunStall core 'n' 31*4882a593Smuzhiyun * 0220 c Cache coherency enabled 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define MIROUT(irq) (0x000 + (irq)) 35*4882a593Smuzhiyun #define MIPICAUSE(cpu) (0x100 + (cpu)) 36*4882a593Smuzhiyun #define MIPISET(cause) (0x140 + (cause)) 37*4882a593Smuzhiyun #define MIENG 0x180 38*4882a593Smuzhiyun #define MIENGSET 0x184 39*4882a593Smuzhiyun #define MIASG 0x188 /* Read Global Assert Register */ 40*4882a593Smuzhiyun #define MIASGSET 0x18c /* Set Global Addert Regiter */ 41*4882a593Smuzhiyun #define MIPIPART 0x190 42*4882a593Smuzhiyun #define SYSCFGID 0x1a0 43*4882a593Smuzhiyun #define MPSCORE 0x200 44*4882a593Smuzhiyun #define CCON 0x220 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* _XTENSA_MXREGS_H */ 47