xref: /OK3568_Linux_fs/kernel/arch/xtensa/boot/dts/virt.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/dts-v1/;
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/ {
5*4882a593Smuzhiyun	compatible = "cdns,xtensa-iss";
6*4882a593Smuzhiyun	#address-cells = <1>;
7*4882a593Smuzhiyun	#size-cells = <1>;
8*4882a593Smuzhiyun	interrupt-parent = <&pic>;
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	chosen {
11*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200n8 debug";
12*4882a593Smuzhiyun	};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	memory@0 {
15*4882a593Smuzhiyun		device_type = "memory";
16*4882a593Smuzhiyun		reg = <0x00000000 0x80000000>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	cpus {
20*4882a593Smuzhiyun		#address-cells = <1>;
21*4882a593Smuzhiyun		#size-cells = <0>;
22*4882a593Smuzhiyun		cpu@0 {
23*4882a593Smuzhiyun			compatible = "cdns,xtensa-cpu";
24*4882a593Smuzhiyun			reg = <0>;
25*4882a593Smuzhiyun			clocks = <&osc>;
26*4882a593Smuzhiyun		};
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	clocks {
30*4882a593Smuzhiyun		osc: osc {
31*4882a593Smuzhiyun			#clock-cells = <0>;
32*4882a593Smuzhiyun			compatible = "fixed-clock";
33*4882a593Smuzhiyun			clock-frequency = <40000000>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	pic: pic {
38*4882a593Smuzhiyun		compatible = "cdns,xtensa-pic";
39*4882a593Smuzhiyun		/* one cell: internal irq number,
40*4882a593Smuzhiyun		 * two cells: second cell == 0: internal irq number
41*4882a593Smuzhiyun		 *            second cell == 1: external irq number
42*4882a593Smuzhiyun		 */
43*4882a593Smuzhiyun		#address-cells = <0>;
44*4882a593Smuzhiyun		#interrupt-cells = <2>;
45*4882a593Smuzhiyun		interrupt-controller;
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	pci {
49*4882a593Smuzhiyun		compatible = "pci-host-ecam-generic";
50*4882a593Smuzhiyun		device_type = "pci";
51*4882a593Smuzhiyun		#address-cells = <3>;
52*4882a593Smuzhiyun		#size-cells = <2>;
53*4882a593Smuzhiyun		#interrupt-cells = <0x1>;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun		bus-range = <0x0 0x3e>;
56*4882a593Smuzhiyun		reg = <0xf0100000 0x03f00000>;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		     // BUS_ADDRESS(3)  CPU_PHYSICAL(1)  SIZE(2)
59*4882a593Smuzhiyun		ranges = <0x01000000 0x0 0x00000000  0xf0000000  0x0 0x00010000>,
60*4882a593Smuzhiyun			 <0x02000000 0x0 0xf4000000  0xf4000000  0x0 0x08000000>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		     // PCI_DEVICE(3)  INT#(1)  CONTROLLER(PHANDLE)  CONTROLLER_DATA(2)
63*4882a593Smuzhiyun		interrupt-map = <
64*4882a593Smuzhiyun			0x0000 0x0 0x0  0x1  &pic  0x0 0x1
65*4882a593Smuzhiyun			0x0800 0x0 0x0  0x1  &pic  0x1 0x1
66*4882a593Smuzhiyun			0x1000 0x0 0x0  0x1  &pic  0x2 0x1
67*4882a593Smuzhiyun			0x1800 0x0 0x0  0x1  &pic  0x3 0x1
68*4882a593Smuzhiyun			>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		interrupt-map-mask = <0x1800 0x0 0x0  0x7>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73