1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/ { 5*4882a593Smuzhiyun compatible = "cdns,xtensa-xtfpga"; 6*4882a593Smuzhiyun #address-cells = <1>; 7*4882a593Smuzhiyun #size-cells = <1>; 8*4882a593Smuzhiyun interrupt-parent = <&pic>; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun chosen { 11*4882a593Smuzhiyun bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel"; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@0 { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpus { 20*4882a593Smuzhiyun #address-cells = <1>; 21*4882a593Smuzhiyun #size-cells = <0>; 22*4882a593Smuzhiyun cpu@0 { 23*4882a593Smuzhiyun compatible = "cdns,xtensa-cpu"; 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun pic: pic { 29*4882a593Smuzhiyun compatible = "cdns,xtensa-pic"; 30*4882a593Smuzhiyun #interrupt-cells = <2>; 31*4882a593Smuzhiyun interrupt-controller; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clocks { 35*4882a593Smuzhiyun osc: main-oscillator { 36*4882a593Smuzhiyun #clock-cells = <0>; 37*4882a593Smuzhiyun compatible = "fixed-clock"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun soc { 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <1>; 44*4882a593Smuzhiyun compatible = "simple-bus"; 45*4882a593Smuzhiyun ranges = <0x00000000 0xf0000000 0x10000000>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun uart0: serial@0d000000 { 48*4882a593Smuzhiyun compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 49*4882a593Smuzhiyun clocks = <&osc>, <&osc>; 50*4882a593Smuzhiyun clock-names = "uart_clk", "pclk"; 51*4882a593Smuzhiyun reg = <0x0d000000 0x1000>; 52*4882a593Smuzhiyun interrupts = <0 1>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun}; 56