xref: /OK3568_Linux_fs/kernel/arch/x86/platform/ce4100/falconfalls.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * CE4100 on Falcon Falls
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (c) Copyright 2010 Intel Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	model = "intel,falconfalls";
10*4882a593Smuzhiyun	compatible = "intel,falconfalls";
11*4882a593Smuzhiyun	#address-cells = <1>;
12*4882a593Smuzhiyun	#size-cells = <1>;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	cpus {
15*4882a593Smuzhiyun		#address-cells = <1>;
16*4882a593Smuzhiyun		#size-cells = <0>;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun		cpu@0 {
19*4882a593Smuzhiyun			device_type = "cpu";
20*4882a593Smuzhiyun			compatible = "intel,ce4100";
21*4882a593Smuzhiyun			reg = <0>;
22*4882a593Smuzhiyun			lapic = <&lapic0>;
23*4882a593Smuzhiyun		};
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	soc@0 {
27*4882a593Smuzhiyun		#address-cells = <1>;
28*4882a593Smuzhiyun		#size-cells = <1>;
29*4882a593Smuzhiyun		compatible = "intel,ce4100-cp";
30*4882a593Smuzhiyun		ranges;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		ioapic1: interrupt-controller@fec00000 {
33*4882a593Smuzhiyun			#interrupt-cells = <2>;
34*4882a593Smuzhiyun			compatible = "intel,ce4100-ioapic";
35*4882a593Smuzhiyun			interrupt-controller;
36*4882a593Smuzhiyun			reg = <0xfec00000 0x1000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		timer@fed00000 {
40*4882a593Smuzhiyun			compatible = "intel,ce4100-hpet";
41*4882a593Smuzhiyun			reg = <0xfed00000 0x200>;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		lapic0: interrupt-controller@fee00000 {
45*4882a593Smuzhiyun			compatible = "intel,ce4100-lapic";
46*4882a593Smuzhiyun			reg = <0xfee00000 0x1000>;
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		pci@3fc {
50*4882a593Smuzhiyun			#address-cells = <3>;
51*4882a593Smuzhiyun			#size-cells = <2>;
52*4882a593Smuzhiyun			compatible = "intel,ce4100-pci", "pci";
53*4882a593Smuzhiyun			device_type = "pci";
54*4882a593Smuzhiyun			bus-range = <0 0>;
55*4882a593Smuzhiyun			ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56*4882a593Smuzhiyun				  0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
57*4882a593Smuzhiyun				  0x0000000 0 0x0	 0x0	    0 0x100>;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun			/* Secondary IO-APIC */
60*4882a593Smuzhiyun			ioapic2: interrupt-controller@0,1 {
61*4882a593Smuzhiyun				#interrupt-cells = <2>;
62*4882a593Smuzhiyun				compatible = "intel,ce4100-ioapic";
63*4882a593Smuzhiyun				interrupt-controller;
64*4882a593Smuzhiyun				reg = <0x100 0x0 0x0 0x0 0x0>;
65*4882a593Smuzhiyun				assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
66*4882a593Smuzhiyun			};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun			pci@1,0 {
69*4882a593Smuzhiyun				#address-cells = <3>;
70*4882a593Smuzhiyun				#size-cells = <2>;
71*4882a593Smuzhiyun				compatible = "intel,ce4100-pci", "pci";
72*4882a593Smuzhiyun				device_type = "pci";
73*4882a593Smuzhiyun				bus-range = <1 1>;
74*4882a593Smuzhiyun				reg = <0x0800 0x0 0x0 0x0 0x0>;
75*4882a593Smuzhiyun				ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun				interrupt-parent = <&ioapic2>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun				display@2,0 {
80*4882a593Smuzhiyun					compatible = "pci8086,2e5b.2",
81*4882a593Smuzhiyun						   "pci8086,2e5b",
82*4882a593Smuzhiyun						   "pciclass038000",
83*4882a593Smuzhiyun						   "pciclass0380";
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun					reg = <0x11000 0x0 0x0 0x0 0x0>;
86*4882a593Smuzhiyun					interrupts = <0 1>;
87*4882a593Smuzhiyun				};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun				multimedia@3,0 {
90*4882a593Smuzhiyun					compatible = "pci8086,2e5c.2",
91*4882a593Smuzhiyun						   "pci8086,2e5c",
92*4882a593Smuzhiyun						   "pciclass048000",
93*4882a593Smuzhiyun						   "pciclass0480";
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun					reg = <0x11800 0x0 0x0 0x0 0x0>;
96*4882a593Smuzhiyun					interrupts = <2 1>;
97*4882a593Smuzhiyun				};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun				multimedia@4,0 {
100*4882a593Smuzhiyun					compatible = "pci8086,2e5d.2",
101*4882a593Smuzhiyun						   "pci8086,2e5d",
102*4882a593Smuzhiyun						   "pciclass048000",
103*4882a593Smuzhiyun						   "pciclass0480";
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun					reg = <0x12000 0x0 0x0 0x0 0x0>;
106*4882a593Smuzhiyun					interrupts = <4 1>;
107*4882a593Smuzhiyun				};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun				multimedia@4,1 {
110*4882a593Smuzhiyun					compatible = "pci8086,2e5e.2",
111*4882a593Smuzhiyun						   "pci8086,2e5e",
112*4882a593Smuzhiyun						   "pciclass048000",
113*4882a593Smuzhiyun						   "pciclass0480";
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun					reg = <0x12100 0x0 0x0 0x0 0x0>;
116*4882a593Smuzhiyun					interrupts = <5 1>;
117*4882a593Smuzhiyun				};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun				sound@6,0 {
120*4882a593Smuzhiyun					compatible = "pci8086,2e5f.2",
121*4882a593Smuzhiyun						   "pci8086,2e5f",
122*4882a593Smuzhiyun						   "pciclass040100",
123*4882a593Smuzhiyun						   "pciclass0401";
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun					reg = <0x13000 0x0 0x0 0x0 0x0>;
126*4882a593Smuzhiyun					interrupts = <6 1>;
127*4882a593Smuzhiyun				};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun				sound@6,1 {
130*4882a593Smuzhiyun					compatible = "pci8086,2e5f.2",
131*4882a593Smuzhiyun						   "pci8086,2e5f",
132*4882a593Smuzhiyun						   "pciclass040100",
133*4882a593Smuzhiyun						   "pciclass0401";
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun					reg = <0x13100 0x0 0x0 0x0 0x0>;
136*4882a593Smuzhiyun					interrupts = <7 1>;
137*4882a593Smuzhiyun				};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun				sound@6,2 {
140*4882a593Smuzhiyun					compatible = "pci8086,2e60.2",
141*4882a593Smuzhiyun						   "pci8086,2e60",
142*4882a593Smuzhiyun						   "pciclass040100",
143*4882a593Smuzhiyun						   "pciclass0401";
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun					reg = <0x13200 0x0 0x0 0x0 0x0>;
146*4882a593Smuzhiyun					interrupts = <8 1>;
147*4882a593Smuzhiyun				};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun				display@8,0 {
150*4882a593Smuzhiyun					compatible = "pci8086,2e61.2",
151*4882a593Smuzhiyun						   "pci8086,2e61",
152*4882a593Smuzhiyun						   "pciclass038000",
153*4882a593Smuzhiyun						   "pciclass0380";
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun					reg = <0x14000 0x0 0x0 0x0 0x0>;
156*4882a593Smuzhiyun					interrupts = <9 1>;
157*4882a593Smuzhiyun				};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun				display@8,1 {
160*4882a593Smuzhiyun					compatible = "pci8086,2e62.2",
161*4882a593Smuzhiyun						   "pci8086,2e62",
162*4882a593Smuzhiyun						   "pciclass038000",
163*4882a593Smuzhiyun						   "pciclass0380";
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun					reg = <0x14100 0x0 0x0 0x0 0x0>;
166*4882a593Smuzhiyun					interrupts = <10 1>;
167*4882a593Smuzhiyun				};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun				multimedia@8,2 {
170*4882a593Smuzhiyun					compatible = "pci8086,2e63.2",
171*4882a593Smuzhiyun						   "pci8086,2e63",
172*4882a593Smuzhiyun						   "pciclass048000",
173*4882a593Smuzhiyun						   "pciclass0480";
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun					reg = <0x14200 0x0 0x0 0x0 0x0>;
176*4882a593Smuzhiyun					interrupts = <11 1>;
177*4882a593Smuzhiyun				};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun				entertainment-encryption@9,0 {
180*4882a593Smuzhiyun					compatible = "pci8086,2e64.2",
181*4882a593Smuzhiyun						   "pci8086,2e64",
182*4882a593Smuzhiyun						   "pciclass101000",
183*4882a593Smuzhiyun						   "pciclass1010";
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun					reg = <0x14800 0x0 0x0 0x0 0x0>;
186*4882a593Smuzhiyun					interrupts = <12 1>;
187*4882a593Smuzhiyun				};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun				localbus@a,0 {
190*4882a593Smuzhiyun					compatible = "pci8086,2e65.2",
191*4882a593Smuzhiyun						   "pci8086,2e65",
192*4882a593Smuzhiyun						   "pciclassff0000",
193*4882a593Smuzhiyun						   "pciclassff00";
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun					reg = <0x15000 0x0 0x0 0x0 0x0>;
196*4882a593Smuzhiyun				};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun				serial@b,0 {
199*4882a593Smuzhiyun					compatible = "pci8086,2e66.2",
200*4882a593Smuzhiyun						   "pci8086,2e66",
201*4882a593Smuzhiyun						   "pciclass070003",
202*4882a593Smuzhiyun						   "pciclass0700";
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun					reg = <0x15800 0x0 0x0 0x0 0x0>;
205*4882a593Smuzhiyun					interrupts = <14 1>;
206*4882a593Smuzhiyun				};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun				pcigpio: gpio@b,1 {
209*4882a593Smuzhiyun					#gpio-cells = <2>;
210*4882a593Smuzhiyun					#interrupt-cells = <2>;
211*4882a593Smuzhiyun					compatible = "pci8086,2e67.2",
212*4882a593Smuzhiyun						   "pci8086,2e67",
213*4882a593Smuzhiyun						   "pciclassff0000",
214*4882a593Smuzhiyun						   "pciclassff00";
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun					reg = <0x15900 0x0 0x0 0x0 0x0>;
217*4882a593Smuzhiyun					interrupts = <15 1>;
218*4882a593Smuzhiyun					interrupt-controller;
219*4882a593Smuzhiyun					gpio-controller;
220*4882a593Smuzhiyun					intel,muxctl = <0>;
221*4882a593Smuzhiyun				};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun				i2c-controller@b,2 {
224*4882a593Smuzhiyun					#address-cells = <2>;
225*4882a593Smuzhiyun					#size-cells = <1>;
226*4882a593Smuzhiyun					compatible = "pci8086,2e68.2",
227*4882a593Smuzhiyun						   "pci8086,2e68",
228*4882a593Smuzhiyun						   "pciclass,ff0000",
229*4882a593Smuzhiyun						   "pciclass,ff00";
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun					reg = <0x15a00 0x0 0x0 0x0 0x0>;
232*4882a593Smuzhiyun					interrupts = <16 1>;
233*4882a593Smuzhiyun					ranges = <0 0	0x02000000 0 0xdffe0500	0x100
234*4882a593Smuzhiyun						  1 0	0x02000000 0 0xdffe0600	0x100
235*4882a593Smuzhiyun						  2 0	0x02000000 0 0xdffe0700	0x100>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun					i2c@0 {
238*4882a593Smuzhiyun						#address-cells = <1>;
239*4882a593Smuzhiyun						#size-cells = <0>;
240*4882a593Smuzhiyun						compatible = "intel,ce4100-i2c-controller";
241*4882a593Smuzhiyun						reg = <0 0 0x100>;
242*4882a593Smuzhiyun					};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun					i2c@1 {
245*4882a593Smuzhiyun						#address-cells = <1>;
246*4882a593Smuzhiyun						#size-cells = <0>;
247*4882a593Smuzhiyun						compatible = "intel,ce4100-i2c-controller";
248*4882a593Smuzhiyun						reg = <1 0 0x100>;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun						gpio@26 {
251*4882a593Smuzhiyun							#gpio-cells = <2>;
252*4882a593Smuzhiyun							compatible = "ti,pcf8575";
253*4882a593Smuzhiyun							reg = <0x26>;
254*4882a593Smuzhiyun							gpio-controller;
255*4882a593Smuzhiyun						};
256*4882a593Smuzhiyun					};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun					i2c@2 {
259*4882a593Smuzhiyun						#address-cells = <1>;
260*4882a593Smuzhiyun						#size-cells = <0>;
261*4882a593Smuzhiyun						compatible = "intel,ce4100-i2c-controller";
262*4882a593Smuzhiyun						reg = <2 0 0x100>;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun						gpio@26 {
265*4882a593Smuzhiyun							#gpio-cells = <2>;
266*4882a593Smuzhiyun							compatible = "ti,pcf8575";
267*4882a593Smuzhiyun							reg = <0x26>;
268*4882a593Smuzhiyun							gpio-controller;
269*4882a593Smuzhiyun						};
270*4882a593Smuzhiyun					};
271*4882a593Smuzhiyun				};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun				smard-card@b,3 {
274*4882a593Smuzhiyun					compatible = "pci8086,2e69.2",
275*4882a593Smuzhiyun						   "pci8086,2e69",
276*4882a593Smuzhiyun						   "pciclass070500",
277*4882a593Smuzhiyun						   "pciclass0705";
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun					reg = <0x15b00 0x0 0x0 0x0 0x0>;
280*4882a593Smuzhiyun					interrupts = <15 1>;
281*4882a593Smuzhiyun				};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun				spi-controller@b,4 {
284*4882a593Smuzhiyun					#address-cells = <1>;
285*4882a593Smuzhiyun					#size-cells = <0>;
286*4882a593Smuzhiyun					compatible =
287*4882a593Smuzhiyun						"pci8086,2e6a.2",
288*4882a593Smuzhiyun						"pci8086,2e6a",
289*4882a593Smuzhiyun						"pciclass,ff0000",
290*4882a593Smuzhiyun						"pciclass,ff00";
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun					reg = <0x15c00 0x0 0x0 0x0 0x0>;
293*4882a593Smuzhiyun					interrupts = <15 1>;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun					dac@0 {
296*4882a593Smuzhiyun						compatible = "ti,pcm1755";
297*4882a593Smuzhiyun						reg = <0>;
298*4882a593Smuzhiyun						spi-max-frequency = <115200>;
299*4882a593Smuzhiyun					};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun					dac@1 {
302*4882a593Smuzhiyun						compatible = "ti,pcm1609a";
303*4882a593Smuzhiyun						reg = <1>;
304*4882a593Smuzhiyun						spi-max-frequency = <115200>;
305*4882a593Smuzhiyun					};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun					eeprom@2 {
308*4882a593Smuzhiyun						compatible = "atmel,at93c46";
309*4882a593Smuzhiyun						reg = <2>;
310*4882a593Smuzhiyun						spi-max-frequency = <115200>;
311*4882a593Smuzhiyun					};
312*4882a593Smuzhiyun				};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun				multimedia@b,7 {
315*4882a593Smuzhiyun					compatible = "pci8086,2e6d.2",
316*4882a593Smuzhiyun						   "pci8086,2e6d",
317*4882a593Smuzhiyun						   "pciclassff0000",
318*4882a593Smuzhiyun						   "pciclassff00";
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun					reg = <0x15f00 0x0 0x0 0x0 0x0>;
321*4882a593Smuzhiyun				};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun				ethernet@c,0 {
324*4882a593Smuzhiyun					compatible = "pci8086,2e6e.2",
325*4882a593Smuzhiyun						   "pci8086,2e6e",
326*4882a593Smuzhiyun						   "pciclass020000",
327*4882a593Smuzhiyun						   "pciclass0200";
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun					reg = <0x16000 0x0 0x0 0x0 0x0>;
330*4882a593Smuzhiyun					interrupts = <21 1>;
331*4882a593Smuzhiyun				};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun				clock@c,1 {
334*4882a593Smuzhiyun					compatible = "pci8086,2e6f.2",
335*4882a593Smuzhiyun						   "pci8086,2e6f",
336*4882a593Smuzhiyun						   "pciclassff0000",
337*4882a593Smuzhiyun						   "pciclassff00";
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun					reg = <0x16100 0x0 0x0 0x0 0x0>;
340*4882a593Smuzhiyun					interrupts = <3 1>;
341*4882a593Smuzhiyun				};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun				usb@d,0 {
344*4882a593Smuzhiyun					compatible = "pci8086,2e70.2",
345*4882a593Smuzhiyun						   "pci8086,2e70",
346*4882a593Smuzhiyun						   "pciclass0c0320",
347*4882a593Smuzhiyun						   "pciclass0c03";
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun					reg = <0x16800 0x0 0x0 0x0 0x0>;
350*4882a593Smuzhiyun					interrupts = <22 1>;
351*4882a593Smuzhiyun				};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun				usb@d,1 {
354*4882a593Smuzhiyun					compatible = "pci8086,2e70.2",
355*4882a593Smuzhiyun						   "pci8086,2e70",
356*4882a593Smuzhiyun						   "pciclass0c0320",
357*4882a593Smuzhiyun						   "pciclass0c03";
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun					reg = <0x16900 0x0 0x0 0x0 0x0>;
360*4882a593Smuzhiyun					interrupts = <22 1>;
361*4882a593Smuzhiyun				};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun				sata@e,0 {
364*4882a593Smuzhiyun					compatible = "pci8086,2e71.0",
365*4882a593Smuzhiyun						   "pci8086,2e71",
366*4882a593Smuzhiyun						   "pciclass010601",
367*4882a593Smuzhiyun						   "pciclass0106";
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun					reg = <0x17000 0x0 0x0 0x0 0x0>;
370*4882a593Smuzhiyun					interrupts = <23 1>;
371*4882a593Smuzhiyun				};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun				flash@f,0 {
374*4882a593Smuzhiyun					compatible = "pci8086,701.1",
375*4882a593Smuzhiyun						   "pci8086,701",
376*4882a593Smuzhiyun						   "pciclass050100",
377*4882a593Smuzhiyun						   "pciclass0501";
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun					reg = <0x17800 0x0 0x0 0x0 0x0>;
380*4882a593Smuzhiyun					interrupts = <13 1>;
381*4882a593Smuzhiyun				};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun				entertainment-encryption@10,0 {
384*4882a593Smuzhiyun					compatible = "pci8086,702.1",
385*4882a593Smuzhiyun						   "pci8086,702",
386*4882a593Smuzhiyun						   "pciclass101000",
387*4882a593Smuzhiyun						   "pciclass1010";
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun					reg = <0x18000 0x0 0x0 0x0 0x0>;
390*4882a593Smuzhiyun				};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun				co-processor@11,0 {
393*4882a593Smuzhiyun					compatible = "pci8086,703.1",
394*4882a593Smuzhiyun						   "pci8086,703",
395*4882a593Smuzhiyun						   "pciclass0b4000",
396*4882a593Smuzhiyun						   "pciclass0b40";
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun					reg = <0x18800 0x0 0x0 0x0 0x0>;
399*4882a593Smuzhiyun					interrupts = <1 1>;
400*4882a593Smuzhiyun				};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun				multimedia@12,0 {
403*4882a593Smuzhiyun					compatible = "pci8086,704.0",
404*4882a593Smuzhiyun						   "pci8086,704",
405*4882a593Smuzhiyun						   "pciclass048000",
406*4882a593Smuzhiyun						   "pciclass0480";
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun					reg = <0x19000 0x0 0x0 0x0 0x0>;
409*4882a593Smuzhiyun				};
410*4882a593Smuzhiyun			};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun			isa@1f,0 {
413*4882a593Smuzhiyun				#address-cells = <2>;
414*4882a593Smuzhiyun				#size-cells = <1>;
415*4882a593Smuzhiyun				compatible = "isa";
416*4882a593Smuzhiyun				reg = <0xf800 0x0 0x0 0x0 0x0>;
417*4882a593Smuzhiyun				ranges = <1 0 0 0 0 0x100>;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun				rtc@70 {
420*4882a593Smuzhiyun					compatible = "intel,ce4100-rtc", "motorola,mc146818";
421*4882a593Smuzhiyun					interrupts = <8 3>;
422*4882a593Smuzhiyun					interrupt-parent = <&ioapic1>;
423*4882a593Smuzhiyun					ctrl-reg = <2>;
424*4882a593Smuzhiyun					freq-reg = <0x26>;
425*4882a593Smuzhiyun					reg = <1 0x70 2>;
426*4882a593Smuzhiyun				};
427*4882a593Smuzhiyun			};
428*4882a593Smuzhiyun		};
429*4882a593Smuzhiyun	};
430*4882a593Smuzhiyun};
431