1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel CE4100 platform specific setup code
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2010 Intel Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/irq.h>
10*4882a593Smuzhiyun #include <linux/reboot.h>
11*4882a593Smuzhiyun #include <linux/serial_reg.h>
12*4882a593Smuzhiyun #include <linux/serial_8250.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/ce4100.h>
15*4882a593Smuzhiyun #include <asm/prom.h>
16*4882a593Smuzhiyun #include <asm/setup.h>
17*4882a593Smuzhiyun #include <asm/i8259.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun #include <asm/io_apic.h>
20*4882a593Smuzhiyun #include <asm/emergency-restart.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * The CE4100 platform has an internal 8051 Microcontroller which is
24*4882a593Smuzhiyun * responsible for signaling to the external Power Management Unit the
25*4882a593Smuzhiyun * intention to reset, reboot or power off the system. This 8051 device has
26*4882a593Smuzhiyun * its command register mapped at I/O port 0xcf9 and the value 0x4 is used
27*4882a593Smuzhiyun * to power off the system.
28*4882a593Smuzhiyun */
ce4100_power_off(void)29*4882a593Smuzhiyun static void ce4100_power_off(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun outb(0x4, 0xcf9);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250
35*4882a593Smuzhiyun
mem_serial_in(struct uart_port * p,int offset)36*4882a593Smuzhiyun static unsigned int mem_serial_in(struct uart_port *p, int offset)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun offset = offset << p->regshift;
39*4882a593Smuzhiyun return readl(p->membase + offset);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * The UART Tx interrupts are not set under some conditions and therefore serial
44*4882a593Smuzhiyun * transmission hangs. This is a silicon issue and has not been root caused. The
45*4882a593Smuzhiyun * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
46*4882a593Smuzhiyun * bit of LSR register in interrupt handler to see whether at least one of these
47*4882a593Smuzhiyun * two bits is set, if so then process the transmit request. If this workaround
48*4882a593Smuzhiyun * is not applied, then the serial transmission may hang. This workaround is for
49*4882a593Smuzhiyun * errata number 9 in Errata - B step.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun
ce4100_mem_serial_in(struct uart_port * p,int offset)52*4882a593Smuzhiyun static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun unsigned int ret, ier, lsr;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (offset == UART_IIR) {
57*4882a593Smuzhiyun offset = offset << p->regshift;
58*4882a593Smuzhiyun ret = readl(p->membase + offset);
59*4882a593Smuzhiyun if (ret & UART_IIR_NO_INT) {
60*4882a593Smuzhiyun /* see if the TX interrupt should have really set */
61*4882a593Smuzhiyun ier = mem_serial_in(p, UART_IER);
62*4882a593Smuzhiyun /* see if the UART's XMIT interrupt is enabled */
63*4882a593Smuzhiyun if (ier & UART_IER_THRI) {
64*4882a593Smuzhiyun lsr = mem_serial_in(p, UART_LSR);
65*4882a593Smuzhiyun /* now check to see if the UART should be
66*4882a593Smuzhiyun generating an interrupt (but isn't) */
67*4882a593Smuzhiyun if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
68*4882a593Smuzhiyun ret &= ~UART_IIR_NO_INT;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun } else
72*4882a593Smuzhiyun ret = mem_serial_in(p, offset);
73*4882a593Smuzhiyun return ret;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
ce4100_mem_serial_out(struct uart_port * p,int offset,int value)76*4882a593Smuzhiyun static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun offset = offset << p->regshift;
79*4882a593Smuzhiyun writel(value, p->membase + offset);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
ce4100_serial_fixup(int port,struct uart_port * up,u32 * capabilities)82*4882a593Smuzhiyun static void ce4100_serial_fixup(int port, struct uart_port *up,
83*4882a593Smuzhiyun u32 *capabilities)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun #ifdef CONFIG_EARLY_PRINTK
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * Over ride the legacy port configuration that comes from
88*4882a593Smuzhiyun * asm/serial.h. Using the ioport driver then switching to the
89*4882a593Smuzhiyun * PCI memmaped driver hangs the IOAPIC
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun if (up->iotype != UPIO_MEM32) {
92*4882a593Smuzhiyun up->uartclk = 14745600;
93*4882a593Smuzhiyun up->mapbase = 0xdffe0200;
94*4882a593Smuzhiyun set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
95*4882a593Smuzhiyun up->mapbase & PAGE_MASK);
96*4882a593Smuzhiyun up->membase =
97*4882a593Smuzhiyun (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
98*4882a593Smuzhiyun up->membase += up->mapbase & ~PAGE_MASK;
99*4882a593Smuzhiyun up->mapbase += port * 0x100;
100*4882a593Smuzhiyun up->membase += port * 0x100;
101*4882a593Smuzhiyun up->iotype = UPIO_MEM32;
102*4882a593Smuzhiyun up->regshift = 2;
103*4882a593Smuzhiyun up->irq = 4;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun #endif
106*4882a593Smuzhiyun up->iobase = 0;
107*4882a593Smuzhiyun up->serial_in = ce4100_mem_serial_in;
108*4882a593Smuzhiyun up->serial_out = ce4100_mem_serial_out;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun *capabilities |= (1 << 12);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
sdv_serial_fixup(void)113*4882a593Smuzhiyun static __init void sdv_serial_fixup(void)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun serial8250_set_isa_configurator(ce4100_serial_fixup);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #else
sdv_serial_fixup(void)119*4882a593Smuzhiyun static inline void sdv_serial_fixup(void) {};
120*4882a593Smuzhiyun #endif
121*4882a593Smuzhiyun
sdv_arch_setup(void)122*4882a593Smuzhiyun static void __init sdv_arch_setup(void)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun sdv_serial_fixup();
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
sdv_pci_init(void)127*4882a593Smuzhiyun static void sdv_pci_init(void)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun x86_of_pci_init();
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun * CE4100 specific x86_init function overrides and early setup
134*4882a593Smuzhiyun * calls.
135*4882a593Smuzhiyun */
x86_ce4100_early_setup(void)136*4882a593Smuzhiyun void __init x86_ce4100_early_setup(void)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun x86_init.oem.arch_setup = sdv_arch_setup;
139*4882a593Smuzhiyun x86_init.resources.probe_roms = x86_init_noop;
140*4882a593Smuzhiyun x86_init.mpparse.get_smp_config = x86_init_uint_noop;
141*4882a593Smuzhiyun x86_init.mpparse.find_smp_config = x86_init_noop;
142*4882a593Smuzhiyun x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
143*4882a593Smuzhiyun x86_init.pci.init = ce4100_pci_init;
144*4882a593Smuzhiyun x86_init.pci.init_irq = sdv_pci_init;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * By default, the reboot method is ACPI which is supported by the
148*4882a593Smuzhiyun * CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue
149*4882a593Smuzhiyun * the bootloader will however issue a system power off instead of
150*4882a593Smuzhiyun * reboot. By using BOOT_KBD we ensure proper system reboot as
151*4882a593Smuzhiyun * expected.
152*4882a593Smuzhiyun */
153*4882a593Smuzhiyun reboot_type = BOOT_KBD;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun pm_power_off = ce4100_power_off;
156*4882a593Smuzhiyun }
157