xref: /OK3568_Linux_fs/kernel/arch/x86/pci/sta2x11-fixup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * DMA translation between STA2x11 AMBA memory mapping and the x86 memory mapping
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * ST Microelectronics ConneXt (STA2X11/STA2X10)
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (c) 2010-2011 Wind River Systems, Inc.
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun #include <linux/pci_ids.h>
12*4882a593Smuzhiyun #include <linux/export.h>
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <linux/dma-direct.h>
15*4882a593Smuzhiyun #include <asm/iommu.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define STA2X11_SWIOTLB_SIZE (4*1024*1024)
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun  * We build a list of bus numbers that are under the ConneXt. The
21*4882a593Smuzhiyun  * main bridge hosts 4 busses, which are the 4 endpoints, in order.
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun #define STA2X11_NR_EP		4	/* 0..3 included */
24*4882a593Smuzhiyun #define STA2X11_NR_FUNCS	8	/* 0..7 included */
25*4882a593Smuzhiyun #define STA2X11_AMBA_SIZE	(512 << 20)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct sta2x11_ahb_regs { /* saved during suspend */
28*4882a593Smuzhiyun 	u32 base, pexlbase, pexhbase, crw;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct sta2x11_mapping {
32*4882a593Smuzhiyun 	int is_suspended;
33*4882a593Smuzhiyun 	struct sta2x11_ahb_regs regs[STA2X11_NR_FUNCS];
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun struct sta2x11_instance {
37*4882a593Smuzhiyun 	struct list_head list;
38*4882a593Smuzhiyun 	int bus0;
39*4882a593Smuzhiyun 	struct sta2x11_mapping map[STA2X11_NR_EP];
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun static LIST_HEAD(sta2x11_instance_list);
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* At probe time, record new instances of this bridge (likely one only) */
sta2x11_new_instance(struct pci_dev * pdev)45*4882a593Smuzhiyun static void sta2x11_new_instance(struct pci_dev *pdev)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	struct sta2x11_instance *instance;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	instance = kzalloc(sizeof(*instance), GFP_ATOMIC);
50*4882a593Smuzhiyun 	if (!instance)
51*4882a593Smuzhiyun 		return;
52*4882a593Smuzhiyun 	/* This has a subordinate bridge, with 4 more-subordinate ones */
53*4882a593Smuzhiyun 	instance->bus0 = pdev->subordinate->number + 1;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (list_empty(&sta2x11_instance_list)) {
56*4882a593Smuzhiyun 		int size = STA2X11_SWIOTLB_SIZE;
57*4882a593Smuzhiyun 		/* First instance: register your own swiotlb area */
58*4882a593Smuzhiyun 		dev_info(&pdev->dev, "Using SWIOTLB (size %i)\n", size);
59*4882a593Smuzhiyun 		if (swiotlb_late_init_with_default_size(size))
60*4882a593Smuzhiyun 			dev_emerg(&pdev->dev, "init swiotlb failed\n");
61*4882a593Smuzhiyun 	}
62*4882a593Smuzhiyun 	list_add(&instance->list, &sta2x11_instance_list);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, 0xcc17, sta2x11_new_instance);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun  * Utility functions used in this file from below
68*4882a593Smuzhiyun  */
sta2x11_pdev_to_instance(struct pci_dev * pdev)69*4882a593Smuzhiyun static struct sta2x11_instance *sta2x11_pdev_to_instance(struct pci_dev *pdev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct sta2x11_instance *instance;
72*4882a593Smuzhiyun 	int ep;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	list_for_each_entry(instance, &sta2x11_instance_list, list) {
75*4882a593Smuzhiyun 		ep = pdev->bus->number - instance->bus0;
76*4882a593Smuzhiyun 		if (ep >= 0 && ep < STA2X11_NR_EP)
77*4882a593Smuzhiyun 			return instance;
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun 	return NULL;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
sta2x11_pdev_to_ep(struct pci_dev * pdev)82*4882a593Smuzhiyun static int sta2x11_pdev_to_ep(struct pci_dev *pdev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct sta2x11_instance *instance;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	instance = sta2x11_pdev_to_instance(pdev);
87*4882a593Smuzhiyun 	if (!instance)
88*4882a593Smuzhiyun 		return -1;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	return pdev->bus->number - instance->bus0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /* This is exported, as some devices need to access the MFD registers */
sta2x11_get_instance(struct pci_dev * pdev)94*4882a593Smuzhiyun struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	return sta2x11_pdev_to_instance(pdev);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun EXPORT_SYMBOL(sta2x11_get_instance);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* At setup time, we use our own ops if the device is a ConneXt one */
sta2x11_setup_pdev(struct pci_dev * pdev)101*4882a593Smuzhiyun static void sta2x11_setup_pdev(struct pci_dev *pdev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct sta2x11_instance *instance = sta2x11_pdev_to_instance(pdev);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	if (!instance) /* either a sta2x11 bridge or another ST device */
106*4882a593Smuzhiyun 		return;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/* We must enable all devices as master, for audio DMA to work */
109*4882a593Smuzhiyun 	pci_set_master(pdev);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_setup_pdev);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun  * At boot we must set up the mappings for the pcie-to-amba bridge.
115*4882a593Smuzhiyun  * It involves device access, and the same happens at suspend/resume time
116*4882a593Smuzhiyun  */
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define AHB_MAPB		0xCA4
119*4882a593Smuzhiyun #define AHB_CRW(i)		(AHB_MAPB + 0  + (i) * 0x10)
120*4882a593Smuzhiyun #define AHB_CRW_SZMASK			0xfffffc00UL
121*4882a593Smuzhiyun #define AHB_CRW_ENABLE			(1 << 0)
122*4882a593Smuzhiyun #define AHB_CRW_WTYPE_MEM		(2 << 1)
123*4882a593Smuzhiyun #define AHB_CRW_ROE			(1UL << 3)	/* Relax Order Ena */
124*4882a593Smuzhiyun #define AHB_CRW_NSE			(1UL << 4)	/* No Snoop Enable */
125*4882a593Smuzhiyun #define AHB_BASE(i)		(AHB_MAPB + 4  + (i) * 0x10)
126*4882a593Smuzhiyun #define AHB_PEXLBASE(i)		(AHB_MAPB + 8  + (i) * 0x10)
127*4882a593Smuzhiyun #define AHB_PEXHBASE(i)		(AHB_MAPB + 12 + (i) * 0x10)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* At probe time, enable mapping for each endpoint, using the pdev */
sta2x11_map_ep(struct pci_dev * pdev)130*4882a593Smuzhiyun static void sta2x11_map_ep(struct pci_dev *pdev)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	struct sta2x11_instance *instance = sta2x11_pdev_to_instance(pdev);
133*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
134*4882a593Smuzhiyun 	u32 amba_base, max_amba_addr;
135*4882a593Smuzhiyun 	int i, ret;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if (!instance)
138*4882a593Smuzhiyun 		return;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	pci_read_config_dword(pdev, AHB_BASE(0), &amba_base);
141*4882a593Smuzhiyun 	max_amba_addr = amba_base + STA2X11_AMBA_SIZE - 1;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	ret = dma_direct_set_offset(dev, 0, amba_base, STA2X11_AMBA_SIZE);
144*4882a593Smuzhiyun 	if (ret)
145*4882a593Smuzhiyun 		dev_err(dev, "sta2x11: could not set DMA offset\n");
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	dev->bus_dma_limit = max_amba_addr;
148*4882a593Smuzhiyun 	pci_set_consistent_dma_mask(pdev, max_amba_addr);
149*4882a593Smuzhiyun 	pci_set_dma_mask(pdev, max_amba_addr);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* Configure AHB mapping */
152*4882a593Smuzhiyun 	pci_write_config_dword(pdev, AHB_PEXLBASE(0), 0);
153*4882a593Smuzhiyun 	pci_write_config_dword(pdev, AHB_PEXHBASE(0), 0);
154*4882a593Smuzhiyun 	pci_write_config_dword(pdev, AHB_CRW(0), STA2X11_AMBA_SIZE |
155*4882a593Smuzhiyun 			       AHB_CRW_WTYPE_MEM | AHB_CRW_ENABLE);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* Disable all the other windows */
158*4882a593Smuzhiyun 	for (i = 1; i < STA2X11_NR_FUNCS; i++)
159*4882a593Smuzhiyun 		pci_write_config_dword(pdev, AHB_CRW(i), 0);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	dev_info(&pdev->dev,
162*4882a593Smuzhiyun 		 "sta2x11: Map EP %i: AMBA address %#8x-%#8x\n",
163*4882a593Smuzhiyun 		 sta2x11_pdev_to_ep(pdev), amba_base, max_amba_addr);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_map_ep);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #ifdef CONFIG_PM /* Some register values must be saved and restored */
168*4882a593Smuzhiyun 
sta2x11_pdev_to_mapping(struct pci_dev * pdev)169*4882a593Smuzhiyun static struct sta2x11_mapping *sta2x11_pdev_to_mapping(struct pci_dev *pdev)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	struct sta2x11_instance *instance;
172*4882a593Smuzhiyun 	int ep;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	instance = sta2x11_pdev_to_instance(pdev);
175*4882a593Smuzhiyun 	if (!instance)
176*4882a593Smuzhiyun 		return NULL;
177*4882a593Smuzhiyun 	ep = sta2x11_pdev_to_ep(pdev);
178*4882a593Smuzhiyun 	return instance->map + ep;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
suspend_mapping(struct pci_dev * pdev)181*4882a593Smuzhiyun static void suspend_mapping(struct pci_dev *pdev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct sta2x11_mapping *map = sta2x11_pdev_to_mapping(pdev);
184*4882a593Smuzhiyun 	int i;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	if (!map)
187*4882a593Smuzhiyun 		return;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	if (map->is_suspended)
190*4882a593Smuzhiyun 		return;
191*4882a593Smuzhiyun 	map->is_suspended = 1;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* Save all window configs */
194*4882a593Smuzhiyun 	for (i = 0; i < STA2X11_NR_FUNCS; i++) {
195*4882a593Smuzhiyun 		struct sta2x11_ahb_regs *regs = map->regs + i;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 		pci_read_config_dword(pdev, AHB_BASE(i), &regs->base);
198*4882a593Smuzhiyun 		pci_read_config_dword(pdev, AHB_PEXLBASE(i), &regs->pexlbase);
199*4882a593Smuzhiyun 		pci_read_config_dword(pdev, AHB_PEXHBASE(i), &regs->pexhbase);
200*4882a593Smuzhiyun 		pci_read_config_dword(pdev, AHB_CRW(i), &regs->crw);
201*4882a593Smuzhiyun 	}
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, suspend_mapping);
204*4882a593Smuzhiyun 
resume_mapping(struct pci_dev * pdev)205*4882a593Smuzhiyun static void resume_mapping(struct pci_dev *pdev)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	struct sta2x11_mapping *map = sta2x11_pdev_to_mapping(pdev);
208*4882a593Smuzhiyun 	int i;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	if (!map)
211*4882a593Smuzhiyun 		return;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	if (!map->is_suspended)
215*4882a593Smuzhiyun 		goto out;
216*4882a593Smuzhiyun 	map->is_suspended = 0;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	/* Restore all window configs */
219*4882a593Smuzhiyun 	for (i = 0; i < STA2X11_NR_FUNCS; i++) {
220*4882a593Smuzhiyun 		struct sta2x11_ahb_regs *regs = map->regs + i;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 		pci_write_config_dword(pdev, AHB_BASE(i), regs->base);
223*4882a593Smuzhiyun 		pci_write_config_dword(pdev, AHB_PEXLBASE(i), regs->pexlbase);
224*4882a593Smuzhiyun 		pci_write_config_dword(pdev, AHB_PEXHBASE(i), regs->pexhbase);
225*4882a593Smuzhiyun 		pci_write_config_dword(pdev, AHB_CRW(i), regs->crw);
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun out:
228*4882a593Smuzhiyun 	pci_set_master(pdev); /* Like at boot, enable master on all devices */
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, resume_mapping);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun #endif /* CONFIG_PM */
233