1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Numascale NumaConnect-specific PCI code
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012 Numascale AS. All rights reserved.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Send feedback to <support@numascale.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * PCI accessor functions derived from mmconfig_64.c
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <asm/pci_x86.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static u8 limit __read_mostly;
17*4882a593Smuzhiyun
pci_dev_base(unsigned int seg,unsigned int bus,unsigned int devfn)18*4882a593Smuzhiyun static inline char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun if (cfg && cfg->virt)
23*4882a593Smuzhiyun return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
24*4882a593Smuzhiyun return NULL;
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
pci_mmcfg_read_numachip(unsigned int seg,unsigned int bus,unsigned int devfn,int reg,int len,u32 * value)27*4882a593Smuzhiyun static int pci_mmcfg_read_numachip(unsigned int seg, unsigned int bus,
28*4882a593Smuzhiyun unsigned int devfn, int reg, int len, u32 *value)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun char __iomem *addr;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
33*4882a593Smuzhiyun if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
34*4882a593Smuzhiyun err: *value = -1;
35*4882a593Smuzhiyun return -EINVAL;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Ensure AMD Northbridges don't decode reads to other devices */
39*4882a593Smuzhiyun if (unlikely(bus == 0 && devfn >= limit)) {
40*4882a593Smuzhiyun *value = -1;
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun rcu_read_lock();
45*4882a593Smuzhiyun addr = pci_dev_base(seg, bus, devfn);
46*4882a593Smuzhiyun if (!addr) {
47*4882a593Smuzhiyun rcu_read_unlock();
48*4882a593Smuzhiyun goto err;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun switch (len) {
52*4882a593Smuzhiyun case 1:
53*4882a593Smuzhiyun *value = mmio_config_readb(addr + reg);
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case 2:
56*4882a593Smuzhiyun *value = mmio_config_readw(addr + reg);
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case 4:
59*4882a593Smuzhiyun *value = mmio_config_readl(addr + reg);
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun rcu_read_unlock();
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
pci_mmcfg_write_numachip(unsigned int seg,unsigned int bus,unsigned int devfn,int reg,int len,u32 value)67*4882a593Smuzhiyun static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus,
68*4882a593Smuzhiyun unsigned int devfn, int reg, int len, u32 value)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun char __iomem *addr;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
73*4882a593Smuzhiyun if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
74*4882a593Smuzhiyun return -EINVAL;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Ensure AMD Northbridges don't decode writes to other devices */
77*4882a593Smuzhiyun if (unlikely(bus == 0 && devfn >= limit))
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun rcu_read_lock();
81*4882a593Smuzhiyun addr = pci_dev_base(seg, bus, devfn);
82*4882a593Smuzhiyun if (!addr) {
83*4882a593Smuzhiyun rcu_read_unlock();
84*4882a593Smuzhiyun return -EINVAL;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun switch (len) {
88*4882a593Smuzhiyun case 1:
89*4882a593Smuzhiyun mmio_config_writeb(addr + reg, value);
90*4882a593Smuzhiyun break;
91*4882a593Smuzhiyun case 2:
92*4882a593Smuzhiyun mmio_config_writew(addr + reg, value);
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun case 4:
95*4882a593Smuzhiyun mmio_config_writel(addr + reg, value);
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun rcu_read_unlock();
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct pci_raw_ops pci_mmcfg_numachip = {
104*4882a593Smuzhiyun .read = pci_mmcfg_read_numachip,
105*4882a593Smuzhiyun .write = pci_mmcfg_write_numachip,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
pci_numachip_init(void)108*4882a593Smuzhiyun int __init pci_numachip_init(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun int ret = 0;
111*4882a593Smuzhiyun u32 val;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* For remote I/O, restrict bus 0 access to the actual number of AMD
114*4882a593Smuzhiyun Northbridges, which starts at device number 0x18 */
115*4882a593Smuzhiyun ret = raw_pci_read(0, 0, PCI_DEVFN(0x18, 0), 0x60, sizeof(val), &val);
116*4882a593Smuzhiyun if (ret)
117*4882a593Smuzhiyun goto out;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* HyperTransport fabric size in bits 6:4 */
120*4882a593Smuzhiyun limit = PCI_DEVFN(0x18 + ((val >> 4) & 7) + 1, 0);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* Use NumaChip PCI accessors for non-extended and extended access */
123*4882a593Smuzhiyun raw_pci_ops = raw_pci_ext_ops = &pci_mmcfg_numachip;
124*4882a593Smuzhiyun out:
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun }
127