xref: /OK3568_Linux_fs/kernel/arch/x86/pci/mmconfig_64.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This is an 64bit optimized version that always keeps the full mmconfig
6*4882a593Smuzhiyun  * space mapped. This allows lockless config space operation.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/pci.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/acpi.h>
12*4882a593Smuzhiyun #include <linux/bitmap.h>
13*4882a593Smuzhiyun #include <linux/rcupdate.h>
14*4882a593Smuzhiyun #include <asm/e820/api.h>
15*4882a593Smuzhiyun #include <asm/pci_x86.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define PREFIX "PCI: "
18*4882a593Smuzhiyun 
pci_dev_base(unsigned int seg,unsigned int bus,unsigned int devfn)19*4882a593Smuzhiyun static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun 	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	if (cfg && cfg->virt)
24*4882a593Smuzhiyun 		return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
25*4882a593Smuzhiyun 	return NULL;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun 
pci_mmcfg_read(unsigned int seg,unsigned int bus,unsigned int devfn,int reg,int len,u32 * value)28*4882a593Smuzhiyun static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
29*4882a593Smuzhiyun 			  unsigned int devfn, int reg, int len, u32 *value)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun 	char __iomem *addr;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
34*4882a593Smuzhiyun 	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
35*4882a593Smuzhiyun err:		*value = -1;
36*4882a593Smuzhiyun 		return -EINVAL;
37*4882a593Smuzhiyun 	}
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	rcu_read_lock();
40*4882a593Smuzhiyun 	addr = pci_dev_base(seg, bus, devfn);
41*4882a593Smuzhiyun 	if (!addr) {
42*4882a593Smuzhiyun 		rcu_read_unlock();
43*4882a593Smuzhiyun 		goto err;
44*4882a593Smuzhiyun 	}
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	switch (len) {
47*4882a593Smuzhiyun 	case 1:
48*4882a593Smuzhiyun 		*value = mmio_config_readb(addr + reg);
49*4882a593Smuzhiyun 		break;
50*4882a593Smuzhiyun 	case 2:
51*4882a593Smuzhiyun 		*value = mmio_config_readw(addr + reg);
52*4882a593Smuzhiyun 		break;
53*4882a593Smuzhiyun 	case 4:
54*4882a593Smuzhiyun 		*value = mmio_config_readl(addr + reg);
55*4882a593Smuzhiyun 		break;
56*4882a593Smuzhiyun 	}
57*4882a593Smuzhiyun 	rcu_read_unlock();
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
pci_mmcfg_write(unsigned int seg,unsigned int bus,unsigned int devfn,int reg,int len,u32 value)62*4882a593Smuzhiyun static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
63*4882a593Smuzhiyun 			   unsigned int devfn, int reg, int len, u32 value)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	char __iomem *addr;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
68*4882a593Smuzhiyun 	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
69*4882a593Smuzhiyun 		return -EINVAL;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	rcu_read_lock();
72*4882a593Smuzhiyun 	addr = pci_dev_base(seg, bus, devfn);
73*4882a593Smuzhiyun 	if (!addr) {
74*4882a593Smuzhiyun 		rcu_read_unlock();
75*4882a593Smuzhiyun 		return -EINVAL;
76*4882a593Smuzhiyun 	}
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	switch (len) {
79*4882a593Smuzhiyun 	case 1:
80*4882a593Smuzhiyun 		mmio_config_writeb(addr + reg, value);
81*4882a593Smuzhiyun 		break;
82*4882a593Smuzhiyun 	case 2:
83*4882a593Smuzhiyun 		mmio_config_writew(addr + reg, value);
84*4882a593Smuzhiyun 		break;
85*4882a593Smuzhiyun 	case 4:
86*4882a593Smuzhiyun 		mmio_config_writel(addr + reg, value);
87*4882a593Smuzhiyun 		break;
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 	rcu_read_unlock();
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun const struct pci_raw_ops pci_mmcfg = {
95*4882a593Smuzhiyun 	.read =		pci_mmcfg_read,
96*4882a593Smuzhiyun 	.write =	pci_mmcfg_write,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
mcfg_ioremap(struct pci_mmcfg_region * cfg)99*4882a593Smuzhiyun static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	void __iomem *addr;
102*4882a593Smuzhiyun 	u64 start, size;
103*4882a593Smuzhiyun 	int num_buses;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
106*4882a593Smuzhiyun 	num_buses = cfg->end_bus - cfg->start_bus + 1;
107*4882a593Smuzhiyun 	size = PCI_MMCFG_BUS_OFFSET(num_buses);
108*4882a593Smuzhiyun 	addr = ioremap(start, size);
109*4882a593Smuzhiyun 	if (addr)
110*4882a593Smuzhiyun 		addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
111*4882a593Smuzhiyun 	return addr;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
pci_mmcfg_arch_init(void)114*4882a593Smuzhiyun int __init pci_mmcfg_arch_init(void)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	struct pci_mmcfg_region *cfg;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	list_for_each_entry(cfg, &pci_mmcfg_list, list)
119*4882a593Smuzhiyun 		if (pci_mmcfg_arch_map(cfg)) {
120*4882a593Smuzhiyun 			pci_mmcfg_arch_free();
121*4882a593Smuzhiyun 			return 0;
122*4882a593Smuzhiyun 		}
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	raw_pci_ext_ops = &pci_mmcfg;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	return 1;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
pci_mmcfg_arch_free(void)129*4882a593Smuzhiyun void __init pci_mmcfg_arch_free(void)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	struct pci_mmcfg_region *cfg;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	list_for_each_entry(cfg, &pci_mmcfg_list, list)
134*4882a593Smuzhiyun 		pci_mmcfg_arch_unmap(cfg);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
pci_mmcfg_arch_map(struct pci_mmcfg_region * cfg)137*4882a593Smuzhiyun int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	cfg->virt = mcfg_ioremap(cfg);
140*4882a593Smuzhiyun 	if (!cfg->virt) {
141*4882a593Smuzhiyun 		pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
142*4882a593Smuzhiyun 		return -ENOMEM;
143*4882a593Smuzhiyun 	}
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
pci_mmcfg_arch_unmap(struct pci_mmcfg_region * cfg)148*4882a593Smuzhiyun void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	if (cfg && cfg->virt) {
151*4882a593Smuzhiyun 		iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
152*4882a593Smuzhiyun 		cfg->virt = NULL;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun }
155