1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /*---------------------------------------------------------------------------+ 3*4882a593Smuzhiyun | status_w.h | 4*4882a593Smuzhiyun | | 5*4882a593Smuzhiyun | Copyright (C) 1992,1993 | 6*4882a593Smuzhiyun | W. Metzenthen, 22 Parker St, Ormond, Vic 3163, | 7*4882a593Smuzhiyun | Australia. E-mail billm@vaxc.cc.monash.edu.au | 8*4882a593Smuzhiyun | | 9*4882a593Smuzhiyun +---------------------------------------------------------------------------*/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _STATUS_H_ 12*4882a593Smuzhiyun #define _STATUS_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "fpu_emu.h" /* for definition of PECULIAR_486 */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 17*4882a593Smuzhiyun #define Const__(x) $##x 18*4882a593Smuzhiyun #else 19*4882a593Smuzhiyun #define Const__(x) x 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define SW_Backward Const__(0x8000) /* backward compatibility */ 23*4882a593Smuzhiyun #define SW_C3 Const__(0x4000) /* condition bit 3 */ 24*4882a593Smuzhiyun #define SW_Top Const__(0x3800) /* top of stack */ 25*4882a593Smuzhiyun #define SW_Top_Shift Const__(11) /* shift for top of stack bits */ 26*4882a593Smuzhiyun #define SW_C2 Const__(0x0400) /* condition bit 2 */ 27*4882a593Smuzhiyun #define SW_C1 Const__(0x0200) /* condition bit 1 */ 28*4882a593Smuzhiyun #define SW_C0 Const__(0x0100) /* condition bit 0 */ 29*4882a593Smuzhiyun #define SW_Summary Const__(0x0080) /* exception summary */ 30*4882a593Smuzhiyun #define SW_Stack_Fault Const__(0x0040) /* stack fault */ 31*4882a593Smuzhiyun #define SW_Precision Const__(0x0020) /* loss of precision */ 32*4882a593Smuzhiyun #define SW_Underflow Const__(0x0010) /* underflow */ 33*4882a593Smuzhiyun #define SW_Overflow Const__(0x0008) /* overflow */ 34*4882a593Smuzhiyun #define SW_Zero_Div Const__(0x0004) /* divide by zero */ 35*4882a593Smuzhiyun #define SW_Denorm_Op Const__(0x0002) /* denormalized operand */ 36*4882a593Smuzhiyun #define SW_Invalid Const__(0x0001) /* invalid operation */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define SW_Exc_Mask Const__(0x27f) /* Status word exception bit mask */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define COMP_A_gt_B 1 43*4882a593Smuzhiyun #define COMP_A_eq_B 2 44*4882a593Smuzhiyun #define COMP_A_lt_B 3 45*4882a593Smuzhiyun #define COMP_No_Comp 4 46*4882a593Smuzhiyun #define COMP_Denormal 0x20 47*4882a593Smuzhiyun #define COMP_NaN 0x40 48*4882a593Smuzhiyun #define COMP_SNaN 0x80 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define status_word() \ 51*4882a593Smuzhiyun ((partial_status & ~SW_Top & 0xffff) | ((top << SW_Top_Shift) & SW_Top)) setcc(int cc)52*4882a593Smuzhiyunstatic inline void setcc(int cc) 53*4882a593Smuzhiyun { 54*4882a593Smuzhiyun partial_status &= ~(SW_C0 | SW_C1 | SW_C2 | SW_C3); 55*4882a593Smuzhiyun partial_status |= (cc) & (SW_C0 | SW_C1 | SW_C2 | SW_C3); 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef PECULIAR_486 59*4882a593Smuzhiyun /* Default, this conveys no information, but an 80486 does it. */ 60*4882a593Smuzhiyun /* Clear the SW_C1 bit, "other bits undefined". */ 61*4882a593Smuzhiyun # define clear_C1() { partial_status &= ~SW_C1; } 62*4882a593Smuzhiyun # else 63*4882a593Smuzhiyun # define clear_C1() 64*4882a593Smuzhiyun #endif /* PECULIAR_486 */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _STATUS_H_ */ 69