1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun .file "shr_Xsig.S" 3*4882a593Smuzhiyun/*---------------------------------------------------------------------------+ 4*4882a593Smuzhiyun | shr_Xsig.S | 5*4882a593Smuzhiyun | | 6*4882a593Smuzhiyun | 12 byte right shift function | 7*4882a593Smuzhiyun | | 8*4882a593Smuzhiyun | Copyright (C) 1992,1994,1995 | 9*4882a593Smuzhiyun | W. Metzenthen, 22 Parker St, Ormond, Vic 3163, | 10*4882a593Smuzhiyun | Australia. E-mail billm@jacobi.maths.monash.edu.au | 11*4882a593Smuzhiyun | | 12*4882a593Smuzhiyun | Call from C as: | 13*4882a593Smuzhiyun | void shr_Xsig(Xsig *arg, unsigned nr) | 14*4882a593Smuzhiyun | | 15*4882a593Smuzhiyun | Extended shift right function. | 16*4882a593Smuzhiyun | Fastest for small shifts. | 17*4882a593Smuzhiyun | Shifts the 12 byte quantity pointed to by the first arg (arg) | 18*4882a593Smuzhiyun | right by the number of bits specified by the second arg (nr). | 19*4882a593Smuzhiyun | | 20*4882a593Smuzhiyun +---------------------------------------------------------------------------*/ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun#include "fpu_emu.h" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun.text 25*4882a593SmuzhiyunSYM_FUNC_START(shr_Xsig) 26*4882a593Smuzhiyun push %ebp 27*4882a593Smuzhiyun movl %esp,%ebp 28*4882a593Smuzhiyun pushl %esi 29*4882a593Smuzhiyun movl PARAM2,%ecx 30*4882a593Smuzhiyun movl PARAM1,%esi 31*4882a593Smuzhiyun cmpl $32,%ecx /* shrd only works for 0..31 bits */ 32*4882a593Smuzhiyun jnc L_more_than_31 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun/* less than 32 bits */ 35*4882a593Smuzhiyun pushl %ebx 36*4882a593Smuzhiyun movl (%esi),%eax /* lsl */ 37*4882a593Smuzhiyun movl 4(%esi),%ebx /* midl */ 38*4882a593Smuzhiyun movl 8(%esi),%edx /* msl */ 39*4882a593Smuzhiyun shrd %cl,%ebx,%eax 40*4882a593Smuzhiyun shrd %cl,%edx,%ebx 41*4882a593Smuzhiyun shr %cl,%edx 42*4882a593Smuzhiyun movl %eax,(%esi) 43*4882a593Smuzhiyun movl %ebx,4(%esi) 44*4882a593Smuzhiyun movl %edx,8(%esi) 45*4882a593Smuzhiyun popl %ebx 46*4882a593Smuzhiyun popl %esi 47*4882a593Smuzhiyun leave 48*4882a593Smuzhiyun RET 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunL_more_than_31: 51*4882a593Smuzhiyun cmpl $64,%ecx 52*4882a593Smuzhiyun jnc L_more_than_63 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun subb $32,%cl 55*4882a593Smuzhiyun movl 4(%esi),%eax /* midl */ 56*4882a593Smuzhiyun movl 8(%esi),%edx /* msl */ 57*4882a593Smuzhiyun shrd %cl,%edx,%eax 58*4882a593Smuzhiyun shr %cl,%edx 59*4882a593Smuzhiyun movl %eax,(%esi) 60*4882a593Smuzhiyun movl %edx,4(%esi) 61*4882a593Smuzhiyun movl $0,8(%esi) 62*4882a593Smuzhiyun popl %esi 63*4882a593Smuzhiyun leave 64*4882a593Smuzhiyun RET 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunL_more_than_63: 67*4882a593Smuzhiyun cmpl $96,%ecx 68*4882a593Smuzhiyun jnc L_more_than_95 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun subb $64,%cl 71*4882a593Smuzhiyun movl 8(%esi),%eax /* msl */ 72*4882a593Smuzhiyun shr %cl,%eax 73*4882a593Smuzhiyun xorl %edx,%edx 74*4882a593Smuzhiyun movl %eax,(%esi) 75*4882a593Smuzhiyun movl %edx,4(%esi) 76*4882a593Smuzhiyun movl %edx,8(%esi) 77*4882a593Smuzhiyun popl %esi 78*4882a593Smuzhiyun leave 79*4882a593Smuzhiyun RET 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunL_more_than_95: 82*4882a593Smuzhiyun xorl %eax,%eax 83*4882a593Smuzhiyun movl %eax,(%esi) 84*4882a593Smuzhiyun movl %eax,4(%esi) 85*4882a593Smuzhiyun movl %eax,8(%esi) 86*4882a593Smuzhiyun popl %esi 87*4882a593Smuzhiyun leave 88*4882a593Smuzhiyun RET 89*4882a593SmuzhiyunSYM_FUNC_END(shr_Xsig) 90