1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /*---------------------------------------------------------------------------+ 3*4882a593Smuzhiyun | control_w.h | 4*4882a593Smuzhiyun | | 5*4882a593Smuzhiyun | Copyright (C) 1992,1993 | 6*4882a593Smuzhiyun | W. Metzenthen, 22 Parker St, Ormond, Vic 3163, | 7*4882a593Smuzhiyun | Australia. E-mail billm@vaxc.cc.monash.edu.au | 8*4882a593Smuzhiyun | | 9*4882a593Smuzhiyun +---------------------------------------------------------------------------*/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _CONTROLW_H_ 12*4882a593Smuzhiyun #define _CONTROLW_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 15*4882a593Smuzhiyun #define _Const_(x) $##x 16*4882a593Smuzhiyun #else 17*4882a593Smuzhiyun #define _Const_(x) x 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CW_RC _Const_(0x0C00) /* rounding control */ 21*4882a593Smuzhiyun #define CW_PC _Const_(0x0300) /* precision control */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CW_Precision Const_(0x0020) /* loss of precision mask */ 24*4882a593Smuzhiyun #define CW_Underflow Const_(0x0010) /* underflow mask */ 25*4882a593Smuzhiyun #define CW_Overflow Const_(0x0008) /* overflow mask */ 26*4882a593Smuzhiyun #define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */ 27*4882a593Smuzhiyun #define CW_Denormal Const_(0x0002) /* denormalized operand mask */ 28*4882a593Smuzhiyun #define CW_Invalid Const_(0x0001) /* invalid operation mask */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CW_Exceptions _Const_(0x003f) /* all masks */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define RC_RND _Const_(0x0000) 33*4882a593Smuzhiyun #define RC_DOWN _Const_(0x0400) 34*4882a593Smuzhiyun #define RC_UP _Const_(0x0800) 35*4882a593Smuzhiyun #define RC_CHOP _Const_(0x0C00) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* p 15-5: Precision control bits affect only the following: 38*4882a593Smuzhiyun ADD, SUB(R), MUL, DIV(R), and SQRT */ 39*4882a593Smuzhiyun #define PR_24_BITS _Const_(0x000) 40*4882a593Smuzhiyun #define PR_53_BITS _Const_(0x200) 41*4882a593Smuzhiyun #define PR_64_BITS _Const_(0x300) 42*4882a593Smuzhiyun #define PR_RESERVED_BITS _Const_(0x100) 43*4882a593Smuzhiyun /* FULL_PRECISION simulates all exceptions masked */ 44*4882a593Smuzhiyun #define FULL_PRECISION (PR_64_BITS | RC_RND | 0x3f) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* _CONTROLW_H_ */ 47