1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __KVM_IO_APIC_H
3*4882a593Smuzhiyun #define __KVM_IO_APIC_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/kvm_host.h>
6*4882a593Smuzhiyun #include <kvm/iodev.h>
7*4882a593Smuzhiyun #include "irq.h"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun struct kvm;
10*4882a593Smuzhiyun struct kvm_vcpu;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS
13*4882a593Smuzhiyun #define MAX_NR_RESERVED_IOAPIC_PINS KVM_MAX_IRQ_ROUTES
14*4882a593Smuzhiyun #define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
15*4882a593Smuzhiyun #define IOAPIC_EDGE_TRIG 0
16*4882a593Smuzhiyun #define IOAPIC_LEVEL_TRIG 1
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
19*4882a593Smuzhiyun #define IOAPIC_MEM_LENGTH 0x100
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Direct registers. */
22*4882a593Smuzhiyun #define IOAPIC_REG_SELECT 0x00
23*4882a593Smuzhiyun #define IOAPIC_REG_WINDOW 0x10
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Indirect registers. */
26*4882a593Smuzhiyun #define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
27*4882a593Smuzhiyun #define IOAPIC_REG_VERSION 0x01
28*4882a593Smuzhiyun #define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*ioapic delivery mode*/
31*4882a593Smuzhiyun #define IOAPIC_FIXED 0x0
32*4882a593Smuzhiyun #define IOAPIC_LOWEST_PRIORITY 0x1
33*4882a593Smuzhiyun #define IOAPIC_PMI 0x2
34*4882a593Smuzhiyun #define IOAPIC_NMI 0x4
35*4882a593Smuzhiyun #define IOAPIC_INIT 0x5
36*4882a593Smuzhiyun #define IOAPIC_EXTINT 0x7
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifdef CONFIG_X86
39*4882a593Smuzhiyun #define RTC_GSI 8
40*4882a593Smuzhiyun #else
41*4882a593Smuzhiyun #define RTC_GSI -1U
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct dest_map {
45*4882a593Smuzhiyun /* vcpu bitmap where IRQ has been sent */
46*4882a593Smuzhiyun DECLARE_BITMAP(map, KVM_MAX_VCPU_ID);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Vector sent to a given vcpu, only valid when
50*4882a593Smuzhiyun * the vcpu's bit in map is set
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun u8 vectors[KVM_MAX_VCPU_ID];
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun struct rtc_status {
57*4882a593Smuzhiyun int pending_eoi;
58*4882a593Smuzhiyun struct dest_map dest_map;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun union kvm_ioapic_redirect_entry {
62*4882a593Smuzhiyun u64 bits;
63*4882a593Smuzhiyun struct {
64*4882a593Smuzhiyun u8 vector;
65*4882a593Smuzhiyun u8 delivery_mode:3;
66*4882a593Smuzhiyun u8 dest_mode:1;
67*4882a593Smuzhiyun u8 delivery_status:1;
68*4882a593Smuzhiyun u8 polarity:1;
69*4882a593Smuzhiyun u8 remote_irr:1;
70*4882a593Smuzhiyun u8 trig_mode:1;
71*4882a593Smuzhiyun u8 mask:1;
72*4882a593Smuzhiyun u8 reserve:7;
73*4882a593Smuzhiyun u8 reserved[4];
74*4882a593Smuzhiyun u8 dest_id;
75*4882a593Smuzhiyun } fields;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun struct kvm_ioapic {
79*4882a593Smuzhiyun u64 base_address;
80*4882a593Smuzhiyun u32 ioregsel;
81*4882a593Smuzhiyun u32 id;
82*4882a593Smuzhiyun u32 irr;
83*4882a593Smuzhiyun u32 pad;
84*4882a593Smuzhiyun union kvm_ioapic_redirect_entry redirtbl[IOAPIC_NUM_PINS];
85*4882a593Smuzhiyun unsigned long irq_states[IOAPIC_NUM_PINS];
86*4882a593Smuzhiyun struct kvm_io_device dev;
87*4882a593Smuzhiyun struct kvm *kvm;
88*4882a593Smuzhiyun void (*ack_notifier)(void *opaque, int irq);
89*4882a593Smuzhiyun spinlock_t lock;
90*4882a593Smuzhiyun struct rtc_status rtc_status;
91*4882a593Smuzhiyun struct delayed_work eoi_inject;
92*4882a593Smuzhiyun u32 irq_eoi[IOAPIC_NUM_PINS];
93*4882a593Smuzhiyun u32 irr_delivered;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #ifdef DEBUG
97*4882a593Smuzhiyun #define ASSERT(x) \
98*4882a593Smuzhiyun do { \
99*4882a593Smuzhiyun if (!(x)) { \
100*4882a593Smuzhiyun printk(KERN_EMERG "assertion failed %s: %d: %s\n", \
101*4882a593Smuzhiyun __FILE__, __LINE__, #x); \
102*4882a593Smuzhiyun BUG(); \
103*4882a593Smuzhiyun } \
104*4882a593Smuzhiyun } while (0)
105*4882a593Smuzhiyun #else
106*4882a593Smuzhiyun #define ASSERT(x) do { } while (0)
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun
ioapic_in_kernel(struct kvm * kvm)109*4882a593Smuzhiyun static inline int ioapic_in_kernel(struct kvm *kvm)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun return irqchip_kernel(kvm);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu);
115*4882a593Smuzhiyun void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector,
116*4882a593Smuzhiyun int trigger_mode);
117*4882a593Smuzhiyun int kvm_ioapic_init(struct kvm *kvm);
118*4882a593Smuzhiyun void kvm_ioapic_destroy(struct kvm *kvm);
119*4882a593Smuzhiyun int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
120*4882a593Smuzhiyun int level, bool line_status);
121*4882a593Smuzhiyun void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id);
122*4882a593Smuzhiyun void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
123*4882a593Smuzhiyun void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
124*4882a593Smuzhiyun void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu,
125*4882a593Smuzhiyun ulong *ioapic_handled_vectors);
126*4882a593Smuzhiyun void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu,
127*4882a593Smuzhiyun ulong *ioapic_handled_vectors);
128*4882a593Smuzhiyun #endif
129