1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 1991,1992,1995 Linus Torvalds
4*4882a593Smuzhiyun * Copyright (c) 1994 Alan Modra
5*4882a593Smuzhiyun * Copyright (c) 1995 Markus Kuhn
6*4882a593Smuzhiyun * Copyright (c) 1996 Ingo Molnar
7*4882a593Smuzhiyun * Copyright (c) 1998 Andrea Arcangeli
8*4882a593Smuzhiyun * Copyright (c) 2002,2006 Vojtech Pavlik
9*4882a593Smuzhiyun * Copyright (c) 2003 Andi Kleen
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clocksource.h>
14*4882a593Smuzhiyun #include <linux/clockchips.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/i8253.h>
18*4882a593Smuzhiyun #include <linux/time.h>
19*4882a593Smuzhiyun #include <linux/export.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <asm/vsyscall.h>
22*4882a593Smuzhiyun #include <asm/x86_init.h>
23*4882a593Smuzhiyun #include <asm/i8259.h>
24*4882a593Smuzhiyun #include <asm/timer.h>
25*4882a593Smuzhiyun #include <asm/hpet.h>
26*4882a593Smuzhiyun #include <asm/time.h>
27*4882a593Smuzhiyun
profile_pc(struct pt_regs * regs)28*4882a593Smuzhiyun unsigned long profile_pc(struct pt_regs *regs)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun unsigned long pc = instruction_pointer(regs);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun if (!user_mode(regs) && in_lock_functions(pc)) {
33*4882a593Smuzhiyun #ifdef CONFIG_FRAME_POINTER
34*4882a593Smuzhiyun return *(unsigned long *)(regs->bp + sizeof(long));
35*4882a593Smuzhiyun #else
36*4882a593Smuzhiyun unsigned long *sp = (unsigned long *)regs->sp;
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Return address is either directly at stack pointer
39*4882a593Smuzhiyun * or above a saved flags. Eflags has bits 22-31 zero,
40*4882a593Smuzhiyun * kernel addresses don't.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun if (sp[0] >> 22)
43*4882a593Smuzhiyun return sp[0];
44*4882a593Smuzhiyun if (sp[1] >> 22)
45*4882a593Smuzhiyun return sp[1];
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun return pc;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun EXPORT_SYMBOL(profile_pc);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * Default timer interrupt handler for PIT/HPET
54*4882a593Smuzhiyun */
timer_interrupt(int irq,void * dev_id)55*4882a593Smuzhiyun static irqreturn_t timer_interrupt(int irq, void *dev_id)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun global_clock_event->event_handler(global_clock_event);
58*4882a593Smuzhiyun return IRQ_HANDLED;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
setup_default_timer_irq(void)61*4882a593Smuzhiyun static void __init setup_default_timer_irq(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun unsigned long flags = IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * Unconditionally register the legacy timer interrupt; even
67*4882a593Smuzhiyun * without legacy PIC/PIT we need this for the HPET0 in legacy
68*4882a593Smuzhiyun * replacement mode.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun if (request_irq(0, timer_interrupt, flags, "timer", NULL))
71*4882a593Smuzhiyun pr_info("Failed to register legacy timer interrupt\n");
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Default timer init function */
hpet_time_init(void)75*4882a593Smuzhiyun void __init hpet_time_init(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun if (!hpet_enable()) {
78*4882a593Smuzhiyun if (!pit_timer_init())
79*4882a593Smuzhiyun return;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun setup_default_timer_irq();
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
x86_late_time_init(void)85*4882a593Smuzhiyun static __init void x86_late_time_init(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * Before PIT/HPET init, select the interrupt mode. This is required
89*4882a593Smuzhiyun * to make the decision whether PIT should be initialized correct.
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun x86_init.irqs.intr_mode_select();
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* Setup the legacy timers */
94*4882a593Smuzhiyun x86_init.timers.timer_init();
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * After PIT/HPET timers init, set up the final interrupt mode for
98*4882a593Smuzhiyun * delivering IRQs.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun x86_init.irqs.intr_mode_init();
101*4882a593Smuzhiyun tsc_init();
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (static_cpu_has(X86_FEATURE_WAITPKG))
104*4882a593Smuzhiyun use_tpause_delay();
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Initialize TSC and delay the periodic timer init to
109*4882a593Smuzhiyun * late x86_late_time_init() so ioremap works.
110*4882a593Smuzhiyun */
time_init(void)111*4882a593Smuzhiyun void __init time_init(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun late_time_init = x86_late_time_init;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /*
117*4882a593Smuzhiyun * Sanity check the vdso related archdata content.
118*4882a593Smuzhiyun */
clocksource_arch_init(struct clocksource * cs)119*4882a593Smuzhiyun void clocksource_arch_init(struct clocksource *cs)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun if (cs->vdso_clock_mode == VDSO_CLOCKMODE_NONE)
122*4882a593Smuzhiyun return;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (cs->mask != CLOCKSOURCE_MASK(64)) {
125*4882a593Smuzhiyun pr_warn("clocksource %s registered with invalid mask %016llx for VDSO. Disabling VDSO support.\n",
126*4882a593Smuzhiyun cs->name, cs->mask);
127*4882a593Smuzhiyun cs->vdso_clock_mode = VDSO_CLOCKMODE_NONE;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun }
130