1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef _UAPI_ASM_X86_PROCESSOR_FLAGS_H 3*4882a593Smuzhiyun #define _UAPI_ASM_X86_PROCESSOR_FLAGS_H 4*4882a593Smuzhiyun /* Various flags defined: can be included from assembler. */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include <linux/const.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * EFLAGS bits 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #define X86_EFLAGS_CF_BIT 0 /* Carry Flag */ 12*4882a593Smuzhiyun #define X86_EFLAGS_CF _BITUL(X86_EFLAGS_CF_BIT) 13*4882a593Smuzhiyun #define X86_EFLAGS_FIXED_BIT 1 /* Bit 1 - always on */ 14*4882a593Smuzhiyun #define X86_EFLAGS_FIXED _BITUL(X86_EFLAGS_FIXED_BIT) 15*4882a593Smuzhiyun #define X86_EFLAGS_PF_BIT 2 /* Parity Flag */ 16*4882a593Smuzhiyun #define X86_EFLAGS_PF _BITUL(X86_EFLAGS_PF_BIT) 17*4882a593Smuzhiyun #define X86_EFLAGS_AF_BIT 4 /* Auxiliary carry Flag */ 18*4882a593Smuzhiyun #define X86_EFLAGS_AF _BITUL(X86_EFLAGS_AF_BIT) 19*4882a593Smuzhiyun #define X86_EFLAGS_ZF_BIT 6 /* Zero Flag */ 20*4882a593Smuzhiyun #define X86_EFLAGS_ZF _BITUL(X86_EFLAGS_ZF_BIT) 21*4882a593Smuzhiyun #define X86_EFLAGS_SF_BIT 7 /* Sign Flag */ 22*4882a593Smuzhiyun #define X86_EFLAGS_SF _BITUL(X86_EFLAGS_SF_BIT) 23*4882a593Smuzhiyun #define X86_EFLAGS_TF_BIT 8 /* Trap Flag */ 24*4882a593Smuzhiyun #define X86_EFLAGS_TF _BITUL(X86_EFLAGS_TF_BIT) 25*4882a593Smuzhiyun #define X86_EFLAGS_IF_BIT 9 /* Interrupt Flag */ 26*4882a593Smuzhiyun #define X86_EFLAGS_IF _BITUL(X86_EFLAGS_IF_BIT) 27*4882a593Smuzhiyun #define X86_EFLAGS_DF_BIT 10 /* Direction Flag */ 28*4882a593Smuzhiyun #define X86_EFLAGS_DF _BITUL(X86_EFLAGS_DF_BIT) 29*4882a593Smuzhiyun #define X86_EFLAGS_OF_BIT 11 /* Overflow Flag */ 30*4882a593Smuzhiyun #define X86_EFLAGS_OF _BITUL(X86_EFLAGS_OF_BIT) 31*4882a593Smuzhiyun #define X86_EFLAGS_IOPL_BIT 12 /* I/O Privilege Level (2 bits) */ 32*4882a593Smuzhiyun #define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT) 33*4882a593Smuzhiyun #define X86_EFLAGS_NT_BIT 14 /* Nested Task */ 34*4882a593Smuzhiyun #define X86_EFLAGS_NT _BITUL(X86_EFLAGS_NT_BIT) 35*4882a593Smuzhiyun #define X86_EFLAGS_RF_BIT 16 /* Resume Flag */ 36*4882a593Smuzhiyun #define X86_EFLAGS_RF _BITUL(X86_EFLAGS_RF_BIT) 37*4882a593Smuzhiyun #define X86_EFLAGS_VM_BIT 17 /* Virtual Mode */ 38*4882a593Smuzhiyun #define X86_EFLAGS_VM _BITUL(X86_EFLAGS_VM_BIT) 39*4882a593Smuzhiyun #define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */ 40*4882a593Smuzhiyun #define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT) 41*4882a593Smuzhiyun #define X86_EFLAGS_VIF_BIT 19 /* Virtual Interrupt Flag */ 42*4882a593Smuzhiyun #define X86_EFLAGS_VIF _BITUL(X86_EFLAGS_VIF_BIT) 43*4882a593Smuzhiyun #define X86_EFLAGS_VIP_BIT 20 /* Virtual Interrupt Pending */ 44*4882a593Smuzhiyun #define X86_EFLAGS_VIP _BITUL(X86_EFLAGS_VIP_BIT) 45*4882a593Smuzhiyun #define X86_EFLAGS_ID_BIT 21 /* CPUID detection */ 46*4882a593Smuzhiyun #define X86_EFLAGS_ID _BITUL(X86_EFLAGS_ID_BIT) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Basic CPU control in CR0 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define X86_CR0_PE_BIT 0 /* Protection Enable */ 52*4882a593Smuzhiyun #define X86_CR0_PE _BITUL(X86_CR0_PE_BIT) 53*4882a593Smuzhiyun #define X86_CR0_MP_BIT 1 /* Monitor Coprocessor */ 54*4882a593Smuzhiyun #define X86_CR0_MP _BITUL(X86_CR0_MP_BIT) 55*4882a593Smuzhiyun #define X86_CR0_EM_BIT 2 /* Emulation */ 56*4882a593Smuzhiyun #define X86_CR0_EM _BITUL(X86_CR0_EM_BIT) 57*4882a593Smuzhiyun #define X86_CR0_TS_BIT 3 /* Task Switched */ 58*4882a593Smuzhiyun #define X86_CR0_TS _BITUL(X86_CR0_TS_BIT) 59*4882a593Smuzhiyun #define X86_CR0_ET_BIT 4 /* Extension Type */ 60*4882a593Smuzhiyun #define X86_CR0_ET _BITUL(X86_CR0_ET_BIT) 61*4882a593Smuzhiyun #define X86_CR0_NE_BIT 5 /* Numeric Error */ 62*4882a593Smuzhiyun #define X86_CR0_NE _BITUL(X86_CR0_NE_BIT) 63*4882a593Smuzhiyun #define X86_CR0_WP_BIT 16 /* Write Protect */ 64*4882a593Smuzhiyun #define X86_CR0_WP _BITUL(X86_CR0_WP_BIT) 65*4882a593Smuzhiyun #define X86_CR0_AM_BIT 18 /* Alignment Mask */ 66*4882a593Smuzhiyun #define X86_CR0_AM _BITUL(X86_CR0_AM_BIT) 67*4882a593Smuzhiyun #define X86_CR0_NW_BIT 29 /* Not Write-through */ 68*4882a593Smuzhiyun #define X86_CR0_NW _BITUL(X86_CR0_NW_BIT) 69*4882a593Smuzhiyun #define X86_CR0_CD_BIT 30 /* Cache Disable */ 70*4882a593Smuzhiyun #define X86_CR0_CD _BITUL(X86_CR0_CD_BIT) 71*4882a593Smuzhiyun #define X86_CR0_PG_BIT 31 /* Paging */ 72*4882a593Smuzhiyun #define X86_CR0_PG _BITUL(X86_CR0_PG_BIT) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * Paging options in CR3 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define X86_CR3_PWT_BIT 3 /* Page Write Through */ 78*4882a593Smuzhiyun #define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT) 79*4882a593Smuzhiyun #define X86_CR3_PCD_BIT 4 /* Page Cache Disable */ 80*4882a593Smuzhiyun #define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define X86_CR3_PCID_BITS 12 83*4882a593Smuzhiyun #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ 86*4882a593Smuzhiyun #define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Intel CPU features in CR4 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun #define X86_CR4_VME_BIT 0 /* enable vm86 extensions */ 92*4882a593Smuzhiyun #define X86_CR4_VME _BITUL(X86_CR4_VME_BIT) 93*4882a593Smuzhiyun #define X86_CR4_PVI_BIT 1 /* virtual interrupts flag enable */ 94*4882a593Smuzhiyun #define X86_CR4_PVI _BITUL(X86_CR4_PVI_BIT) 95*4882a593Smuzhiyun #define X86_CR4_TSD_BIT 2 /* disable time stamp at ipl 3 */ 96*4882a593Smuzhiyun #define X86_CR4_TSD _BITUL(X86_CR4_TSD_BIT) 97*4882a593Smuzhiyun #define X86_CR4_DE_BIT 3 /* enable debugging extensions */ 98*4882a593Smuzhiyun #define X86_CR4_DE _BITUL(X86_CR4_DE_BIT) 99*4882a593Smuzhiyun #define X86_CR4_PSE_BIT 4 /* enable page size extensions */ 100*4882a593Smuzhiyun #define X86_CR4_PSE _BITUL(X86_CR4_PSE_BIT) 101*4882a593Smuzhiyun #define X86_CR4_PAE_BIT 5 /* enable physical address extensions */ 102*4882a593Smuzhiyun #define X86_CR4_PAE _BITUL(X86_CR4_PAE_BIT) 103*4882a593Smuzhiyun #define X86_CR4_MCE_BIT 6 /* Machine check enable */ 104*4882a593Smuzhiyun #define X86_CR4_MCE _BITUL(X86_CR4_MCE_BIT) 105*4882a593Smuzhiyun #define X86_CR4_PGE_BIT 7 /* enable global pages */ 106*4882a593Smuzhiyun #define X86_CR4_PGE _BITUL(X86_CR4_PGE_BIT) 107*4882a593Smuzhiyun #define X86_CR4_PCE_BIT 8 /* enable performance counters at ipl 3 */ 108*4882a593Smuzhiyun #define X86_CR4_PCE _BITUL(X86_CR4_PCE_BIT) 109*4882a593Smuzhiyun #define X86_CR4_OSFXSR_BIT 9 /* enable fast FPU save and restore */ 110*4882a593Smuzhiyun #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) 111*4882a593Smuzhiyun #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ 112*4882a593Smuzhiyun #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) 113*4882a593Smuzhiyun #define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ 114*4882a593Smuzhiyun #define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) 115*4882a593Smuzhiyun #define X86_CR4_LA57_BIT 12 /* enable 5-level page tables */ 116*4882a593Smuzhiyun #define X86_CR4_LA57 _BITUL(X86_CR4_LA57_BIT) 117*4882a593Smuzhiyun #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ 118*4882a593Smuzhiyun #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) 119*4882a593Smuzhiyun #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ 120*4882a593Smuzhiyun #define X86_CR4_SMXE _BITUL(X86_CR4_SMXE_BIT) 121*4882a593Smuzhiyun #define X86_CR4_FSGSBASE_BIT 16 /* enable RDWRFSGS support */ 122*4882a593Smuzhiyun #define X86_CR4_FSGSBASE _BITUL(X86_CR4_FSGSBASE_BIT) 123*4882a593Smuzhiyun #define X86_CR4_PCIDE_BIT 17 /* enable PCID support */ 124*4882a593Smuzhiyun #define X86_CR4_PCIDE _BITUL(X86_CR4_PCIDE_BIT) 125*4882a593Smuzhiyun #define X86_CR4_OSXSAVE_BIT 18 /* enable xsave and xrestore */ 126*4882a593Smuzhiyun #define X86_CR4_OSXSAVE _BITUL(X86_CR4_OSXSAVE_BIT) 127*4882a593Smuzhiyun #define X86_CR4_SMEP_BIT 20 /* enable SMEP support */ 128*4882a593Smuzhiyun #define X86_CR4_SMEP _BITUL(X86_CR4_SMEP_BIT) 129*4882a593Smuzhiyun #define X86_CR4_SMAP_BIT 21 /* enable SMAP support */ 130*4882a593Smuzhiyun #define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT) 131*4882a593Smuzhiyun #define X86_CR4_PKE_BIT 22 /* enable Protection Keys support */ 132*4882a593Smuzhiyun #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* 135*4882a593Smuzhiyun * x86-64 Task Priority Register, CR8 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun #define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 140*4882a593Smuzhiyun * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* 144*4882a593Smuzhiyun * NSC/Cyrix CPU configuration register indexes 145*4882a593Smuzhiyun */ 146*4882a593Smuzhiyun #define CX86_PCR0 0x20 147*4882a593Smuzhiyun #define CX86_GCR 0xb8 148*4882a593Smuzhiyun #define CX86_CCR0 0xc0 149*4882a593Smuzhiyun #define CX86_CCR1 0xc1 150*4882a593Smuzhiyun #define CX86_CCR2 0xc2 151*4882a593Smuzhiyun #define CX86_CCR3 0xc3 152*4882a593Smuzhiyun #define CX86_CCR4 0xe8 153*4882a593Smuzhiyun #define CX86_CCR5 0xe9 154*4882a593Smuzhiyun #define CX86_CCR6 0xea 155*4882a593Smuzhiyun #define CX86_CCR7 0xeb 156*4882a593Smuzhiyun #define CX86_PCR1 0xf0 157*4882a593Smuzhiyun #define CX86_DIR0 0xfe 158*4882a593Smuzhiyun #define CX86_DIR1 0xff 159*4882a593Smuzhiyun #define CX86_ARR_BASE 0xc4 160*4882a593Smuzhiyun #define CX86_RCR_BASE 0xdc 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 163*4882a593Smuzhiyun X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 164*4882a593Smuzhiyun X86_CR0_PG) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */ 167