1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef _ASM_X86_PERF_REGS_H 3*4882a593Smuzhiyun #define _ASM_X86_PERF_REGS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun enum perf_event_x86_regs { 6*4882a593Smuzhiyun PERF_REG_X86_AX, 7*4882a593Smuzhiyun PERF_REG_X86_BX, 8*4882a593Smuzhiyun PERF_REG_X86_CX, 9*4882a593Smuzhiyun PERF_REG_X86_DX, 10*4882a593Smuzhiyun PERF_REG_X86_SI, 11*4882a593Smuzhiyun PERF_REG_X86_DI, 12*4882a593Smuzhiyun PERF_REG_X86_BP, 13*4882a593Smuzhiyun PERF_REG_X86_SP, 14*4882a593Smuzhiyun PERF_REG_X86_IP, 15*4882a593Smuzhiyun PERF_REG_X86_FLAGS, 16*4882a593Smuzhiyun PERF_REG_X86_CS, 17*4882a593Smuzhiyun PERF_REG_X86_SS, 18*4882a593Smuzhiyun PERF_REG_X86_DS, 19*4882a593Smuzhiyun PERF_REG_X86_ES, 20*4882a593Smuzhiyun PERF_REG_X86_FS, 21*4882a593Smuzhiyun PERF_REG_X86_GS, 22*4882a593Smuzhiyun PERF_REG_X86_R8, 23*4882a593Smuzhiyun PERF_REG_X86_R9, 24*4882a593Smuzhiyun PERF_REG_X86_R10, 25*4882a593Smuzhiyun PERF_REG_X86_R11, 26*4882a593Smuzhiyun PERF_REG_X86_R12, 27*4882a593Smuzhiyun PERF_REG_X86_R13, 28*4882a593Smuzhiyun PERF_REG_X86_R14, 29*4882a593Smuzhiyun PERF_REG_X86_R15, 30*4882a593Smuzhiyun /* These are the limits for the GPRs. */ 31*4882a593Smuzhiyun PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, 32*4882a593Smuzhiyun PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* These all need two bits set because they are 128bit */ 35*4882a593Smuzhiyun PERF_REG_X86_XMM0 = 32, 36*4882a593Smuzhiyun PERF_REG_X86_XMM1 = 34, 37*4882a593Smuzhiyun PERF_REG_X86_XMM2 = 36, 38*4882a593Smuzhiyun PERF_REG_X86_XMM3 = 38, 39*4882a593Smuzhiyun PERF_REG_X86_XMM4 = 40, 40*4882a593Smuzhiyun PERF_REG_X86_XMM5 = 42, 41*4882a593Smuzhiyun PERF_REG_X86_XMM6 = 44, 42*4882a593Smuzhiyun PERF_REG_X86_XMM7 = 46, 43*4882a593Smuzhiyun PERF_REG_X86_XMM8 = 48, 44*4882a593Smuzhiyun PERF_REG_X86_XMM9 = 50, 45*4882a593Smuzhiyun PERF_REG_X86_XMM10 = 52, 46*4882a593Smuzhiyun PERF_REG_X86_XMM11 = 54, 47*4882a593Smuzhiyun PERF_REG_X86_XMM12 = 56, 48*4882a593Smuzhiyun PERF_REG_X86_XMM13 = 58, 49*4882a593Smuzhiyun PERF_REG_X86_XMM14 = 60, 50*4882a593Smuzhiyun PERF_REG_X86_XMM15 = 62, 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* These include both GPRs and XMMX registers */ 53*4882a593Smuzhiyun PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2, 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* _ASM_X86_PERF_REGS_H */ 59