1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_X86_XOR_64_H 3*4882a593Smuzhiyun #define _ASM_X86_XOR_64_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun static struct xor_block_template xor_block_sse = { 6*4882a593Smuzhiyun .name = "generic_sse", 7*4882a593Smuzhiyun .do_2 = xor_sse_2, 8*4882a593Smuzhiyun .do_3 = xor_sse_3, 9*4882a593Smuzhiyun .do_4 = xor_sse_4, 10*4882a593Smuzhiyun .do_5 = xor_sse_5, 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Also try the AVX routines */ 15*4882a593Smuzhiyun #include <asm/xor_avx.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* We force the use of the SSE xor block because it can write around L2. 18*4882a593Smuzhiyun We may also be able to load into the L1 only depending on how the cpu 19*4882a593Smuzhiyun deals with a load to a line that is being prefetched. */ 20*4882a593Smuzhiyun #undef XOR_TRY_TEMPLATES 21*4882a593Smuzhiyun #define XOR_TRY_TEMPLATES \ 22*4882a593Smuzhiyun do { \ 23*4882a593Smuzhiyun AVX_XOR_SPEED; \ 24*4882a593Smuzhiyun xor_speed(&xor_block_sse_pf64); \ 25*4882a593Smuzhiyun xor_speed(&xor_block_sse); \ 26*4882a593Smuzhiyun } while (0) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* _ASM_X86_XOR_64_H */ 29